Reconfigurable Parameters Setup

The proposed design has been detailed in previous sections; this section describes the way to reconfigure the parameters of the proposed design in tabular form. Table 5.5 lists the I/O interface of the proposed design. Table 5.6, identical to Table 3.3, lists again the possible SW combination schemes of the proposed design.

Table 5.7 and Table 5.8 give some examples to configure the kill and mode signals, respectively. Some points or exception to be noticed are list as notes at the bottom of each Table.

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Table 5.5. Interface of the proposed design.

MAC Scalar 16-bit 32-bit 64-bit MULTIPLICAND mcand[N-1:0] mcand[15:0] mcand[31:0] mcand[63:0]

MULTIPLIER mlier[N-1:0] mlier[15:0] mlier[31:0] mlier[63:0]

ACCUMULATOR accu[2N-1:0] accu[31:0] accu[63:0] accu[127:0]

MODE ^mode[1:0] mode_v0[1:0] RESULT m_out[2N-1:0] m_out[31:0] m_out[63:0] m_out[127:0]

CARRY-OUT cout cout_v0 cout Note: N is the bit width of scalar input operands

Note: v0, v1, …, v7 indicate SWs in order; v7 aligns to MSB; v0, LSB Note: For all MODE signal: 1?: mixed-mode; 00: unsigned; 01: signed Note: kill is inserted between SWs; kill2 between v2 and v3, and the like

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Table 5.6. Possible sub-word combinations of the proposed SWP MAC design.

A 64-bit SWP MAC is viewed consisting of two independent 32-bit SWP MACs; it then has 5×5 = 25 possible combinations

Table 5.7. Configuration example of KILL signal.

KILL kill6 kill5 kill4 kill3 kill2 kill1 kill0

Note: List only some possible conditions

Note: An illegal input will be redirected to scalar mode by default

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Table 5.8. Configuration example of MODE signal.

MODE ^{SW_7 SW_6 SW_5 SW_4 SW_3 SW_2 SW_1 SW_0} 16-bit SWP MAC

(16) N/A N/A N/A N/A N/A N/A ○ ╳ (8,8) N/A N/A N/A N/A N/A N/A ○ ○ 32-bit SWP_MAC

(32) N/A N/A N/A N/A ○ ╳ ╳ ╳ (16,16) N/A N/A N/A N/A ○ ╳ ○ ╳ (8,8,8,8) N/A N/A N/A N/A ○ ○ ○ ○ (8,8,16) N/A N/A N/A N/A ○ ○ ○ ╳ 64-bit SWP MAC

(64) ○ ╳ ╳ ╳ ╳ ╳ ╳ ╳

(32,32) ○ ╳ ╳ ╳ ○ ╳ ╳ ╳ (16,16,16,16) ○ ╳ ○ ╳ ○ ╳ ○ ╳ (8,8,8,8,8,8,8,8) ○ ○ ○ ○ ○ ○ ○ ○ (16,16,32) ○ ╳ ○ ╳ ○ ╳ ╳ ╳ (8,8,8,8,32) ○ ○ ○ ○ ○ ╳ ╳ ╳ (8,8,16,32) ○ ○ ○ ╳ ○ ╳ ╳ ╳

○: Configurable

╳: Can't configure;should be identical with the nearest ○ on the left side Note: Incorrect assignment of mode may cause a wrong result

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C ^HAPTER 6 C ^ONCLUSIONS

In this thesis, we present the design methodology of a high-performance reconfigurable modified Booth encoded MAC unit. It is capable of supporting sub-word parallel (SWP) operation which enhances computational throughput of many DSP algorithms especially for multimedia applications. The scalar version of the proposed design comprises a high-speed, area-reduced, and race-free MBE; a speed optimized Wallace PPRT using TDM; and a high speed, area-minimized Fong adder. Using essentially the same hardware, SWP is performed on the scalar MAC by applying some preprocessing to operands associated with a new arrangement of the SWPPA, and with the support of carry-chain blocking when accumulating all partial products. A novel full-adder carry-out masking concept is proposed to build the SWPPRT, facilitating the use of TDM. The SWP version Fong adder inherits its scalar merits and supports identical SW combinations with our requirement. The proposed SWP design innovatively features the flexible sub-word combination and mode assignment scheme with nearly same delay and modest area overhead compared with the proposed scalar design. The proposed designs are fully-synthesizable in a reusable and verifiable design style. Experimental results demonstrate that the proposed scalar and SWP designs, for most cases, outperform the designs of DesignWare® IP [38] and of [10] in terms of critical path delay, area cost, and power consumption.

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F ^UTURE W ^ORKS

We are developing a generator to generate the RTL codes of the proposed MAC designs in Verilog HDL format. Testbench for verification, synthesis script, and user’s manual will also be generated. All output files depend on the user reconfigurable inputs. We are also analyzing the pros and cons of replacing the scalar MAC units in multiple-MAC DSP processors by a proposed SWP MAC in order to design a high-performance MAC unit.

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