In order to make a-Si:H TFTs suitable for advanced circuits, besides the improvement of performance of a-Si:H TFTs, the improvement of reliability is also significant. Therefore, reliability testing and understanding of reliability mechanisms become more and more necessary.
1.2.1 DC stress
As mentioned in introduction, the creation of extra defect states in the band gap of a-Si:H and the charge trapping in the SiNx gate dielectric had been reported to be the two main mechanisms that can explain the electrical instabilities of a-Si:H TFTs.
For transistors made with a siliconnitride gate insulator, the threshold voltage shift for low positive gate-bias is due to dangling-bond-state creation in the amorphous silicon layer. But in recent research, for low negative gate-bias, the threshold voltage shift is dominated by the bias-stress-induced removal of dangling-bond states. This is because the zero-bias Fermi energy position in nitride transistors are near the conduction band [14].
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Fig.1-1. Evolution of Id-Vg characteristics with various bias stress times.
[Jpn. J. Appl. Phys. Vol. 37, pp.4706, 1998.]
Fig.1-1. [15] shows the evolution of ID-VG characteristics for a regular a-Si:H TFTs under +20V and -20V steady-state gate-bias stress. As can be seen in this figure, an apparent right shift was obtained for the IV characteristics of +20V stress. From this report, Chiang et al. proposed the right shift was from the increase of the density of deep-gap states in a-Si:H, and also the charge trapping in the SiNx gate dielectric.
The combination of these two mechanisms caused an additive effect in the shift of electron conduction characteristics [15].
For -20V stress, the IV characteristics show an obvious left shift with little distortion of sub-threshold behavior. This result corresponded to a decrease of deep-gap states in the a-Si:H. Similarly to the positive stress, charge trapping was also present and the left shift was a combination of these two mechanisms [15].
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1.2.2 AC stress
In most applications, a-Si:H TFTs are operated under a pulsed gate-bias addressing. To understand the instability under AC bias stress is extremely important as well.
Fig.1-2. Evolution of Id-Vg characteristics induced by pulsed positive and negative gate bias stress. [Jpn. J. Appl. Phys. Vol. 37, pp.4707, 1998.]
Fig.1-2. [15] shows the evolution of ID-VG characteristics of a-Si:H TFTs during a positive and negative pulsed gate-bias stress with 50% duty-cycle and 10ms pulse-width at 70℃. Comparing with Fig. 1-1., it shows that, under positive gate-bias stress, pulsed and steady-state bias stress induced a similar evolution of IV characteristics. However, the left shift IV characteristics induced by negative pulsed gate-bias stress was apparently smaller than that induced by steady-state gate bias stress.
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1.2.2.1 Pulse-Width Dependence
Fig.1-3. Threshold voltage shift (∆VT) versus effective stress time induced by positive and negative gate-bias stress with different gate pulse-width.
[Jpn. J. Appl. Phys. Vol. 37, pp.4707, 1998.]
Fig.1-3. [15] shows the threshold voltage shift (∆VT) versus effective stress time under both positive and negative bias-stress for different pulse conditions. The effective stress time was the accumulation time when the gate voltage was high. For positive pulsed gate-bias stress, ∆VT was slightly smaller than that for steady-state gate-bias stress and did not depend apparently on gate-bias pulse width. For negative pulsed gate-bias stress, ∆VT had strong pulse-width dependence- the wider the pulse width, the greater the magnitude of ∆VT.
From the same report [15], Chiang et al. proposed that, for positive pulsed gate-bias stress, during the OFF-cycle of the stress, some of the trapped charge and created states could be detrapped or relaxed. This could explain the smaller ∆VT of pulsed gate-bias stress than steady-state stress. Also, during the ON-cycle of positive
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pulsed gate-bias stress, there would be a fast electron channel accumulation. Since the accumulation speed of electrons was much faster than the pulse-width, it would have very small pulse-width dependence. In contrast to positive pulsed gate-bias stress, the accumulated carriers of negative pulsed gate-bias stress were holes. The accumulation speed of holes was much slower than that of electrons and even slower than the stress pulse-width. With low concentration of carriers (holes) accumulation, there would not be a large degradation of IV characteristics. And this was the reason why ∆VT had strong pulse-width dependence when performing negative pulsed stress. Libsch et al.
also proposed a RC time delay effect theory [16] to further explain this phenomenon.
1.2.2.2 Duty-Cycle Dependence
For duty-cycle dependence, Chiang et al. reported the following equations to describe the threshold voltage shift under pulsed gate-bias stress [15].
(1.1)
(1.2 )
(1.3)
Where VGH andVGL are the high and low gate-bias pulse-levels, respectively; VTi
is the initial threshold voltage,
t
st is the stress time, A-, A+,α
-,α
+, β-, β+ and FPW are constants, and Dc is the duty cycle of the stressing voltage.They proposed that the total threshold voltage shift ∆VT±(
t
st) could be composed of threshold voltage shift induced by positive stress ∆VT﹢(t
st) and the threshold voltage shift induced by negative stress ∆VT﹣(t
st). The voltage shift of each pulsed gate-bias stress could be expressed as the effective steady-state stress duty with a8
fitting constant β except the frequency limit of negative pulsed gate-bias stress caused by the slow holes accumulation. Fig.1-4. shows a satisfactory fit between the calculated and experimental data.
Fig.1-4. Threshold voltage shift (∆VT) versus stress time for positive and negative gate-bias stress with different duty-cycles.
[Jpn. J. Appl. Phys. Vol. 37, pp.4710, 1998.]