Routability Checking

In order to control package size in a reasonable size, Trackmax means the maximum track number. And Lmax means the maximum number of layers of this problem. If substrate routing can not achieve 100% routability, we will take following stratages:

First, if current track number is less than Trackmax, then increase track number. Second,

if current track number is equal to Trackmax, then increase the number of layers until it is equal to Lmax. Finally, if the number of layers is equal to Lmax, this means the package design with our constraints can not reach 100% routability.

Chapter 4

Experimental Results

Our algorithm was implemented in C++ programming language and tested on a Linux workstation with Core 4 Intel(R) Xeon(R) E5160 3.0 GHz and 32G RAM. We used five industry cases [12] to test our algorithm. The detailed information of each case is listed in TABLE 4.1. Note that, case 1 and case 5 have the same finger set, and case 2, case 3, and case 4 have the same finger set. The PCB components of all cases, however, are not identical to each other. There are at most four routing layers we can use.

Table 4.1: Detailed information of the test cases [12].

case1 case2 case3 case4 case5

# of signals 268 429 429 429 268

# of components 1 3 4 3 1

The experimental results listed in TABLE 4.2 and TABLE 4.3 are compared with the Cadb004 [12] and NTHU [13] specifically. In these tables, the package size and the number of BGA layer are used to evaluate total package cost; on the other hand, the total wirelength on BGA can represent the performance. In our algorithm, the execution time of each case is not more than 10 seconds. And all guarantee routablilty 100%.

Table 4.2: Experimental Results Compared with Cadb004 [12].

Table 4.3: Experimental Results Compared with NTHU [13].

Package Size Performance

L W Improvement

First, the results are compared with Cadb004. Cadb004 is the only one team that finished the five test cases of problem B3 in the 2008 IC/CAD Contest. The method of Cadb004 is sorting all signals and surrounding the chip with the signals one by one in a ring. Finally, the method applies the simple channel routing to route the signals.

Although this method must be success for routing and need only 2 layers to complete, it enlarges the package size and increases the total wirelength. The result shows: although there are one more layer be used, the package size and wirelength shrink much more than a half clearly.

Second, we compare our results with NTHU. NTHU constructed a network flow model and applied the Min-Cost-Max-Flow algorithm to solve this problem which can guarantee routability. In the case2, case3, and case4, the package size reduces 23%, the number of layers decreases one, and the wirelength reduces 9%~10%. Then in case1 and case5, we reduce the number of layers one, the package size is a little larger than NTHU, the number of layers decreases one but the wirelength increase 33% and 19%

respectively. In case2, case3, and case4, because the corner region of BGA is less assigned balls, the routing flow of each signal can easily go outward direction and can avoid routing to the corner region. Therefore, the results of these three cases can get better. On the other hand, the results of case1 and case5, the bump balls on BGA are almost filled; therefore, this increases the routing difficulty and cause the package size and total wirelength increase.

Chapter 5

Conclusions

In this thesis, we propose a package design flow for the chip-package-board co-design flow. At first stage, we propose a new pin assignment algorithm considering the differential pair signals and IR-drop. With this algorithm, the whole routing space can be used more efficiently. Then at second stage, the cost function of A* algorithm and routing order effectively increases the routability and reduces the total number of layers.

The experimental results show that our methodologies improve the package size, and the total wirelength to at least 50% while increasing the number of layers by one.

Then while compared with NTHU, if the corner region on BGA package is sparse, our methodologies guarantee routability and effectively reduce the number of layers, total wirelength while controling the package size in a reasonable one. Otherwise, if the corner region on BGA package is dense, the wirelength and the package size do not be improved while the number of layers still reduces to three.

In this thesis, the given information is just component pins, differential pair signals, power/ ground signals and the wire segments can just be horizontal or vertical. In the future, we want to implement one any-angle substrate routing and propose a cost function which considering the issue of the pin assignment in order to make the pin assignment more convincing.

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