CHAPTER 3 DESIGN OF ADC CALIBRATION
3.3 S TATISTICAL A NALYSIS [17]-[19]
3.3.3 Samples and Accuracy
The number of samples and input signal amplitude are dependent with the accuracy of selecting comparators. For example, the larger the signal amplitude, the denser duty cycles at comparator outputs due to sharper waveform for a periodic frequency. As a consequence, we must have more samples to keep the same distinguishing ability. In accordance with statistics as we mentioned in previous sections, every sampling can be treated as Bernoulli trial, and successive Bernoulli trials are binominal random variables. Each comparator has its duty cycle as binominal variables in the estimation.
We are interested in how many samples and the confidence level we need for the conversion. More samples imply higher accuracy, but more hardware and
calibration time. Obviously they are trade-off. For a given signal, we evaluate the number of samples to maintain a certain confidence level so that we can select the optimal comparators. We configure the threshold gap of 40mV in the comparator array. It means that we have a resolution of 40mV. From table 3.2, for an input of 300mV swing, we can have over 99.35% confidence level in a 7-bit counter.
Meanwhile, it equals that 95.45% confidence level for a 400mV swing. When the number of samples is larger, calibration time becomes longer and accuracy rises significantly.
Variance σ2= 1/4
accuracy ε x Q(x) N-bit timer # of samples confidence level
4.53 1.181E-05 5 32 100.00%
6.4 4.422E-10 6 64 100.00%
9.05 5.855E-19 7 128 100.00%
12.8 9.798E-37 8 256 100.00%
18.1 2.648E-72 9 512 100.00%
25.6 1.88E-143 10 1024 100.00%
36.2 9.33E-286 11 2048 100.00%
2.26 0.0227664 5 32 95.45%
3.2 0.0018694 6 64 99.63%
4.53 1.181E-05 7 128 100.00%
6.4 4.422E-10 8 256 100.00%
9.05 5.855E-19 9 512 100.00%
12.8 9.798E-37 10 1024 100.00%
18.1 2.648E-72 11 2048 100.00%
1.51 0.0881241 5 32 82.38%
2.13 0.0299467 6 64 94.01%
3.02 0.0032689 7 128 99.35%
4.27 3.652E-05 8 256 99.99%
6.03 4.273E-09 9 512 100.00%
8.53 5.515E-17 10 1024 100.00%
12.1 8.756E-33 11 2048 100.00%
1.13 0.1388265 5 32 72.23%
1.6 0.0771742 6 64 84.57%
2.26 0.0227664 7 128 95.45%
3.2 0.0018694 8 256 99.63%
4.53 1.181E-05 9 512 100.00%
6.4 4.422E-10 10 1024 100.00%
9.05 5.855E-19 11 2048 100.00%
0.75 0.1884185 5 32 62.32%
1.07 0.1478554 6 64 70.43%
1.51 0.0881241 7 128 82.38%
2.13 0.0299467 8 256 94.01%
3.02 0.0032689 9 512 99.35%
4.27 3.652E-05 10 1024 99.99%
6.03 4.273E-09 11 2048 100.00%
40/400 40/300 40/100
40/200
40/600
(Accuracy ε here is the ratio of threshold gap over input signal amplitude) Table 3.2 Estimation of samples and confidence level
Chapter 4
Simulation Results
We are going to discuss simulation results, specification comparison, and layout in this chapter. Simulation results include comparator corners, ADC output, and calibration results. We will check the ADC output before CDR processing and analyze the calibration result. Further more, we will make a specification comparison.
4.1 Threshold Comparator
4.1.1 Threshold Comparator Corners
Conversion range of comparator is set from 600mV to 1200mV. In Figure 4.1, FF case has the sharpest slope, and it means the dynamic range becomes wider for signal coverage. Because the number of comparators does not increase, obviously the threshold gap becomes wider and resolution deteriorates. In contrast, dynamic range of SS corner decreases, but resolution improves. That is to say, the accuracy is getting better in self-calibration. Another in SF case, the dynamic range shifts upward due to strong PMOS. FS case is on the opposite way, but both resolutions are the same as TT case. The calibration automatically selects the threshold comparators closet to center of the eye diagram, so we can avoid process variation impact to the accuracy through calibration.
Comparator threshold corner simulation
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Wp/Wn Vth
Vth_FF Vth_FS Vth_TT Vth_SF Vth_SS
Figure 4.1 Comparator threshold corner
4.1.2 Gain Boosting
We mentioned that the inverter based MUX has gain boosting effects in previous chapter. In Figure 4.2, an initial input is amplified stage by stage from 100mV to 1300mV, and biased at DC level of 0.9V. Besides, we can see a light transition overshoot due to inductive peaking in the eye diagram.
S 0[2:0] S 1[2:0] S 2[2:0]
S 0[2:0] S 1[2:0] S 2[2:0]
A B C D
A B C D A B C
Figure 4.2 Gain boosting of TIQ ADC
4.2 ADC Simulation
4.2.1 2.5Gsps 4-PAM Input
We input a 2.5Gsps 4-PAM signal of 600mV swing to TIQ ADC through a fading channel by RC model. The ADC input waveform is simulated as shown in Figure 4.3. We extract three best channels out of three threshold levels from the simulations. The best channels have at least 0.5 unit interval (UI) eye-opening of 400ps period at the ends of outputs as shown in Figure 4.4.
Figure 4.3 2.5Gsps 4-PAM signal
Figure 4.4 TIQ ADC output of 4-PAM input D2: Ch_11
Eye width: 225ps
D1: Ch_8
Eye width: 215ps
D0: Ch_3
Eye width: 260ps
4.2.2 2.5Gbps Pseudo Random Binary Sequence
(PRBS) Input
We input PRBS of different level to replace 4-PAM, and get the three best eye-diagrams of ADC output as shown in Figure 4.5. The eye-openings are more than 330ps in the post simulation.
D2: Ch_13 Eye width: 300ps
D1: Ch_8
Eye width: 326ps
D0: Ch_2
Eye width: 360ps
Figure 4.5 TT case of TIQ ADC output of PRBS input
Figure 4.6 shows the FF case of PRBS input, and it has wider eyes than those of TT case. Threshold gap becomes wider in FF case, so the channels of best eyes are getting closer.
D2: Ch_13 Eye width: 338ps
D1: Ch_8
Eye width: 350ps
D0: Ch_3
Eye width: 375ps
Figure 4.6 FF corner of TIQ ADC output of PRBS input
SS case as shown in Figure 4.7 stands opposite to FF case. The jitter grows due to slow transition, and outer channels for better eye-diagrams. Even though, the eye-opening is still enough for a CDR system.
D2: Ch_14 Eye width: 246ps
D1: Ch_8
Eye width: 293ps
D0: Ch_1
Eye width: 326ps
Figure 4.7 SS corner of TIQ ADC output of PRBS input
4.3 Calibration Simulation
For the sake of calibration verification, we simulate an 80MHz triangular input as fast as our available function generator. In Figure 4.8, we can see the calibrated channels of threshold levels and data outputs accordingly. With respect to Table 4.1, the selected threshold comparators are very close to ideal threshold voltages of eye center, and so do the duty cycles.
LS1
LS0
Lev 2
Lev 1
Lev 0
D2
D1
D0
CH 4 CH 7 CH 11
Level 0 Level 1 Level 2
Duty: 26%
Duty: 51%
Duty: 71%
Figure 4.8 Calibration simulation of triangular input
345Msps 0.6~1.2V Ideal Vth Channel Vth duty%
Level 2 1.05 11 1.04 26%
Level 1 0.9 7 0.88 51%
Level 0 0.75 4 0.76 71%
80MHz triangular
Table 4.1 Calibration summary Corner Level 0 Level 1 Level 2
FF CH4 CH7 CH8
TT CH4 CH7 CH11
SS CH3 CH7 CH12
Table 4.2 Corner cases calibration result
Further more, we compare the calibration resulting different corners as shown in Table 4.2. As we expect, FF case has wider conversion range, so it selects the closer channels as compare with other corners. In contrast, SS case selects the outer comparators.
4.4 Layout
The PAM receiver was fabricated in a six-level metal single poly 0.18um CMOS process. The layout of this chip is shown in Figure 4.9. The core area is
2( 111
0. mm 370um 300× um), while the total area is ( ).
The pads close to the circuit layout are configured for high-speed I/Os, however, the pads far away are designated for control pins. The rest area is filled up with decouple capacitance in order to bypass power noise.
25 2
.
1 mm 1120um 1120× um
1120 um
1120 um
Figure 4.9 Layout of self-calibrating 4-PAM receiver
4.5 Specification Comparison
As shown in Table 4.5, this specification falls into two categories: normal mode and calibration mode. In normal operation, we get eye-openings over 0.75UI for PRBS source and 0.5UI for 4-PAM source. The power dissipation is only 3.2mW and 4.2mW for 2.5Gbps PRBS and 2.5Gsps 4-PAM input respectively. While operating in calibration mode, it consumes 3.9mW at 345MHz sampling rate, and 5.16mW in the worst case. Notice that the power consumption of calibration can be reduced by decreasing sampling rate.
Item Spec (Normal) Spec (Calibration)
Supply Voltage 1.8V
2.5Gbps PRBS
Input 80 MHz Triangular
2.5Gsps 4PAM
PRBS jitter 100ps@ 2.5Gbps N/A 4-PAM jitter 190ps@ 2.5Gsps N/A Power consumption 3.2mW @ 2.5Gbps PRBS
4.2mW @ 2.5Gsps 4PAM
3.9mW @ 345MHz CLK 5.16mW @ FF
Core area 0.111mm 2
Table 4.3 Performance summary
In Table 4.4, figure of merit (FOM) shows the comparison with the other high-speed ADCs. For the convenience of comparison at the same level, we scale up to 6bit and 8bit to obtain estimated 67mW and 268mW power respectively at 2.5Gsps.
Obviously, this work has least power consumption based on the same resolution, and the second minimum area.
ADC Process Resolution Speed Power Area Year TIQ [4] 0.25um 6bit 1Gsps 44mW 0.013mm2 2001 PRA-TIQ [20] 0.18um 6bit 2.66Gsps 97mW 0.218mm2 2004 Flash [21] 0.25um 6bit 1.3Gsps 600mW 0.12mm2 2003 Folding [22] 0.18um 8bit 1.6Gsps 774mW 3.6mm2 2004 Proposed 0.18um 2bit 2.5Gsps 4.2mW 0.11mm2 2006
Table 4.4 FOM comparison
Chapter 5
Measurement Considerations
In this chapter, we divide testing method into two parts: one is 4-PAM test, and the other is binary test. First, we introduce measurement considerations, inclusive of chip function implementation, and test configuration. Second, we illustrate how to generate signal sources in two ways: on-chip and off-chip test. Last, we describe both test flows.
5.1 Test Setup
5.1.1 Measurement Configurations
The test configuration is shown in Figure5.1 and we illustrate the purpose of each instrument. Power supply enables this chip, and pulse data generator provides stimulus input up to 5Gbps data rate. Dual-in-line (DIP) switches are used for channel selection, and switching mode. By a wide-band oscilloscope, we can observe the high-speed performance of ADC. Meanwhile, logic analyzer helps to check the calibrated channels and state. There is still an alternative way to measure channel characteristics by serial BERT. It stimulates the ADC and measures bit error rate (BER) with a feedback. [23]
Input
Figure 5.1 Measurement setup
5.1.2 Test Considerations
We illustrate the measure purpose of each pin, and explain what we want to observe as below:
1. MUX output: D [2:0]
These are the output signals of some channels of some channels after a series of gain boosting. We judge if it is clear enough to operate in 2.5GHz or even higher after clocked data recovery (CDR), and observe ISI jitter.
2. DFF output: Q [2:0]
These points are designated to observe the duty cycle after asynchronously random sampling. The sampled signal has only clock jitter, but no ISI jitter.
3. Level output: Lev [2:0]
These pins tell us which channel of each level we select by switching level select signal LS [1:0].
4. State machine: State [2:0]
By probing these pins, we realize current state of the system, and debug easier.
5. Manual channel select: MS [8:0]
In the system measurement, we can manually control the channel for calibration verification. We measure not only BER, but also eye-diagram.
6. Level select: LS [1:0]
To observe the selected channels, we switch it for three levels.
7. Auto:
It is a control pin for MUX switch interface. It enables for self-calibration, or disables for manual control otherwise.
5.2 Signal Sources
In this section, we introduce two methods to generate signal for test. One is a built-in circuit for both 4-PAM and binary signal sources, and the other is an off-chip solution.
5.2.1 On-chip Solution
This self-generating signal source consists of linear feedback shift registers (LFSR), multiplexers, logic gates, and a 2-bit current mode digital-to-analog converter (DAC) in the circuitry which is shown in Figure 5.2. It generates not only 4-PAM signal, but also PRBS signal. The PRBS generated by LFSR is fed into binary-to-thermometer decoder via MUX to control the gates of current mode DAC for 4-PAM signal. We insert control logics between LFSR and MUX for different level binary signals.
The current mode DAC can generate high-speed signal, but drain a great deal of current. By switching on the gates, it sinks more current and lowers the output voltage.
For our specification, its output swing ranges from 600mV to 1200mV and speed is up to 2.5Gsps. To consider the termination, the pull-up load is 50 ohm. The schematic of 2-bit current mode DAC is shown in Figure 5.3.
Table 5.1 is the code table of switching patterns. As shown in Figure 5.4, the eye of 2.5Gsps 4-PAM signal is wide-open. Figure 5.5 shows self-generating 2.5Gbps PRBS of various levels.
16-bit LFSR
2-bit Current Mode DAC
G [3:1] 3
Figure 5.2 Block diagram of signal generator
50 Ω
Figure 5.3 Schematic of 2-bit current mode DAC
Pattern 4-P M PRBS_0 PRBS_1 PRBS_2 PRBS_F A
SW 0 1 1 1 1
S1 X 0 0 1 1
S0 X 0 1 0 1
Table 5.1 Signal generator switching code table
Figure 5.4 Self-generating 2.5Gsps 4-PAM signal
PRBS_F
PRBS_2
PRBS_1
PRBS_0
Figure 5.5 Self-generating 2.5Gbps PRBS signal
5.2.2 Off-chip Solution
There still an alternative way to generate 4-PAM signal by analog MUX inputs attached to resistor ladder. We can apply high-speed analog MUX and make random switches for random 4-PAM signal as shown in Figure 5.6. The key spec summary of analog MUX is shown in Table 5.2.
LMH 6574
Pulse PRBS VIN
Figure 5.6 Off-chip 4-PAM generator
Parameter Description Condition Typ. value Unit
-3dB BW -3dB BW Vout =0.5Vpp 500 MHz
0.1dB BW 0.1 dB BW Vout = 0.25Vpp 150 MHz
SR Slew Rate 4V step 2200 V/us
T Channel
switching time
Logic transition to 90% output
8 ns
RS
OS Overshoot 2V step 5 %
Table 5.2 NS LMH6574 spec summary
5.3 Test Flow
Figure 5.7 Test flow of 4-PAM Input
5.3.2 Test Flow of Binary Input
If we do not have 4-PAM source, there is an alternative way to replace 4-PAM with binary signal. First, it is fed with a PRBS which represents the lowest eye of 4-PAM signal while switching to calibration mode. After a period of calibration, we will get the selected channel number of the level. Record it and repeat the same procedure for the rest levels.
Second, we switch to normal mode when complete calibration is done, and feed the lowest binary sequence again and scan channels. It tells which channel is the best either by BER analysis or eye-diagram comparison. Last, we check the other two levels iteratively. The test flow is shown in Figure 5.8.
BEGIN
increment &
Record
Figure 5.8 Test flow of binary input
Chapter 6 Conclusion
In this thesis, we have proposed an ADC with advantages of simple structure, high-speed, power-efficient, low hardware overhead, and immunity against process variation and temperature. We use tri-state inverters as comparator and building up multiplexers for the merit of power saving and gain and gain boosting. By proper overlap between comparators and multiplexers, we can enhance the accuracy of conversion. Because the threshold comparators are deeply impacted by process variation, we use an undersampling scheme for calibration. By means of duty cycle estimation, we can choose optimal comparators and channels for conversion. The numbers of sampling are evaluated by statistical analysis. For example, we can get 99.35% confidence level for a 300mV peak to peak input out of a 7-bit counter to acquire the best channels.
In verification, we propose PRBS and 4-PAM test. PRBS is a simpler way for data acquisition, but the test flow is more complicated for the three-eye iteration. As for 4-PAM source, we have on-chip and off-chip solutions. On-chip signal solution is a self-generating signal by LFSR and DAC. On the other hand, off-chip solution is configured as a resistor-ladder type DAC through a high slew rate analog MUX.
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Autobiography
I was born in Taichung and raised in a traditional family. After graduating from National Central University, I went to military service as a lieutenant officer. I had learned responsibility and led staffs to achieve missions.
My first job was a hardware engineer, developing switch hubs. Later I went on to devote myself to semiconductor field as a product engineer, dealing with yield improvement and new product verification. Being aggressive by nature, I had achieved some goals that other people could not. For instance, I was the youngest qualified statistical process control seed, and quality innovation team leader. Needless to say, team work spirit is important. I have cooperated with others to solve problems, such as shooting defective sources with integration staffs, and working out the returned parts with quality assurance staffs. I also applied Taguchi method and statistical analysis to improve product and testing quality.
Years later, I went back to campus for advance study, majoring in electric engineering and concentrating on integrated circuits design. My project is to make a 2.5Gsps self-calibrating 4-PAM receiver, and evaluate the accuracy by statistical method. During these years, I do appreciate my professor directs me both philosophy and profession. There goes an old saying: “No pain, no gain!” I will devote to work enthusiastically and extend my width and depth aggressively.