Schottky contact

The ideal energy diagram for a particular metal and n-type semiconductor before marking contact is shown in Fig.2.1. The vacuum level is a reference level. The parameter

φ

_m is the metal work function (measured in volts),

φ

_s is the semiconductor

work function, and χ is known as the electron affinity. We have assumed that

φ

_m >

φ

_s.

Before contact, the Fermi level in the semiconductor was above that in the metal. In order for the Fermi level to become a constant through the system in the thermal equilibrium, electrons from the semiconductor flow into the lower energy states in the metal.

Positively charged donor atoms remain in the semiconductor, creating a space charge region. [1]

Fig. 2.1 Energy-band diagram of a metal and semiconductor before contact

8

After contact, the ideal energy-band diagram of a metal-n -semiconductor junction for

φ

m >

φ

s is shown in Fig.2.2. The parameter

φ

BO is the ideal barrier height of the semiconductor contact, the potential barrier seen by electrons in the metal trying to move into the semiconductor.

The barrier is known as the Schottky barrier and is given, ideally, by

φ

_BO = (

φ

_m −

χ

) (2.1) On the semiconductor side, Vbi is the built-in potential barrier. The barrier, similar to the case of the pn junction, is the barrier seen by electrons in the conduction band trying to move into the metal. The built-in potential barrier is given by

V bi =

φ

BO −

φ

n (2.2) which makea slight function of the semiconductor doping, as was the case in a pn junction.[1-2]

Fig. 2.2 Ideal energy-band diagram of a metal- semiconductor junction for Фm >. Фs

9

2.2 Schottky barrier photodiodes

Schottky barrier photodiodes have been studied quite extensively and have also found application as ultraviolet detectors [3]. These devices reveal some advantages over p-n junction photodiodes: absence of high-temperature diffusion processes, fabrication simplicity, and high speed of response.

The current transport processes

The interface will form a barrier after particular metal and semiconductor making contact. This contact is a rectifying contact and is called for Schottky contact.

On the other hand, Ohmic contacts are not rectifying contacts and low-resistance junction providing conduction in both directions between the metal and semiconductor. The current transport in a metal-semiconductor junction is due mainly to majority carriers as opposed to minority carriers in a pn junction. The current can be transported in various ways under forward bias conditions as shown in Fig. 2.1.

The four processes are: (1) Emission of electrons from the semiconductor over the top of the barrier into the metal, (2) tunneling through the barrier , (3) generation-recombination, (4) Recombination in the neutral region [4]

Fig. 2.3 The mechanisms of current transport in forword-biased Schottky contect

10

There are various theories to describe the mechanism of electrons going through potential barrier. These mechanisms include diffusion, thermionic emission, and unified thermionic emission diffusion. It is now widely accepted that, for high-mobility semiconductors with impurity concentrations of practical interest, the thermionic emission theory appears to explain qualitatively the experimentally observed I –V characteristics.

The thermonic emission characteristics are derived by using the assumptions that the barrier height is much larger than kT, so that the Maxwell-Boltzmann approximation applies and that thermal equilibrium is not affected by this process. Fig.

2.4 shows the one-dimensional barrier with an applied forward-bias voltage Va and shows two electron current density components. The current J s→m is the electron current due to the flow of electron from the semiconductor into the metal, and the current J m→s is the electron current density due to the flow of electrons from the metal into semiconductor. The conventional current direction is opposite to the electron flow. The net current density in the metal-to-semiconductor junction can be written as:

J = J s→m −J m→s (2.3)

Fig. 2.4 Energy-band diagram of a forward-biased metal-semiconductor junction including the image lowering effect.

11

which is defined to be positive in the direction from the metal to the semiconductor.

We fine that

The parameter A^*is called the effective Richardson constant. Equation (2.4) can be written in the usual diode form as

where Jst is the reverse-saturation current density and is given by

⎟⎠

The equation is similar to the transport equation for p-n junctions. However, the expression for the saturation current densities is quite different.

12

2.3 Quantum Efficiency

External quantum efficiency η( 0 ≤ η ≤ 1 ) of a photodetector is the number of photoelectrons generated per incident photon that contributes to the detector current.

When many photons are incident, η is the ratio of the flux of generated electron-hole pairs that contribute to the detector current to the flux of incident photons [4,5]. The higher quantum efficiency the more electrons will be generated by incident photons.

The quantum Efficiency is defined as

η=(1−R)ζ[1−exp(−αd)]

(2.8) where R is the optical power reflectance at the surface, The first factor (1-R) represents the effect of reflection at the surface of the device. ζ is the fraction of electron-hole pairs that successfully avoid recombination at the material surface and contribute to the useful photocurrent, α the absorption coefficient of the material (cm^-1), and d the photodetector depth. [1−exp(−αd)] is the fraction of the photon flux absorbed in the bulk of the material. The device should have a sufficiently large value of d to maximize this factor.

13

2.4 Responsivity

The definition of photodetector’s responsivity is the ratio of incident light power to induced photocurrent. the responsivity can be represented as

hv

where Iphoto is the photocurrent, and Φ is the photon flux. If every photon were to generate a single photoelectron ( η = 1 ), a photon flux would produce an electron flux , and then Iphoto = e Φ. A photon at frequency v has energy hv. Thus optical

(under constant power) because photoelectric detectors are responsive to the photon flux rather than to the optical power. As λ0 increases, a given optical power is carried by more photons, which, in turn, produce more electrons. Since the wavelength dependence of η comes into play for both long and short wavelengths, the region over which R increases with λ0 is limited.

14

2.5 Gain effect

The formulas presented above are predicated on the assumption that each carrier produces a charge e in the detector circuit. However, many devices produce a charge q in the circuit that differs from e [5]. Such devices are said to exhibit gain. The gain G is the average number of circuit electros generated per photocurrent pair. G should be distinguished from η, which is the probability that an incident photon produces a detectable photocurrent pair. The gain, which is defined as

e

G= (2.11) q

can be either greater than or less than unity. Therefore, more general expressions for the photocurrent and responsivity are

hv

The responsivity of a photoconductor is given by (2.13). The device exhibits an internal gain which, simply viewed, comes about because the recombination lifetime and transit time generally differ. Suppose that electrons travel faster than holes and that the recombination lifetime is very long. As the electron and hole are transported to opposite sides of the photoconductor, the electron completes its trip sooner than the hole. The requirement of current continuity forces the external circuit to provide another electron immediately, which enters the device from the wire at the left. This

15

new electron moves quickly toward the right, again completing its trip before the hole reaches the left edge. This process continues until the electron recombines with the hole. A single photon absorption can therefore result in an electron passing through the external circuit many times. The expected number of trips that the electron makes before the process terminates is [7]

e

G τ

= τ (2.14)

Where τ is the excess-carrier recombination lifetime and τeis the electron transit time across the sample. The charge delivers to the circuit by a single electron-hole pair in this case is q = G e＞e so that the device exhibits gain.

2.6 Detectivity

The specific detectivity D* is used to characterize performance of a photodetector. A more-sensitive detector has a larger detectivity than a less-sensitive detector. The definition of D* is

D* =

where e is the electronic charge, ηis the quantum efficiency, h is Planck’s constant, νis the frequency of the radiation, Ro is the dynamic resistance at zero bias, A is the detector area, k is Boltzman’s constant, and T is the absolute temperature [6].

The advantage of D* as a figure of merit is that it is normalized to an active detector area of 1cm²and noise bandwidth of 1Hz. Therefore, D* may be used to compared directly the merit of detectors of different size whose performance was measured using different bandwidths.

16

2.7 C-V measurement

Capacitance-Voltage (C-V) Measurement is one of the very basic measurements that can be done to characterize semiconductor devices. What is normally done is the device is hooked up to the instrument and C-V graphs are plotted and with that data we can conclude the type of device, whether it’s a p-type or an n-type device and many other parameters. The main aim of the C-V measurement is to extract the doping information of the diode.

The capacitance of a device is defined as

dV

C= dQ (2.15)

where dQ is the magnitude of the differential charge in charge on one plate as a function of the differential charge in voltage dV across the capacitor. For a MOS capacitor ,there are three operating conditions: accumulation, depletion, and inversion.

Fig. 2.5 (a) shows the energy-band diagram of an MOS capacitor with a p-type substrate for the case when a negative voltage is applied to the gate. A small differential change in voltage across the MOS structure will cause a differential charge in charge on the metal gate and also in the hole accumulation charge, as shown in Fig 2.5 (b), the capacitance C per unit area of the MOS capacitor for this accumulation mode just the oxide capacitance

ox ox ox

acc C t

C ε

=

= (2.16)

17

where Cox is the oxide capacitance per unit area ,and ε_ox ,t are the permittivity _ox and thickness of oxide, respectivity.

Fig. 2.5 (a) Energy-band diagram through an MOS capacitor for the accumulation mode. (b) Differential charge distribution at accumulation for a differential change in gate voltage.

In inversion condition, a positive voltage is applied to the gate, inducing a space charge region in the semiconductor. In the limit of very high frequency, the inversion layer charge will not respond to a differential charge in capacitor voltage. Fig 2.6(a) shows the energy-band diagram of the MOS device for this condition. Fig 2.6(b) illustrate the charge distribution through the device. A small differential change in voltage across the capacitor will cause a differential change in the space charge width.

The total capacitance of the serious combination is

s

Where Cs is the capacitance of semiconductor in the space charge width, and Cinv

is the total capacitance in inversion condition.

|dQ|

|dQ|

EF

EFi

18

Fig 2.6 (a) Energy-band diagram through an MOS capacitor for the inversion mode.(b) Differential charge distribution at inversion for a differential change in gate voltage.(high frequency)

The flat-band voltage is defined as the applied gate voltage such that there is no band bending in the semiconductor. It was given by

VFB =

Where Qss is the equivalent fixed oxide charge and φ_ms is the metal-semiconductor work function difference. The flat-band voltage shift to more negative voltages for a positive fixed oxide change.Since the oxide charge is not a function of gate voltage, the curves show a parallel shift with oxide charge, and the shipe of the C-V curves remains the same as the ideal characteristics.

The C-V characteristics can be used to determine the equivalent fixed oxide charge. Using the equation given in Ref. 7, for a given MOS structure, Cox are given ,

∆VFB can be determined.

19

Where ε is the permittivities [7]. In the case of multilevel charge storage,

(2.21)

Where tn is the upper control gate oxide thickness, tdot is the nanocrystal diameter, and εox and εsi are the permittivities of the oxide and silicon, respectively[7].

2.8 Reference

1. Donald A. Neamen, Semiconductor Physics & Devices, third Edition.

2. S.M. Sze, Physics of semiconductor devices. New York: John Wiley & Sons 1981.

3. David Wood, “Optoelectronic Semiconductor Devices”, (Prentice Hall, New York, 1994).

4. M. Razeghi and A. Rogalski, J. Appl. Phys. 79, 7433 (1996).

5. Bahaa E. A. Saleh and Malvin Carl Teich, ”Fundamentals of Photonics”, ( Wiley - Interscience Publication, New Yok, 1991).

6. C. K. Wang, T. K. Ko, C. S. Chang, S. J. Chang, Y. K. Su, T. C. Wen, C. H. Kuo, and Y. Z. Chiou, IEEE Photon. Technol. Lett. 17, 2161 (2005).

7. T. Z. Lu,a M. Alexe, R. Scholz, V. Talelaev, and M. Zacharias, APL .87, 202110 (2005)

20

Chapter 3 Experimental Details

3.1 Process

3.1.1 Preparation of mesoporous silica template

The mesoporous silica (MS) films [1] are initially spin-coated on silicon wafers using sol-gel-prepared precursors that contain different organic templates (cetyltrimethylammonium bromide (CTAB), polyoxyethylene cetyl ether (Brij-56), and Triblock copolymer Pluronic P-123 (P123)) for controlling the pore-size , followed by drying at 40°C and baking at 110°C for five and three hours respectively . The MS film was formed by molecular self-assembly aggregation in this step. The film was employed as nanotemplate for the growth of three-dimensional array of Si (Ge) nanocrystals (nc).

The flowchart of mesoporous silica nanotemplate films preparing is shown in Fig. 3.1.

The sol-gel was made by mixing H

2O, HCl , tetraethylorthosilicate (TEOS), and ethanol at 70℃ for 90 min. The molar ratios of reactants were 1:0.008-0.03:3.5-5:0.003-0.03:10-34(TEOS/(P123,CTAB,Brij-56)/H

2O/HCl/ethanol).

After aged at room temperature fore more than 3hours, it was spin-coated onto silicon substrates at 2200 rpm for 30 seconds.

21

Fig. 3.1 Flowchart of sol-gel procedure for preparing mesoporous silica nanotemplate films.

Aging for 3-6 hours, RT

Spin coating on Si Wafer

Drying at 40

^o

C and baking at 110

^o

C (Self-assembly aggregation ⁾

Addition of triblock copolymer template

MS template preparing flowchart Precursor sol : P123/H2o/HCl

70℃, 90 min

Aging for 3-6 hours, RT

Spin coating on Si Wafer

Drying at 40

^o

C and baking at 110

^o

C (Self-assembly aggregation ⁾

Addition of triblock copolymer template

MS template preparing flowchart Precursor sol : P123/H2o/HCl

70℃, 90 min

22

3.1.2 The growth of 3-D Si (and Ge ) nanocrystals by HDP-CVD

Inductivity coupled plasma-chemical vapor deposition (ICPCVD) [2,3] of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. High-Density Plasma Chemical Vapor Deposition (HDPCVD) with the features of low process temperature, low pressure and high plasma density was chosen to growth Nc-Si (or nc-Ge) in the MS tempelate.

Base pressure of chamber was as low as 10

-6

Torr. Mixture plasma at 500W was powered on after loading MS-coated wafers into the chamber. During the entire process, pressure was kept below 10m torr and the substrate temperature was hold at 400℃. MS films embedded with high density silicon (or germanium) nanocrystals were prepared by using 12 – 18 cycles of pulsed SiH

4+H

There are numerous reactions involved in the formation of nc-Si (or nc-Ge) in the MS template with ICPCVD . Firstly, the pure-H

2-ICP-plasma (step A of Fig. 3.2) removes organic-templates of MS matrices lightly for enabling limited nucleation sites of Si-OH on pure-surfaces [4]. This is a self-limiting reaction (SLR), which is a core concept in atomic layer deposition [5]. Sequentially, ICP-dissolved SiH

x (GeH

x) species (step B of Fig. 3.2) in the form of nanoclusters diffuse into the nanopores, and are then absorbed and embedded in the residual organic-template of MS. They eventually react with the nucleation sites through hydrogen-elimination reaction (HER). Therefore, both

23

self-limiting reaction [5] and hydrogen-elimination reaction (HER) [4,5] govern the conversion of ICP-dissolved species in MS into nc-Si (or nc-Ge). The density of nc-Si (or nc-Ge) grown by pulsed plasma can as high as 2.5x10

18

/cm

3

.

Fig. 3.2 Schematic mechanism of 3D Si nanodots formed by pulse ICP process.

SiO2

Si

24

3.1.3 Device fabrication

The device structure is depicted schematically in Fig. 1.First, a 220-nm-thick MS template layer is formed on Si substrates. Si nanocrystals were thereafter synthesized in the MS templates by using a plasma deposition process.12 For device applications, the organic contents of MS are removed by calcinations in the same chamber with H

2 plasma at the flow rate of 150 sccm for 2 hours. The indium–tin–oxide (ITO) films of 2400A

o

thick were deposited onto the samples by E-gun evaporation, followed by 20 min of annealing at 400℃ in N

2 ambient.

Fig. 3.3 A schematic drawing illustrating the configuration of the photodiodes of ITO/nc-Si embedded MS /p-Si.

• Calcined (Remove organic contents) H₂plasma, flow rate: 200 sccm, 2hours,450℃

• E-gun evaporation : ITO film 240nm

P type Si substrate ITO

nc-Si embedded in MS 220nm

p- Si substrate

25

3.2 Experiment Setup

3.2.1 The Capacitance-Voltage measurement system

The system we used to measure the low ferquence capacitance is Bias Temperature Stress measurement system (BTS): Keithley 590 CV analyzer 、Keithley 595 Quasistatic CV meter、Keithley 230 programmable voltage source、Keithley 5951 remote input coupler and computer with AIT software installed. Fig 3.4 shows the schematic diagram of C-V measurement system.

Fig. 3.4 The schematic diagram of C-V measurement system.

Shielding Box

Probe Station

Probe Probe

Microscop

Keithley 230 programmabl

e voltage

Keithley 595 Quasistatic

CV meter

Keithley 5951 remote input coupler Keithley 590 CV analyzer

26

3.2.2 Spectral responsivity measurement system

The setup of spectral responsivity measurement system as showed in Fig. 3.5.

Spectral responsivity measurements were achieved using a 300 W xenon lamp with wavelength selection using a double-grating monochoramator ( Jobin-Yvon Gemini 180).

Lamp focuses on the sample through 2 focal lens which focal length is five centimeter.

The spot size is about 3x4 mm² after focusing and the power is 0.1~0.7 mW on the surface of the sample. The measurements of current-voltage characteristics were controlled by the Labview programs. A Keithley 2400 source measurement unit was used to apply biases to the electrodes., Bias-dependent responsivity was measured in dc mode by recording current–voltage (I –V) curves under a fixed wavelength and power. The power density of the excitation was determined with a calibrated UV Si photodetector.

Fig. 3.5 Diagram of spectral responsivity measurement system.

Keithley 2400 Computer

Monochoramat Xe

lamp

XYZ Stage

27

3.3 References

1. D. Zhao, P. Ya ng, N. Melosh, J. Feng, B. F. Chmelka, and G. D. Stucky, Adv. Mater.

10, 1380 (1998).

2. J. M. Shieh, K. C. Tsai, and B. T. Dai, Appl. Phys. Lett. 81, 1294 (2002).

3. J. H. Wu, J. M. Shieh, B. T. Dai, and Y. S. Wu, Electrochemical and Solid-State Letters 7 (6), G128 (2004).

4.

ö

. Dag, G. A. Ozin, H. Yang, C. Reber, and G. Bussie`re, Adv. Mater. 11, 474 (1999).

5. Y. J. Lee, and S. W. Kang, Electrochemical and Solid-State Letters, 6 (5), C70 (2003).

28

Chapter 4 Results and Discussions

4.1 TEM Image

The experiment was started with the formation of a 220-nm-thick MS template layer on p-type silicon substrates. Si or Ge nanocrystals were thereafter synthesized in the MS templates by using a plasma technique [1]. Fig. 4.1 is the cross-sectional transmission electron microscopy (TEM) image for the sample. One can see that the MS film was decorated with ~10¹⁸ cm^-3 of Si nanocrystals, and the mean size of nc-Si was found to be 4 nm.

Fig. 4.1 The cross-sectional TEM images of the mesoporous silica (MS) films with high density silicon nanocrystals.

20nm

29

4.2 C-V Measurement

For C-V measurement, a compound oxide with structure of SiO2/MS with Si (Ge) QD imbedded/SiO2 was formed on p-type Si wafer. The tapping oxide and tunneling oxide with thickness of 10nm and 5nm were deposited by HDPCVD, with gas flow of SiH4:N2O=1:15 sccm and process temperature of 375⁰C. After that, the top and back contact layers of Aluminum were plated by thermal coater. Fig 4.2 (a) illustrates the device structure, and (b) is the image of device.

Fig. 4.2 (a) A schematic drawing illustrate the configuration of the device with compound oxide. (b) The image shows device with Al contact layer.

SiO

2

20nm

SiO

2

3nm

Si (Ge) QD imbedded MS 220nm

Al

P-type Si (sub) Al

Al

30

To investigate the trapping characteristics of the structure we performed multiple up-down capacitance voltage (C-V) sweeps between inversion and accumulation regions. The measurements were performed at 1MHz using BTS C-V measurement system at room temperature. Fig 4.3(a) and (b) illustrate the characteristic multilevel charge storage for our metal-oxide-semiconductor (MOS) structures. The C-V hysteresis was observed, which is caused by the successive charge trapping and de-trapping processes in the Si (Ge) NCs. With sweeping range of 20V, the hysteresis widths of Si and Ge doped sample can be as large as 16 and 12 V, respectively.

Fig. 4.3 High frequency C-V characteristics of the sample (a) with Si QD and (b) Ge QD imbedded in MS.

As can be seen in Fig 4.4, a different programming bias applied at the gate results in a various C-V hysteresis widths. Hence, the narrowest C-V loop corresponds to the charging of only one layer and the widest one to the charging of more layers of QDs imbedded in MS. The sweep is from the inversion to the accumulation region for the MOS devices based on p-type substrates. For negative program bias, more and more holes are trapped in the QDs which are evident by the counterclockwise

-15 -10 -5 0 5 10 15 20

31

hysteresis. After each sweep, holes charged in the QDs were always erased by positive bias to bring the device back to the neutral stage.

hysteresis. After each sweep, holes charged in the QDs were always erased by positive bias to bring the device back to the neutral stage.

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