4.1 Introduction
The double-gate (DG) transistor, where the both gates are employed to control the channel, exhibits attractive advantages in comparison to the conventional MOS transistor. The double gate transistor has the properties of almost ideal subthreshold swing and high transconductance. The increase of DG transistor’s current is due to the formation of a double conducting channel close to the two Si and SiOB2B interfaces. The additional advantage in terms of transconductance and current drive are attributed to the inversion layer of the silicon region away from the two interfaces, which suffer less surface roughness scattering. The double-gate transistor with even thinner semiconductor layer can work in the volume inversion regime [4.1-4.3],which means that the whole volume of the semiconductor region is in the strong inversion.
If the semiconductor layer is ultra thin, the energy quantization effect becomes evident which affects considerably the carrier distribution in the semiconductor and influences the transistor parameters. In this chapter, we firstly investigate the effect of the semiconductor thickness on the hole density distribution, threshold voltage and finally compare the double-gate and single-gate transistor in terms of hole density distribution and the effective electric field, which are related to the low field mobility.
4.2 Device Configuration and Simulation Technique
(SG) MOS devices. The silicon thickness down to 5nm and the thickness of the back-oxide of the SG MOS device 50nm are considered. For the silicon layer, n-type doping with NBDB=10P17P cmP-3P is assumed for both cases. The two gate electrodes of the DG device and the front gate of the SG are assumed of pP+P-polysilicon, while in the SG device a grounded nP+P-polysilicon gate mimics the effect of the silicon substrate, as shown in Fig 4.1.
The simulation is carried out by self-consistently solving the Poisson and Schrödinger equations. The quasi-Fermi levels for electrons and holes are set within the whole simulation domain, to reflect a bias condition with grounded source and drain. The poly depletion and wave function penetration into the gate oxide are neglected in our simulations. The procedures of solving the Poisson and Schrödinger equations are referred to chapter 3.
4.3 Results and Discussions
4.3.1 Symmetric Double Gate MOS
Fig. 4.2 shows the hole concentration distribution in a DG MOS device with 10nm silicon thickness and 6nm oxide, which is biased above threshold. A maximum at the center of the silicon layer is obtained at lower gate voltage, while at higher gate voltage two inversion maxima are formed. The effect of volume inversion vanishes rapidly as silicon thickness is increased, resulting in a reduction of the minority carrier concentration in the middle of the silicon layer.
Fig. 4.3 shows the influence of the silicon thickness on the hole concentration distribution at the same VBgB-VBfbB. As shown in Fig. 4.3, if the silicon thickness is thinner than 10nm, two regions overlap strongly that the hole concentration maximum
from the classical picture. In Fig. 4.4, the dependence of the total inversion hole density on the different silicon thickness in the symmetrical DG device is shown. For the small VBgB-VBfbB, i.e. small surface potential, when the potential is nearly rectangular, the quantization is effective only for silicon thickness thinner than 20nm, as a result of the hole wave functions confinement by the two silicon and oxide interfaces. On the other hand, for the larger VBgB-VBfbB, all holes are confined in the surface subwells. As a consequence, the inversion hole density does not depend on the silicon thickness.
Fig. 4.5 shows the dependence of the threshold voltage on the silicon thickness TBsiB. The threshold voltage is determined by the linear extrapolation of the gate voltage dependence of the inversion hole density [4.4]. It is worth noticing that the turn-around characteristic of the threshold voltage is demonstrated, which implies that for silicon layer thickness below 20nm, the effects of surface inversion layer overlap and the hole energy quantization become obvious. On the other hand, an appropriate work function of the double gate should be chosen to adjust the positive threshold voltage of pFET demonstrated here.
4.3.2 Comparison of Double Gate and Single Gate MOS devices
In this section, we will focus on the advantages of DG devices in comparison to SG devices in terms of the low-field mobility, which is determined by the transverse electric field in the silicon layer and the displacement of the peak hole concentration from the oxide interface.
In Fig. 4.6, the inversion hole density as a function of the gate voltage in a DG and SG MOS device with 20nm silicon thickness and 3nm oxide is shown. The inset is the linear scale of the inversion hole density versus the gate voltage to extrapolate the threshold voltage. Both two devices show ideal subthreshold swing, which is
in SG device due to the formation of the two conducting channels. In Fig 4.7 (a), the hole concentration distribution of a DG device is compared to that of a SG device biased with the same gate drive, which means the difference of the threshold voltage of the two devices is considered. The calculated inversion hole density is 7.32*10P12P cmP-2P for a DG device and 3.65*10P12P cmP-2P for a SG device, respectively. The inversion hole density of a DG device is twice of a SG device. As shown in the Fig. 4.7 (b), the DG inversion hole density distribution is more displaced from the interface than the SG one, which is about 0.45nm. This difference is crucial in determination of the low-field mobility. Finally, Fig. 4.8 compares the transverse electric field within one half of the silicon layer of a DG and a SG device biased at the same gate drive. The transverse electric field is lower in the DG device and vanishes at the middle of the silicon layer due to the symmetry of the structure. Moreover, the surface roughness scattering rate is given by [4.5],
* 2 2 2 2 2 2 2
where △ is the average displacement of the interface and EBeffB is the effective electric field. In a consequence, the effective electric field is lower in the DG device, which possibly results in the improved mobility as a result of a reduction of the surface roughness scattering.
oxide