Semiconductor Fabrication

Semiconductor device fabrication is the process used to create the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuit are gradually created on a wafer made of pure semiconducting material. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors.

The entire manufacturing process from start to packaged chips ready for shipment takes six to eight weeks and is performed in highly specialized facilities called ―fabs‖.

Table 3.2 Process flows and description for semiconductor fabrication

Classification Description

1

Front-end processing Front-end processing refers to the formation of the transistors directly on the silicon. The raw wafer is engineering by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effect.

Front-end surface engineering is following by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In memory devices, storage cells, conventionally capacitors, are also fabricated at this time, either into the silicon surface or stacked above the transistor.

2 Back end processing Once the various semiconductor devices have been created they must be interconnected to form the desired electrical circuits. This back end of line (BEOL, the latter portion of the wafer fabrication, not to be confused

with back end of chip fabrication which refers to the package and test stages)

Involves creating metal interconnecting wires that are isolated by insulating dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.

3 Modules Historically, the metal wires consisted of aluminum. In this approach to wiring often called subtractive aluminum, blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires.

Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called vias, in the insulating material and depositing tungsten in them with a CVD technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminium to copper and from the silicon dioxides to newer low-K material. This performance enhancement also comes at a reduced cost via damascene processing that eliminates processing steps.

In damascene processing, in contrast to subtractive aluminium technology, the dielectric material is deposited first as a blanket film, and is patterned and etched leaving holes or trenches. In single damascene

processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire lines respectively. In dual damascene technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called copper barrier seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is as thin as possible. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest continuous barrier represents one of the greatest ongoing challenges in copper processing today.

As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked and extend outside the depth of focus of available lithography, interfering with the ability to pattern. CMP (chemical mechanical planarization) is the primary processing method to achieve such planarization although dry etch back is still sometimes employed if the number of interconnect levels is no more than three.

4 Wafer test The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing.

If the number of dies—the integrated circuits that will eventually become chips— etched on a wafer exceeds a failure threshold (ie. too many failed dies on one wafer), the wafer is scrapped rather than investing in further processing.

5 Device test Once the front-end process has been completed, the

semiconductor devices are subjected to a variety of electrical tests to determine if they function properly.

The proportion of devices on the wafer found to perform properly is referred to as the yield.

The fab test the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. The fab charges for test time; the prices are on the order of cents per second. Chips are often designed with

―testability features‖ such as "built-in self test" to speed testing, and reduce test costs.

Good designs try to test and statistically manage corners: extremes of silicon behavior caused by operating temperature combined with the extremes of fab processing steps. Most designs cope with more than 64 corners.

6 Packaging Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny wires are used to connect pads to the pins. In the old days, wires were attached by hand, but now purpose-built machines perform the task.

Traditionally, the wires to the chips were gold, leading to a ―lead frame‖ (pronounced ―leed frame‖) of copper, that had been plated with solder, a mixture of tin and lead. Lead is poisonous, so lead-free ―lead frames‖ are now mandated by ROHS.

Chip-scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die. CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were

not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser etches the chip‘s name and numbers on the package.

Table 3.3 Semiconductor industry from upstream to downstream

Upstream

Fig. 3.2 Semiconductor upstream and downstream diagram

3.6.1 Electronic Device Technology

Electronics is that branch of science and technology that uses the controlled motion of electrons through different media and vacuums The ability to control electron flow is usually applied to information handing or device control. Electronics is distinct from electrical science and technology, which deals with the generation, distribution, control and application of electrical power. This distinction stated around 1906 with the Lee De Forest‘s invention of the triode, which made electrical amplification possible with a non-mechanical device. Until 1950, this field was called

―radio technology‖ because its principal application was the theory and design of radio transmitters, receivers and vacuum tubes. Most electronic devices today uses semiconductor components to control electron flow. The study of semiconductor devices and related technology is considered a branch of physics, whereas the design and construction of electronic circuits to solve practical come under electronics engineering.

3.6.3 The Revolution in Electronic Devices

The emergence of the IC semiconductor stems from the electronic devices revolution, people started to use semiconductors in marking complex chips. Table 3.3 lists the events in the resolution of electronic devices.

Table 3.3 The events of electronic devices revolution 1874 Braun invents the solid-state rectifier 1906 DeForest invents triode vacuum tube 1907~

1927

First radio circuit developed from diodes and triodes 1925 Lilienfeld field-effect device patent filed

1947 Bardeen and Brattain at Bell laboratories invent bipolar transistors 1952 Commercial bipolar transistor production at Texas Instruments 1956 Bardeen, Brattain and Shockley receive Nobel Price

1958 Integrated circuit developed by Kilby and Noyce 1961 First commercial IC from Fairchild Semiconductor 1963 IEEE formed from merger or IRE and AIEE 1968 First commercial IC opamp

1970 One transistor DRAM cell invented by Dennard at IBM 1971 4004 Intel microprocessor introduced

1974 First commercial 1-kilobit memory 1978 8080 microprocessor introduced 1984 Megabit memory chip introduced

2000 Alferov, Kilby, and Kromer share Nobel price