In the IC fabrication systems, numerous lots queue up for the machine. Lot scheduling attempts to determine what type of lot will be operated ® rst. Many heuristic rules exist have been proposed in previous studies (Li et al. 1996, Nahahaari and Khan 1997, Kim et al. 1998a, Kim et al. 1998b, Glassey and Weng 1991), which can be described as listed below:
FIFO : First-in-® rst-out, where lots are scheduled in the order they arrive.
L TF: Longest time ® rst. where lots with the longest processing times are priori-tized. This policy represents a worst-case scenario.
STF: Shortest time ® rst, where lots with the shortest processing times are prior-itized.
L RF: Least remaining step ® rst, where lots with least remaining step ® rst are prioritized.
SSF: Shortest setup time ® rst, where lots with shortest setup time are prioritized.
4.1.1. L ot release
Furthermore, many heuristic rules of lot release exist, which can be described as listed below:
Idle avoidance: Start a new lot to avoid bottlenecks and idle workstation due to a lack of work. Thus, a new lot is released when the virtual inventory at the bottle-neck workstation falls below a predetermined value.
CONW IP: Constant work-in-process (WIP), which means starting a new lot when-ever a lot is completed. With this rule, the WIP level controls the throughput.
POISS : Lots enter the facility according to a Poisson process.
DET ERMIN: Inter-arrival times of lots are constant. This policy is also called UNIF(uniform).
W R(C): Workload regulating input is used. When the expected amount of work in the plant for the bottleneck station drops to C hours, then a new lot is released into the plant.
PW R(C): Parametric workload regulating input is used. This policy resembles WR, but only a portion of lots in the plant are considered when calculating the workload of the bottleneck workstation in PWR.
4.2. AGV -calling dispatching
The control policies of AGV can be classi® ed into four types, namely, AGV-Calling dispatching, AGV-Visiting planning, AGV routing, and making an Idle-AGV depart. As mentioned in the Process Elementary Module, if the current
loca-tion where the wafer resides is di ers from that of the workstaloca-tion of the next operation, a signal must be sent to AGV. This signal invokes an AGV to come to the place where the location of the wafer. An AGV serves a lot transporting, called a transporting task. A heuristic rule workload regulating(WR) is used, Namely, when the expected amount of workload for the AGV drops to k transporting jobs, then dispatch a transporting job to the AGV.
4.3. AGV -visiting planning
Each multiple-load AGV may have to visit several stops for loading or storing the wafers that it is carrying. A good visiting plan is necessary to solve vehicle tra c jam problems by deciding the visiting sequence of an AGV. A heuristic rule shortest distance ® rst (SDF) is used. The stops closest to the current location are visited ® rst.
To achieve this, for the example of the intrabay 1, the system layout must ® rst be transformed to a layout directed graph which is shown in Figure 15. Each arc has the same distance.
4.4. AGV routing
Each time an AGV wants to move from the current stop to another stop, it must
® rst determine its route. The routing policy can be made and the AGV can move along that route. The heuristic rule shortest path ® rst (SPF) is used. Every two nodes in Figure 15 have a planned static shortest path. However, at some point, a limit will be reached due to AGV tra c congestion. A simple heuristic rule congestion solving is used. A ¯ ow control redirects an AGV through a non-congested area or slows an AGV that wants to enter a congested area.
4.5. Selection of idle AGV
When a missioned AGV wants to enter a stop, it informs AGVs that occupy the stop. An idle AGV is selected to leave that stop. A heuristic rule shortest idle time
® rst (SIF) is used, in which the AGVs with the shortest IDLE time depart ® rst. The reason is as follows. when AGVs have a balanced load, there is a higher probability that the AGV with a long idle time will be dispatched a transporting job.
5. Performance analysis and scheduling adjustment by simulation 5.1. Plant layout and process ¯ ow: a case study
To illustrate the promise of the work, a real-word IC wafer fabrication system is made the target plant layout for implementation. Producing ICs is very complex and involves hundreds or thousands of machines and processing steps. For easy illustra-tion and con® dentiality, this study only presents a porillustra-tion of these manufacturing machines. However, the process ¯ ow modelled here is based on an actual process
Figure 15. Layout directed graph.
under development in a Taiwanese wafer fabrication system. Thus, it stills gives an overall picture of IC fabrication.
As shown in Figure 16, there are 24 workstations arranged in locations 1-24. The corresponding AGV stops are also arranged in locations 1± 24. Multiple automated guided vehicles (AGV) are used for wafer transportation. In the interbay system, the corresponding AGV stops are arranged in locations 25± 35. Meanwhile, this system has only a single-loop track. Tracks in di erent areas do not overlap and are denoted as Intrabay 0± 7.
As Figure 17 reveals, for the resist strip process, reentry occurs 23 times for each lot. Twenty-four workstations are divided into six types, and each of the multi-server workstations comprises several identical pieces of equipment. Figure 17 classi® es the resources according to function. In the simulation model, the machine downtime, consisting of unscheduled breakdowns as well as scheduled maintenance is included.
Time between failures and repair time for each workstation is randomly generated from uniform distributions with given mean values. In the Fab model, the mean processing time (MPT) contains the mean processing time and mean setup time. The simulation model presented here, separates these values. The MPT in the current model equals 0.9XMPT in the Fab model, and the mean setup time (MST) equals 0.1XMPT in the Fab model. In the simulation model presented here, each lot enter-ing the fab is based on a speci® c process ¯ ow. The model contains two di erent process ¯ ows, and the sequence of stations to be visited in three process ¯ ows are listed in Figure 18 and Figure 19, respectively. The Re-entry operations on the same machine is assumed to possibly have di erent processing time, since di erent recipes must be processed. Additionally, if the machine deals with processes with di erent recipes, the machine must be set-up. Here, the processing time (PT) for a lot is randomly generated from a uniform distribution between 0.9XMPT and 1.1XMPT, where MPT for each workstation is provided in Figure 17. The setup
Figure 16. Plant layout.
time (ST) is treated similarly, also being randomly generated from a uniform distri-bution between 0.9XMST and 1.1XMST.
5.2. Simulation result
Since the system model is large, simulation is used to obtain performance meas-ures. In this simulation experiment, due to the nature of IC wafer processing, opera-tion time varies little between lots. For ease of illustraopera-tion, this work only focuses on one intrabay in the material handling system. Meanwhile, the other interbay and intrabays are treated with the same simulations. Considering the warm-up period of the system, each simulation run is implemented for an extended period. A simulation experiment is conducted as follows.
5.2.1. L ot scheduling
First, let the release rule be DETERMIN and the arrival interval of input lot be 36 hours. Thus, one lot is released into the wafer factory every 36 hours. Three scheduling rules must be implemented, namely FIFO, LRF, and SSF. Moreover, this simulation contains 10 runs. The ® rst run is for 20,000 hours and the last one runs for 38,000 hours. The Figures 20± 22 shows the simulation results, where SSF performs better than the alternatives. Obviously, the cycle time of the lot is much
Figure 17. Equipment description.
Figure 18. Process ¯ ow for route 1.
longer with FIFO. Moreover, FIFO increases rate of cycle time and WIP(work-in-process).
5.2.2. L ot release
The scheduling rule is ® xed as LRF. The arrival interval of input lot is 36 hours for the constant input of DETERMIN and the mean of POISS. The WIP level is maintained at 600 for CONWIP. This simulation contains 10 runs. The duration of the ® rst run is 20,000 hours while the ® nal run is 38,000 hours. Figure 23 shows that
Figure 19. Process ¯ ow for route 2.
the cycle time will increase with the time duration of the run. Figure 25 indicates that POISS have more completed lots than DETERMIN and CONWIP during the initial runs with a shorter period. When the run is lengthy, CONWIP and DETERMIN perform better than POISS. Meanwhile, the number of completed lots initially increases quickly and reaches the upper bounds. From Figure 26, CONWIP will maintain a certain WIP level while the others will increase according to the duration of the run. From Figure 23, Figure 25 and Figure 26, CONWIP appears better than
Figure 20. The relationship between lot scheduling rule and cycle time.
Figure 21. The relationship between lot scheduling rule and cycle time: 20,000 hours.
DETERMIN. This result indicates that the number of bottleneck machines will increase, when a large number of lots is released into the Fab.
5.2.3. Arrival interval
Given that the scheduling rule is FIFO while the release rule is DETERMIN, the arrival interval of the lot was varied from six hours to seventy-two hours. Moreover, this simulation also contains 10 runs. The duration of the ® rst run is 20,000 hours while the ® nal run is 38,000 hours. Figure 27± 28 reveals the simulation results. In
Figure 22. The relationship between lot scheduling rule and work-in-process.
Figure 23. The relationship between lot release rule and cycle time.
Figure 27, the throughput is worst when the arrival interval is six hours. This ® nding implies that wafer ¯ ow is congested when many lots are in the factory. Notably, seventy-two hours is not the ideal in Figure 27. This observation indicates that the ideal arrival interval is between 54 hours and 72 hours. Meanwhile, the analysis reveals that the optimal arrival interval is 2.6 days. Figure 28 shows that the WIP increases according to the rate of lot arrival.
Figure 24. The relationship between lot release rule and cycle time: 20,000 hours.
Figure 25. The relationship between lot release rule and number of completed lot.
5.2.4. AGV routing and AGV visiting
The intrabay 1 is implemented, where the physical layout is a layout directed graph, which is shown in Figure 15. Intrabay 1 contains three multiple-load AGVs.
There are three rule combinations. (WR, SDF, SPF) denoting that the AGV dis-patching rule is WR, visiting rule is SDF, and routing rule is SPF. Meanwhile, (WR, FCFS, SPF) presents that the dispatching rule is WR, visiting rule is FCFS(® st come
® rst serve), and routing rule is SPF. Finally, (WR, FCFS, RANDOM) presents that the dispatching rule is WR, visiting rule is FCFS, and routing rule is RANDOM.
There are ® ve runs in this simulation. The AGV speed of the ® rst run is 1/0.25 m/
Figure 26. The relationship between lot release rule and work-in-process.
Figure 27. The relationship between lot arrival interval and throughput.
min. and it is 1/1.75 m/min. for the ® nal run. Figure 29± 30 indicates that the gap among the three di erent combinations increases according to 1/(speed of AGV).
This phenomenon indicates that raising the speed of AGV increases performance.
Meanwhile, regression analysis indicates that the optimum speed of AGV is 4 (m/
min.) in this simulation. Figure 29± 30 also shows that the routing rule in¯ uences performance than the visiting rule in this simulation experiment. However, there is a stage where the additional speed does not o er a signi® cant increase in performance.
Figure 28. The relationship between lot arrival interval and work-in-process.
Figure 29. The relationship between speed of AGV and routing rule.
This number depends on physical layout. In the model presented here, the optimal number from analysis is approximately 5.
5.2.5. AGV dispatching
Two combinations must be implemented, (WR, SDF, SPF) and (RANDOM, SDF, SPF). Where (WR, SDF, SPF) denotes that the AGV dispatching rule is WR, visiting rule is SDF, and routing rule is SPF. (RANDOM, SDF, SPF) presents that the dispatching rule is RANDOM, visiting rule is SDF, and routing rule is SPF. The
Figure 30. The relationship between speed of AGV and routing rule.
Figure 31. The relationship between visiting rule and task arrival interval.
loading and storing tasks are fed into the interbay 1. The task arrival is DETERMIN. Moreover, this simulation contains eight runs. The task arrival inter-val of the ® rst run is 3 minutes and that of the last is 10 minutes. Figures 31± 32 displays the results. The cycle time increases with task arrival rate. If the number of AGVs is large, we can predict that RANDOM and WR perform very di erently.
Figure 31 also shows that WR have stable performance than RANDOM.
6. Conclusions
The GSCTPN can model the complex process ¯ ows in wafer fabrication e -ciently and the detailed manufacturing characteristics such as lot processing, machine setup, machine failure, batch processing, and reworking of defective wafers. Some control policies based on the GSCTPN model optimize certain a priori assigned aspects of performance. The plant layout and processing steps resem-ble those in Zhou and Jeng 1998 and Jeng et al 1998. Unlike the model proposed in Zhou and Jeng 1998 and Jeng et al. 1998, this work introduces a GSCTPN modelling of a general IC wafer fabrication system. The resulting net model overcomes the
`long’ net modelling of the reentrant processing problem. It contains fewer places and transitions. Furthermore, the proposed GSCTPN model considers multiple types of wafers. The proposed GSCTPN model extends the modular modelling approach and formally de® nes the class of systems that can be dealt with using the approach. Notably, the GSCTPN model already has embedded a control rule embedded into it to prevent vehicle collision problems from occurring. The trans-porting system aims to introduce a control method into the Petri-Net model to guarantee a jam-free condition among carriers.
The other contribution of this research is in proposing a simulation based per-formance analysis and schedule adjustment. A schedule can be ® ne tuned, based on simulation to meet rapidly changing of system parameters without long-run resche-duling. Performance measures are obtained by simulation. The validated model can
Figure 32. The relationship between visiting rule and task arrival interval.
answer many `what-if ’ questions, for example predicting the throughput. Various possible improvements exist. They will be examined in future studies and are described below.
Factor Combination: So far, the factors that are included in this simulation include lot scheduling rule, lot release rule, and lot arrival interval. However, this study does not address many factors that in¯ uence performance, including the fre-quency of machine breakdown and the number of bottleneck machines. Future studies will attempt to ® nd out and combine these in¯ uences.
Numerical Analysis: Since lengthy simulations are often necessary to obtain results with su cient accuracy. Numerical analysis techniques and simulation both have advantages and limitations. Thus, methods of combining analytical/numerical techniques and simulation will be examined in the future.
Acknowledgements
The authors would like to thank Worldwide Semiconductor Manufacturing Corporation (WSMC) for their valuable assistance and cooperation. In addition, the authors would like to thank the National Science Council of the Republic of China for ® nancially supporting this research under Contract No. NSC 87-2212-E-002± 068.
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