Effect of Strain on Double Gate Device
5.2 Simulation of the Strained DG Device
Now, we propose another kind of double gate strained Si device. The device structure is shown in Fig.5.3. Fig.5.3(a) depicts that Si(100) is pseudomorpically grown on Si1-xGex. A narrow line with (100) sidewall surface is formed after etching the strained Si. Then, after growing the thermally oxide on the sidewall, metal gate is formed. Finally, this device is fin-FET like device. The top view of this device is schematically shown in Fig.3.3(b). Fig.5.4 schematically displays the constant energy surface of conduction band as viewed from the top of this device, where valley A denotes the twofold degenerate valleys with the energy lowering of 0.67x by the bottom strained Si, and valley B and C denote the twofold degenerate valleys perpendicular and parallel to the interface between the oxide and Si, respectively. For valley A,mDi =2 mtml , mc,i =4ml, for valley B,mDi =2mt,mc,i =4mt, and for
valley C, mDi =2 mtml mc,i =4mt.
Unlike the traditional DG device, the fourfold degenerate valleys are further spit into two twofold degenerate valleys. Because of the energy lowering, valley A is preferential on the electron occupancy. As a result, the intervalley scattering between any two valleys is suppressed and thereby only the intravalley scattering of the valley A needs to be concerned. Theoretically, this device should have better device performance. Unlike the subband engineering of the traditional DG device by the space confinement, this new DG device use both strain and space confinement to change the subband. Thus, this device can undergo subband engineering even for thick Si layer.
5.3 Results of Simulation
With this idea in mind, our QM simulator is suitable to simulate this device by
modifying Purdue’s program. Fig. 5.5 and Fig. 5.6 show simulated IBALLISTIC-VG curves for tSi=2nm and tSi=50nm, respectively. For the thicker tSi, the inclusionof Ge in substrate can improve the ballistic current. However, the inclusion of Ge degrades the performance for the thinner tSi. To exploit it more, the effects of Ge content on the ballistic current and vinj for various tSi under fixed QINV are shown in Fig. 5.7 and Fig. 5.8, respectively. Obviously, there is a lower limit of tSi to improve device performance by the inclusion of Ge in substrate. Fig. 5.9 and Fig.5.10 reveal the variation of electron occupancy of valley A and valley B for various tSi under different Ge contents.
5.4 Discussion
We explain the above results as follows. At thicker tSi, the main mechanism of subband engineering is energy splitting of conduction band induced by strain. This energy splitting makes the valley A preferential on electron occupancy so that the inclusion of Ge improves the device performance. However, as tSi shrinks further, another mechanism of subband engineering, space confinement, which makes valley B preferential on electron occupancy and competitive with the previous mechanism.
As a result, the inclusion of Ge degrades the device performance at thin tSi.
Unlike the traditional DG device, which favors thin tSi, this strained silicon device enhances the device performance at thick tSi, but degradations occur at thin tSi.
Thus, a critical thickness ofSi exist, which is found to be the thickness the space confinement starts to influence the wave function of the inversion charge. This critical thickness is about a few nanometer (~5nm in this case), and it continues to shrink as the dopping concentration of Si increases. Such thickness is not practical in view of
manufacture. This means that the strained Si provide a more practical way to improve device performance better than traditional DG device.
Chapter 6 Conclusion
Quantum simulation of strained Si device is successful developed. The simulated gate current via direct tunneling mechanism exhibits distinct dependencies on Ge content and gate voltage. Finally, a new strained DG device with better performance than traditional DG device is proposed and examined.
References
[1] C.Ge, et al.,“Process Strained Si CMOS Featuring 3D Strain Engineering,＂IEDM, p.73, 2003.
[2] http://www.nanohub.purdue.edu.
[3] F. Assad, Z.Ren, D.Vasileska, S.Datta, and M.Lundstrom,“On the performance Limits for Si MOSFET’s:A Theoretical Study,＂IEEE Transactions on Electron Device, 47, p.232, 2000.
[4] J.Blakemore,“Approximation of the Fermi-Dirac integrals, especially the function , used to describe electron density in a semiconductor,＂ Solid State Electronics, 25, p1067, 1982.
[5] F.Stern,“Self-Consistent Results for n-Type Si Inversion Layers,＂Physical Review B, 5, 4891, 1972.
[6] S. Takagi, L. Hoyt, J. Welser, and F. Gibbons,“Comparative Study of Phonon Limited Mobility of Two Dimensional Electrons in Strained and Unstrained Si Metal Oxide Semiconductor Field Effect Transitor,＂Journal of Applied Physics, 80, p.1567, 1996.
[7] S. Takagi,“Re-examination of Subband Structure Engineering in Ultra Short Channel MOSFETs under Ballistic Carrier Transport,＂Symposium on VLSI Technology Digest of Technical Paper, p.115, 2003.
[8] S.Galdin, P.Dollfus, Val´erie Aubry-Fortuna, P. Hesto, and H.Osten,“Band Offset Predictions for Strained Group Ⅳ Alloys: Si1-X-YGeXCY on Si(100) and Si1-XGeX
on Si1-ZGeZ(001),＂Semicond. Sci. Technol., 15, p.565, 2000.
[9] J.Goo, Q.Xiang, Y.Takamura, F.Arasnia, E.Paton, P.Besser, J.Pan, and M.Lin,
“Band Offset Induced Threshold Variation in Strained Si nMOSFETs,＂IEEE Electron Device Letters, 24, p.568, 2003.
[ ]
x12
ℑ
[10] M.Reiger and P.Vogl,“Electronic-band Parameters in Strained Si1-XGeX Alloys on Si1-ZGeZ Substrates,＂Physical Review B, 48, p.14 276, 1993
[11] L.Register, E.Rosenbaum, and K.Yang,“Analytical Model for Direct Tunneling Current in Polycrystalline Si Gate Metal Oxide Semiconductor Devices,＂Applied Physics Letters, 74, p.457, 1999.
[12] N.Yang, W.Henson, J.Hauser, and J.Wortman,“Modeling Study of Ultrathin Oxides Using Direct Tunneling Current and Capacitance-Voltage Measurements in MOS Devices,＂IEEE Transactions on Electron Device, 46, p.1464, 1999.
[13] Q.Xiang, J.Goo, J.Pan, B.Yu, S.Ahmed, J.Zhang, and M.Lin,“Strained Si NMOS with Nickel-Silicide Metal Gate,＂Symposium on VLSI Technology Digest of Technical Paper, p.101, 2003.
[14] S.Takagi, J.Koga, A.Toriumi,“Subband Structure Engineering for Performance Enhancement of Si MOSFETs,＂IEDM, p.219, 1997.
0 5 10 15 20
Wave function ( a.u.)
Distance ( nm )
E1 E2 E'1 E'2
Fig.2.1 Wave function distribution Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =1*1016 cm-3 tOX = 1.65*10-9 m; Temp=300K; and VG=1.2 V.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
35 40 45 50 55 60 65
Occupancy ( % )
VG ( V )
Twofold Valley Fourfold Valley
Fig.2.2 Variation of valley’s occupancy verse VG
Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =1*1016 cm-3; tOX = 1.65*10-9 m; and Temp=300K.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
2.0x1012 4.0x1012 6.0x1012 8.0x1012 1.0x1013
Q INV ( cm-2 )
VG ( V ) Si(110) Si(100)
Fig.2.3 Comparison of induced QINV between Si(100) and Si(110).
Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K.
0 50 100 150 -2
-1 0 1 2
VB = 0 VB = -0.2 VB = -0.5 VB = -1
Band Bending ( eV )
Distance ( nm )
Fig.2.4 Band bending as a result of body effect.
Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =8*1017 cm-3; VG=1.2V; tOX = 1.65*10-9 m; and Temp=298K.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
2.0x1012 4.0x1012 6.0x1012 8.0x1012
Q INV ( cm-2 )
VG ( V ) VB = 0
VB = -0.2 VB = -0.5 VB = -1
Fig.2.5 Induced QINV under body effect.
Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =8*1017 cm-3; tOX = 1.65*10-9 m; and Temp=298K.
Fig.3.1 The effect of biaxial tensile strss on Si band structure.
200 220 240 260 280 300
20 30 40 50 60 70 80 90 100
Occupancy of 2-fold valley ( % )
Temperature ( K )
Ge ( 0% ) ( QM Simulator ) Ge ( 5% )
Ge ( 10% ) Ge ( 20% )
Ge ( 0% ) ( Takagi ) Ge ( 5% )
Ge ( 10% ) Ge ( 20% )
Fig.3.2 Comparison between the results from QM Simulator and Takagi [6].
Simulation condition:
Metal gate with Φ=4.05 eV; NSUB =2*1016 cm-3; tOX = 1.65*10-9 m; Temp=300K; and QINV=1*1012 cm-2 .
0 5 10 15 20
0 20 40 60 80 100 120 140
100 200 300
Occupancy of 2-fold valley ( % )
Ge content of SiGe substrate ( % ) QM Simulator
TAKAGI
Energy difference between 2-fold and 4-fold valley ( meV )
Fig.3.3 Comparison between the results from QM Simulator and Takagi [6]
Simulation condition:
Metal gate with Φ=4.05eV; NSUB =2*1016 cm-3 tOX = 1.65*10-9 m; Temp=300K; and QINV=1*1012 cm-2
Occupancy of 2-fold valley ( % )
Ge ( % )
Fig.3.4 Comparison between the results from QM Simulator and Takagi[7]
Simulation condition:
Metal gate with Φ=4.05eV; NSUB =1*1016 cm-3 tOX = 1.65*10-9 m; Temp=300K; and QINV=7*1012cm-2
0 5 10 15 20 25 30 1.125x107
1.250x107 1.375x107 1.500x107 1.625x107
v INJ ( cm / s )
Ge ( % )
QM Simulator current direction <100>
Takagi
current direction <110>
Fig.3.5 Comparison between the results from QM Simulator and Takagi[7]
Simulation condition:
Metal gate with Φ=4.05eV; NSUB =1*1016 cm-3 tOX = 1.65*10-9 m; Temp=300K; and QINV=7*1012 cm-2
Oxide Thickness ( nm )
Si
Fig.4.1 Direct tunneling current from the channel
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Si
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge0.2 Si0.7Ge0.3
J G ( A / cm2 )
VG ( V )
Fig.4.2 JG forverses VG for different Ge concentration (linear scale) Simulation condition:
Metal gate with Φ=4.05eV;NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K
0.0 0.2 0.4 0.6 0.8 1.0 1.2
1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
Si
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge
0.2
Si0.7Ge0.3 J G ( A / cm2 )
VG ( V )
Fig.4.3 JG forverses VG for different Ge concentration (log scale) Simulation condition:
Metal gate with Φ=4.05eV; NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K
0.0 0.2 0.4 0.6 0.8 1.0 1.2
1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
J G ( A / cm2 )
VG ( V )
E1 E'1 ( Si ) E1 E'1 ( Si0.95Ge0.05 ) E1 E'1 ( Si0.9Ge0.1 ) E1 E'1 ( Si0.8Ge0.2 ) E1 E'1 ( Si0.7Ge0.3 )
Fig.4.4 JG,i of each subband verses VG for different Ge concentration Simulation condition:
Metal gate with Φ=4.05eV; NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K
0.0 0.2 0.4 0.6 0.8 1.0 1.2
-60 -50 -40 -30 -20 -10 0 10 20 30
Si
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge0.2 Si0.7Ge0.3
VG ( V ) (J G,nonequilibrium - J G,equilibrium ) / J G,equilibrium ( % )
Fig.4.5 Comparison of JG between equilibrium and non-equilibrium Simulation condition:
Metal gate with Φ=4.05eV; NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K
0.0 0.2 0.4 0.6 0.8 1.0 1.2
100 101 102 103 104 105
(Q INV(Si 1-xGe x) - Q INV(Si))/Q INV(Si) ( % )
VG ( V )
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge0.2 Si0.7Ge
0.3
Fig.4.6 Variation of QINV vs. Ge concentration Simulation condition:
Metal gate with Φ=4.05eV; NSUB =8*1017 cm-3 tOX = 1.65*10-9 m; and Temp=298K
Fig.4.7 Data of JG verse VG from AMD [11]
1 2 3 4 5
Distance ( nm )
E1 E2 E'1 E'2
Fig.5.1 Wave function distribution Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; Temp=300K; and tSi=5nm
0.0 0.2 0.4 0.6 0.8 1.0 1.2
20 30 40 50 60 70 80 90 100
VG ( V ) Single gate
Double gate with 5nm Si layer
Energy ( meV )
Fig.5.2 Energy difference between the lowest subband of the two valley group Simulation condition(Single gate)
Metal gate with Φ=4.05eV; NSUB =1*1016 cm-3 tOX = 1.65*10-9 m; and Temp=300K
Simulation condition(Double gate)
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; Temp=300K; and TSi=5nm
Fig 5.3. (a) Cross section view of strained Si DG device
Fig 5.3. (b) Top view of strained Si DG device
Fig 5.4 valleys of conduction band seen from the top of device
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
I BALLISTIC ( mA / um )
VG ( V ) Si
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge
0.2
Si0.7Ge0.3 Si0.6Ge0.4
Fig.5.5 IBALLISTIC verse VG for various Ge concentrations Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; Temp=300K; and tSi=50nm
Fig.5.6 IBALLISTIC verse VG for various Ge concentration Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9m; Temp=300K; and tSi=2nm
1 10 1.250x107
1.375x107 1.500x107 1.625x107 1.750x107 1.875x107
nsub=1*1016 ( cm-3 ) QINV = 7*1012 ( cm-2 )
tSi ( nm )
Si
Si0.95Ge0.05 Si0.9Ge0.1 Si0.8Ge0.2 Si0.7Ge0.3
v INJ ( cm / s )
Fig.5.8 vINJ as QINV =7*1012 cm-2 verse tSi for various Ge concentration Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; and Temp=300K
0 10 20 30 40 50
0 20 40 60 80 100
nsub=1*1016 ( cm-3 ) QINV = 7*1012 ( cm-2 )
Occupancy ( % )
tSi ( nm )
Si Si0.9Ge
0.1
Si0.7Ge0.3
Fig.5.9 Electron occupancy of valley Aas QINV =7*1012 cm-2 verse tSi for various Ge concentration
Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; and Temp=300K
0 10 20 30 40 50
0 20 40 60 80 100
nsub=1*1016 ( cm-3 ) QINV = 7*1012 ( cm-2 )
Occupancy ( % )
Si Si0.9Ge0.1 Si0.7Ge0.3
tSi ( nm )
Fig.5.10 Electron occupancy of valley Bas QINV =7*1012cm-2 verse tSi for various Ge concentration
Simulation condition:
Metal gate Φ1=Φ1=4.05eV; NSUB =1*1016 cm-3 tOX,1 = tOX,2 = 1.65*10-9 m; and Temp=300K