Chapter 3. Proposed Algorithm
3.6 Calculation of Number of Adder Bits for All Additions
3.6.2 Smart Sign Extension
The smart sign extension we propose is a systematic method to do sign extension for any input condition. The concept is similar to some booth multiplier, however, the booth multiplier is a regular structure and there is no systematic method proposed yet to the best of our knowledge. There are three cases are sorted out according to the inputs of the CSA. We sorted out all input combinations into three cases, with some common parts and some varied parts. We divide this method to two steps due to these three cases. The common first step is for the LSB handling. The second step handles sign extension for each case. Compared with the trivial sign extension, it has less number of adder bits.
First step:
We rename the three inputs to x, y and z in CSA according to their position of
MSB such that MSB(z)>= MSB(y) >= MSB(x). For input x, we extend its sign bit to 33
Figure 29. (a) Sign extension for input x (b) Direct wiring (c) First step complete
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MSB(y) as shown in Figure 29(a). Then for those inputs whose LSB position it's not the largest, we can do direct wiring to the sum and carry. Because there are two outputs and inputs, no full adder is needed. This means from the bit 0 to max(LSB(x), LSB(y), LSB(z)) − 1, no full adder is needed. The starting point of the series of full adders is max(LSB(x), LSB(y), LSB(z)). In Figure 29(b), the LSB positions of input x and input y are not the largest. So for the bits below LSB(z) (i.e., 0~LSB(z) − 1), no full adder is needed. In implementation, the input with the smallest position of LSB will be wired to the sum and the other input will be wired to carry because we want to balance the word length of carry and sum. The smallest position of LSB is 0 since we only implement the odd constant. The position of LSB of sum and carry become 0 and median(LSB(x), LSB(y), LSB(z) ), respectively. The following procedures of proposed algorithm will depend on the largest position of MSB. In Figure 29(c), it is the MSB(z). We find there are three cases would generate different results and should be discussed separately.
Second step:
We will divide this step into 3 cases according to the relative position of MSB(z) and MSB(y). Case 1 is MSB(z) > MSB(y) + 1, case 2 is MSB(z) = MSB(y) + 1 and case 3 is MSB(z) = MSB(y). These three cases contained all possibility because MSB(z) ≥ MSB(y) by our definition.
Case 1: MSB(z) > MSB(y) + 1
In this case, as shown in Figure 30, MSB(z) is at least 2 bits higher than MSB(y).
The example used in Figure 30 is a CSA with three inputs and their word lengths are 6.
The addition implemented by this CSA is 1<<4 + 1<<2 + 1. So the input x is 1, input
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y is 1<<2 and input z is 1<<4. The first 4 bits of sum and first 2 bits of carry are from
the first 4 bits of x and first 2 bits of y, respectively. In this case, even if we extend input x to the MSB(y), the bit at MSB(y) in input z is still not sign bit thus can’t be added to x and y directly. So an extra operation is needed. We will inverse the bits at MSB(y) of the input x and y and treat them as the unsigned bits. As shown in Figure 30(b), the equation of this operation is –x5 – y5 = –2 + x5+ y5. The logical value of a sign bit xs is actually –xs while a inversed Boolean variable xs is denoted by xs , To prove the equation is a tautology, the truth table of left part and right part of the equation is shown in Table 4.
After handling the sign bit of x and y, we can add these unsigned bits in the middle as shown in Figure 30(c). The end point of the series of the full adders becomes MSB(y) as shown in Figure 30(d). So in this case the number of adder bits of the addition is MSB(y) − max(LSB(x), LSB(y), LSB(z) ) + 1. In this example, the number of adder bits is 7 − 4 + 1 = 4. The bits s4~s7 in sum are the sum outputs and c3~c6 in carry are the carry outputs of the series of full adders. The bit c2 in carry is
Table 4. The truth table of –x5– y5 and –2 + x5+ y5. x5 y5 –x5 – y5 –2 + x5+ y5
0 0 –0–0 = 0 −2+1+1=0
0 1 –0–1 = –1 −2+1+0=–1
1 0 –1–0 = –1 −2+0+1=–1
1 1 –1–1 = –2 −2+0+0=–2
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actually 0, but we will treat it as a variable to make the carry to be a continuous vector for the simplicity of the whole process.
The −1 at MSB(y) + 1 can be used to transform the bit of input z at the same position from unsigned bit to sign bit. In this example, the equation is -z4. = -1 +z4 . The truth table of left part and right part of the equation is shown in Table 5 to prove the equation is also a tautology. The inversed z4 can be used as the sign bit of the sum and the remaining bit in the input z (i.e., the sign bit z6) can be wired to the carry. So both sum and carry are in the format of two's complement. The Table 6 shows the MSB and LSB of both sum and carry.
Table 6. The MSB and LSB of both sum and carry in case 1
MSB LSB
Sum MSB(y) +1 0
Carry MSB(z) median(LSB(x), LSB(y), LSB(z) ) Table 5. The truth table of –1 +z4 and –z4
z4 –1 +z4 –z4
0 –1+0 = –1 –1
1 –1+1 = 0 0
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Figure 30. Example of case 1 after sign extension
Case 2: MSB(z) = MSB(y) + 1
In this case, as shown in Figure 31, MSB(z) is at actually 1 bit higher than MSB(y).
The example used in Figure 31 is a CSA with three inputs is a CSA with three inputs and their word lengths are 6. The addition implemented by this CSA is 1<<3 + 1<<2 + 1. So the input x is 1, input y is 1<<2 and input z is 1<<3. The first 3 bits of sum and
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first 1 bit of carry are from the first 3 bits of x and first 1 bits of y, respectively.
The following procedure is very similar to the procedure in case 1. We will inverse the bits at MSB(y) of the input x and y and treat them as the unsigned bits.
This operation will increase an extra −1 at MSB(y) + 1. In Figure 31(b), this means –x5 – y5 = –2 + x5+ y5. After adding the middle bits, the bits s3~s7 in sum are the sum outputs and c2~c6 in carry are the carry outputs as shown in Figure 31(d). The number of adder bits is also MSB(y) − max(LSB(x), LSB(y), LSB(z) ) + 1. In the example used in Figure 31, it is 7 − 3 + 1 = 5. The bit c1 in carry is actually 0, but we will treat it as a variable like in case 1.
The different point is the bit at MSB(y) + 1 of input z is the sign bit of the input z.
In this example as shown in Figure 31(d), it is −1 − z5, not −1 + z5 in case 1. We will do 1-bit sign extension for input z and inverse the bit at MSB(y) +1 of input z. The inversed bit is used as the sign bit of sum and the extended bit is used as the sign bit of carry. In the example, the sign bit of sum is z5 and the sign bit of carry is z5. This operation is actually the equation –1 – z5= –1 + z5-2z5 = – z5 -2z5 . Then we can take z5 as the sign bit of sum and take z5 as sign bit of carry. The Table 7 shows the MSB and LSB of both sum and carry.
Table 7. The MSB and LSB of both sum and carry in case 2
MSB LSB
Sum MSB(y) +1 0
Carry MSB(z) +1 median(LSB(x), LSB(y), LSB(z) )
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Figure 31. Example of case 2 after sign extension
Case 3: MSB(z) = MSB(y)
In this case, as shown in Figure 32, MSB(z) equals MSB(y). The example used in Figure 32 is a CSA with three inputs and their word lengths are 6. The addition implemented by this CSA is 1<<2 + 1<<2 + 1. So the input x is 1, input y is 1<<2 and input z is 1<<2. The first 2 bits of sum are from the first 2 bits of x. In this example,
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due to LSB(y) = LSB(z), no bit is wired from input y or input z to the carry.
Since the bits at MSB(y) of three inputs are all sign bits, no extra operation is needed to add these three bits. The following equation −x5− y5− z5 = − (x5 + y5 + z5)
= −(sum + carry) = −sum −carry shows why no extra operation is needed. The sum and carry of the full adder can be used as the sign bit of sum and carry of CSA, respectively. The bits s2~s7 in sum are the sum outputs and c0~c6 in carry are the carry outputs of the series of full adders. The number of adder bits is also MSB(y) − max(LSB(x), LSB(y), LSB(z) ) + 1. In the example used in Figure 32, it is 7 − 2 + 1 = 6. The bit c0 in carry is actually 0, but we will treat it as a variable like in case 1. The Table 8 shows the MSB and LSB of both sum and carry.
Table 9 shows the equations of the position of MSB and LSB of sum and carry as well as the number of adder bits for all three cases. We can find the equations of the number of adder bits are the same for all three cases. And the equations of the position of LSB of both sum and carry is the same for all three cases, too. Only the equations of the position of MSB of sum and carry are slightly different for the 3 cases. By using these equations, we can calculate the required number of adder bits and the bit positions of the outputs if input bit information is available.
Table 8. The MSB and LSB of both sum and carry in case 3
MSB LSB
Sum MSB(y) 0
Carry MSB(z) +1 median(LSB(x), LSB(y), LSB(z) )
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Table 9. MSB and LSB of sum and carry as well as the number of adder bits for all three cases
MSB(sum) LSB(sum) MSB(carry) LSB(carry)
#adder bits
MSB(z)> MSB(y) +1
MSB(y) +1 0 MSB(z) median(LSB(x), LSB(y) , LSB(z) ) MSB(y)- max(LSB(x), LSB(y) , LSB(z) )+ 1
MSB(z) = MSB(y) +1
MSB(y) +1 0 MSB(z) +1 median(LSB(x), LSB(y) , LSB(z) ) MSB(y)- max(LSB(x), LSB(y) , LSB(z) ) + 1
MSB(z) = MSB(y)
MSB(y) 0 MSB(z) +1 median(LSB(x), LSB(y) , LSB(z) ) MSB(y) - max(LSB(x), LSB(y) , LSB(z) ) + 1
Figure 32. Example of case 3 after sign extension
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