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NO 2 with SnO 2 nanoribbon nanosensors at room temperature,” Angew

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Fig2-1 Top view and cross-sectional view of the inverse-T double-gate NW-SONOS device.

Fig. 2-2(a) Deposition of the n⁺-doped poly-Si.

Fig. 2-2(b) After removal of 100nm-thick n⁺-doped poly-Si in all regions except the central height of IVTG.

Fig. 2-2(c) After removal of the remaining 50nm-thick in-situ doped n⁺ poly-Si in all regions except the IVTG, leaving the final IVTG.

Fig. 2-2(d) Deposition of the inverse-T O/N/O stack and poly-Si active layer.

Fig. 2-2(e) Source/drain ion implantation.

Fig. 2-2(f) Definition of nanowire channel and source/drain.

Fig. 2-2(g) Deposition of the upper O/N/O stack and top gate.

Fig. 2-3 Dependence of the threshold voltage on channel length and drain bias. [2-17]

Fig. 2-4 Illustration of channel hot electron injection (CHEI) showing that under large drain bias, some channel electrons could become hot enough to surmount the Si/oxide barrier.

Fig. 2-5(a) Illustration of F-N tunneling occurring when V_otis larger than υ_b.

Fig. 2-5(b) Illustration of direct tunneling occurring when _X^∅^𝑏

ot＞ |Eot |＞^∅^b_x^−∅ⁿ

ot , where Eot is the electric field across the tunneling oxide.

N N i i t t r r i i d d e e

Si S i

X X

o_ot t

o o x x i i d d e e

J _DT

φ

N N i i t t r r i i d d e e S S i i

X X

o_ot t

o o x x i i d d e e

J FN

φ

V

Fig. 2-5(c) Illustration of Modified F-N tunneling occurring when n^∅^b_x^−∅ⁿ

ot >

E_ot >_x ^∅^b^−∅ⁿ

ot+ ε^ox xε_n _n.

Fig2-5(d) Illustration of trap assisted tunneling occurring when ^∅^b^−∅_xⁿ^−∅^t

ot > E_ot >

_x ^∅^b^−∅ⁿ^−∅^t

ot+ ε^ox xε_n _n

N N i i t t r r i i d d e e S S i i

X X

_oott

o o x x i i d d e e

J _TAT

φ

N N i i t t r r i i d d e e Si S i

X X

_oott

ox o x i i de d e

J _MFN

φ

(a)

(b)

Fig. 2-6 Illustration of band-to-Band tunneling (a) Deep depletion occurs in the gate-to-drain overlap region when there is a significant voltage drop across the gate and drain. (b) Tunneling paths in the deep depletion region.

Fig. 2-7 Data lost paths of SONOS flash memory.

●

TE

PF T-B

T-T

●

T-G

○

B-T

X

_BO

D

Si S i TO T O N N i i t t ri r i d d e e B B O O P P o o l l y y S S i i

Fig. 3-1 Cross-sectional TEM images of an ITG NW-TFT.

115Å NW 210Å

(a)

(b)

Fig. 3-2 (a) Transfer and (b) output characteristics of the ITG NW-TFT.

VG(V)

Fig. 3-3 On-current as a function of channel length under different operation modes.

Fig. 3-4 Off-current with different dielectrics conditions under different operation modes.

Fig. 3-5 Leakage under overlapped region of gate and drain via BTBT.

Fig. 3-6 (a) Top view of DG-NW-SONOS. Off-current as a function of (b) top width

Bottom Width of ITG (um)

(a)

(b)

Fig. 3-7 Leakage path in (a) ITG mode of operation and (b) TG mode of operation

(a) (b)

Fig. 3-8 Transfer characteristics under varying auxiliary gate bias for (a) ITG mode

and (b) TG modes of operation. VTH variation as a function of auxiliary gate bias for (c) ITG mode and (d) TG modes of operation.

V_ITG (V)

Fig. 3-9 Transfer curves under different P/E conditions.

Fig. 3-10 Voltage drop across nitride/oxide/Si on the side of the auxiliary gate under programming operations. Solid and dashed lines represent the potential profiles when the auxiliary gate is grounded, and biased positively, respectively.

-1 0 1 2 3 4 5

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6

P1(15,0,0,0)-1m E1(-12,0,0,0)-1.5s P2(15,2,0,0)-1m E2(-12,2,0,0)-1.5s

ID(A)

V_G (V)

~ 2.4 V

~ 2.6 V V_TG = 0 V

V_D = 0.5 V L = 0.4 um

(a)

(b)

Fig. 3-11 (a) Program efficiency under different programming conditions. (b) V_TH shift as a function of the top gate bias for the programming operation.

10^-6 10^-5 10^-4 10^-3 10^-2

(a)

(b)

Fig. 3-12 (a) Erase efficiency under different erasing conditions (b) V_TH shift as a function of the top gate bias for the erasing operation.

10^-6 10^-5 10^-4 10^-3 10^-2 10^-1 10⁰

Fig. 3-13 Voltage drop across nitride/oxide/Si on the side of the auxiliary gate under programming operations. Solid, dashed, and dotted lines represent the potential profiles with the auxiliary gate grounded, biased positively, and biased negatively, respectively.

Fig. 3-14 Voltage drop across nitride/oxide/Si on the side of the auxiliary gate under erasing operations. Solid, dashed, and dotted lines represent the potential profiles with the auxiliary gate grounded, biased positively, and biased negatively, respectively.

(a)

(b)

Fig. 3-15 Retention characteristics (a) transfer curves and (b) VTH shift with time.

-2 -1 0 1 2 3 4 5

Fig. 3-16 Schematic illustration of nitride trapped electrons escape by Frenkel-Poole emission and subsequent oxide trap-assisted tunneling

Fig. 3-17 Schematic illustration of the escaped path of tunneling oxide (TO) trapped holes in the erased state.

(a)

(b)

Fig. 3-18 (a) Transfer characteristics and (b) VTH variation with cycling proceeded.

-2 -1 0 1 2 3 4 5 6

Fig. 3-19 Schematic illustration of postulated distribution of trapped electrons in nitride layer after programming. Owing to the higher electric field with a larger curvature, more electrons are trapped in the nitride near the corners.

簡歷

姓名：戴君帆性別：女

生日：74.12.11 籍貫：台灣省高雄縣

住址：高雄縣大寮鄉鳳屏一路 301 號學歷：

國立交通大學電子研究所 2007.09〜2009.07 國立交通大學材料科學與工程學系 2003.09〜2007.06 高雄市立中正高中 2000.09〜2003.06

論文題目：

複晶矽奈米線通道在雙閘極倒 T 型結構上之製作與特性分析

Fabrication and Characterizations of Inverse-T Double-Gated Devices with Poly-Si Nanowire Structure

在文檔中複晶矽奈米線通道在雙閘極倒T型結構上之製作與特性分析 (頁 39-71)

with SnO 2 nanoribbon nanosensors at room temperature,” Angew

4-2 Future Work

NO 2 with SnO 2 nanoribbon nanosensors at room temperature,” Angew

N N i i t t r r i i d d e e

Si S i

X X

o o x x i i d d e e

J DT

φ

φ

N N i i t t r r i i d d e e S S i i

X X

o o x x i i d d e e

J FN

φ

V

N N i i t t r r i i d d e e S S i i

X X

o o x x i i d d e e

J TAT

φ

φ

φ

N N i i t t r r i i d d e e Si S i

X X

ox o x i i de d e

J MFN

φ

φ

TE

PF T-B

T-T

T-G

B-T

X

X

X

D

Si S i TO T O N N i i t t ri r i d d e e B B O O P P o o l l y y S S i i

115Å NW 210Å

簡歷

J _DT

J _TAT

J _MFN