Chapter 5 Simulation and Implementation Result for Digital TV
5.1 Specification of different levels
Table 22 Maximum frame rates (fps) for some different frame types [1]
Table 22 shows the maximum frame rates whose unit is frames per second (fps) for different frame types. The target of our CABAC encoder is designed to support the
In the 1080HD row we find that the maximum frame rates of the level 4.0 and the level 4.1 are the same, both of they are 30fps.
The difference of the level 4.0 and the level 4.1 can be observed in level limits shown in Table 23. The maximum macroblock processing rate (MB/s) of the level 4.0 and the level 4.1 are also the same, they are 245760 MB/s. The main difference of them is the maximum video bit rate. For the level 4.0, its maximum video bit rate is 20Mbps, and the level 4.1 is 50Mbps.
Table 23 level limits [1]
5.2 Simulation and implementation result
We take two 1080HD video sequences to simulate their characteristic curves shown as follows.
Figure 43 The characteristic curves of station video sequence (QP: 42 ~ 16)
Figure 43 shows the characteristic curves of station video sequence under the maximum operating frequency (110MHz) of our CABAC encoder, and the quantization parameter is modified from 42 to 16 whose interval is 2. According to these two characteristic curves of station video sequence, the proposed CABAC encoder can achieve 245760MB/s under 50Mbps; namely, it supports the specification of level 4.1. Besides, the PSNR of Y (luminance) is about 45 dB under the limits of level 4.1.
Figure 44 The characteristic curves of riverbed video sequence (QP: 42 ~ 16)
Figure 44 shows the characteristic curves of riverbed video sequence under 110MHz, and the quantization parameter is also modified from 42 to 16 whose interval is 2. The riverbed video can be regarded as worst case due to its fast motion (the bigger motion vector) causing massive data.
According to these two characteristic curves of riverbed video sequence, the proposed CABAC encoder also can achieve 245760MB/s under 50Mbps; namely, it also supports the specification of level 4.1. Besides, the PSNR of Y (luminance) is about 40 dB under the limits of level 4.1.
Table 24 The proposed arithmetic encoder comparing with the existing designs proposed Ha’[7] Shojaina’[8] Núňez’[9] Osorio’[10] Osorio’[11]
Spec. H.264 H.264 H.264 H.264 H.264 H.264
Table 25 The proposed CABAC codec comparing with the existing CABAC designs
proposed Shojania’[12]
Spec. H.264@MP H.264@MP
Function codec encoder
Technology 0.18 μm
UMC 0.18 μm
Frequency (MHz) 110 263
Processing cycle
(cycles/MB) 241 (QP=18) na
Encoding rate (Mbps) 91.79 (QP=18) 87 Bit-rate (Mbps) 49.4 (QP=18) na Encoding
PSNR_Y 44.778 (QP=18) na
Gate count
(without Memory) 38436 na
Gate count
(with Memory 1) 84873 area: 0.423 mm2 (~43k) Gate count
(with Memory 1+2) 173303 na
Encoding 1080 HD@30fps
proposed Chen’[13] Yang’[14] Yu’[15]
Function codec decoder decoder decoder
Technology 0.18 μm
(with Memory 1) 84873 138226 83157 na
Gate count ps: QP: quantization parameter
Memory 1: context model SRAM
Memory 2: row storage SRAM (RS SRAM)
Table 24 shows the comparison of the proposed arithmetic encoder and the other state-of-the-art designs. Table 25 shows the comparison of the proposed CABAC codec for encoding and decoding respectively. The choice of the quantization parameter (QP) is based on the maximum bit-rate of level defined by H.264/AVC
approximating the target bit-rate is 18 due to that the level 4.1 is the target specification of the proposed CABAC encoding. The maximum video bit-rate of level 4.0 is 20 Mbps, so the selected QP approximating the target bit-rate is 26 due to that the level 4.0 is the target specification of the proposed CABAC decoding.
The gate count of the context model dual-port SRAM is 46437 and of the row storage single-port SRAM is 88430. Besides, the RS SRAM is usually regarded as system level memory, so it isn’t counted into CABAC memory size.
Table 26 Percentage of the cycle reduction for the proposed three throughput promoting methods
Proposed method Target encoding mode
Percentage of the cycle reduction (%) Multi-Symbol Architecture Bypass 20.7 %
Pipeline Organization
Normal, Bypass, Terminal
(mainly for Normal) 50.6%
Case Efficiency Architecture
Normal, Terminal
(mainly for Normal) 47.5%
Table 26 shows the percentage of the cycle reduction for the proposed three throughput promoting methods. The detail estimations of executing cycle for these three throughput promoting methods are shown as follows respectively.
1.
For the Multi-Symbol Architecture (MSA) method:
Before adopting MSA:
84.21% bypass issue: 1 cycle 15.79% bypass issue: 3.776 cycles Average 1.438 cycles
After adopting MSA:
94.04% bypass issue: 1 cycle 5.96% bypass issue: 3.36 cycles Average 1.14 cycles
2.
For Pipeline Organization (PO) method:
Before adopting PO (under Normal encoding mode):
Average 3.99 cycles
After adopting PO (under Normal encoding mode):
Average 1.97 cycles
3.
For Case Efficiency Architecture (CEA) method (The result is under having adopted PO method):
Before adopting CEA (under Normal encoding mode):
Average 1.97 cycles
After adopting CEA (under Normal encoding mode):
Average 1.04 cycles
Chapter 6
Conclusion and Future Work
6.1 Conclusion
We propose three high throughput methods such as multi-symbol architecture, pipeline organization and case efficiency architecture to improve the process efficiency of our CABAC encoder. Besides, we also propose the hardware sharing methods to reduce the cost of CABAC codec. The CABAC decoding of our CABAC codec continues using [2] which we proposed in August 2006. Its throughput can achieve the specification of level 4.0; namely, it supports to decode the 1080HD H.264 video sequence at 30 fps. The maximum video bit rate which it supports is 20 Mbps. The detail of it is shown in [5].
In our work, we implement a H.264@main profile CABAC codec under UMC 0.18µm CMOS Process. The total gate count is about 38436 without embedded SRAM and about 173303 with embedded SRAM. The maximum operating frequency is 110 MHz. Both CABAC encoding and CABAC decoding of our CABAC codec supports to encode/decode 1080HD H.264 video, and they achieve the different levels of H.264 specification. For decoding is level 4.0, and for encoding is level 4.1; namely, it can encode 1080 HD video at 30 fps. The maximum video bit rate which the encoder supports is 50Mbps, and its PSNR of Y (luminance) is about 44.8 dB. It achieves the
“IBBBPBBBP…”.
6.2 Future work
Our CABAC codec can support the encoding and decoding for 1080HD at 30 fps, but it will be insufficient to satisfy the requirement of the future digital TV. In order to achieve the high quality video, the frame rate of 30fps doesn’t correspond to the requirement of our digital TV market. The high resolution and high frame rate becomes the target of the human life. Hence, the large frame and high speed video playing is essentially for the digital TV application. To play the videos of 1080HD at 60fps is the basic requirement for the point view of CABAC. Thus, CABAC has to achieve the 1080HD of 60fps under the maximum bit-rate of 50,000,000 bit-per-second, which means the specification of level 4.2 for H.264/AVC is the future work for CABAC.
Comparing to the level 4.0 and the level 4.1, it has to accelerate CABAC for 5 times.
Hence, the acceleration of CABAC is the essential work in the advanced application.
6.3 Discussion from H.264/AVC system view
In this section, we discuss the proposed CABAC codec system from the whole H.264/AVC system view. The CABAC system is the sub-system of H.264/AVC system.
This discussion focuses on the interface issue between the CABAC sub-system and the next sub-system, and we divided the discussion into the CABAC encoder and the CABAC decoder these two aspects.
For CABAC encoder, its last sub-system is DCT and Quantization. The CABAC
bit-stream. Under considering the throughput matching issue, we design the syntax element buffer storage shown in Figure 41 to buffer the throughput mismatch. The CABAC encoder is the termination of the whole H.264/AVC encoding flow, and next to it is the forward error correction (FEC) which belongs to channel coding. We design two levels buffer storage between CABAC encoder and FEC, and the purpose of it is accumulating variable length bit-stream. Besides, the throughput mismatch buffer storage is design in FEC system.
Figure 45 System block diagram of H.264/AVC decoding for main profile
For CABAC decoder (CABAD), the syntax parser dominates that which scheme (CABAD, UVLD, or CAVLD) is selected for current entropy decoding. Figure 45 shows the system block diagram of H.264/AVC for main profile. The syntax parser belongs to the system level control signal, and it employs in decoding the bit-stream on NAL layer, picture layer, and slice layer, shown as Figure 46. The syntax parser is also the top module to control all sub-system such as CABAD, VLD, intra-prediction, inter-prediction, IDCT, and so on. Hence, CABAD is the passive unit and is requested by the syntax parser and decodes the bit-stream of the macroblock layer in Figure 46.
The bit-stream is also fetched through the syntax parser.
NAL Layer SyntaxNAL
Element NAL unit SyntaxNAL NAL unit
Element SyntaxNAL NAL unit
Element
Figure 46 Bit-stream structure of H.264/AVC
The CABAC decoder is the first sub-system of the whole H.264/AVC decoding flow. As CABAC encoder, the syntax element buffer storage is also designed between the CABAC decoder and the next sub-system. Between the CABAC decoder and channel decoder (FEC), we design two levels buffer storage to buffer the interacting throughput mismatch.
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作 者 簡 歷
姓名 ：林秉昌
出生地 ：台灣省台南市
出生日期：1976. 05. 25
學 歷： 1983. 9 ~ 1989. 6 高雄縣立阿蓮國民小學
1989. 9 ~ 1992. 6 高雄縣立阿蓮國民中學
1993. 9 ~ 1996. 6 國立台南二中
2000. 9 ~ 2004. 6 私立義守大學
電機工程學系 學士
2005. 2 ~ 2007. 1 國立交通大學 電機學院
IC 設計產業研發碩士班 碩士
發 表 論 文
z Yi-Hong Huang, Ping-Chang Lin, Chen-Yi Lee,” A High-Throughput SRAM-Based Context Adaptive Binary Arithmetic Decoder (CABAD) for H.264/AVC”, Proceedings of the 17th VLSI/CAD Symposium, August 2006.