Chapter 4 Probability-Based Static Scaling Optimization for Fixed Wordlength FFT
4.4 Scaling Optimization
4.5.3 SQNR for a real case study
In this experiment, we use a piece of 16-bit 11 KHz audio in WAV format from Wikipedia [80]. The PMF of the audio data is given in Figure 27, which is very close to a normal distribution with a mean of zero and a standard deviation of 0.168. Table 13 presents the number of integer bits of each stage and the scaling optimization outcomes for 256-point radix-2 FFT. Oppenheim’s method [49], which increases the integer part by one bit for every single stage, gives a moderate result (SQNR=46.07dB). Ramakrishnan’s method [50], which increases the integer part by
Figure 26 SQNR vs. standard deviation (radix-4, input in 12b1f).
Figure 27 The PMF of the piece of music.
0 5 10 15 20 25 30 35 40 45 50
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
SQNR (dB)
Standard deviation σ
Oppenheim [49]
BFP [1]
proposed Ramakrishnan [50]
one bit for every two stages, suffers a serious overflow problem under this particular input and the resultant output SQNR is thus extremely low (10.18dB).
Since the additional scale factor tables in BFP determine an appropriate number format by detecting the largest value for each block, the 16-bit wordlength is long enough to preserve the high accuracy and significantly diminish the chance of overflow. Thus, the BFP method [1] achieves the best SQNR result. Meanwhile, if a uniformly distributed input is assumed in our proposed method (not the correct distribution), the output SQNR can achieve 51.75dB, which is still much higher than that of the Oppenheim’s method [49]. Moreover, if the correct PMF of that piece of music (normal distribution with a mean of zero and a standard deviation of 0.168) is used in the analysis, the resultant output SQNR is even better (54.04dB). The experimental results here demonstrate that our proposed method can offer excellent quality of result if the PMF of the input is known in advance. Even if the PMF of the input is unknown, the quality of result is still fairly good in this experiment when compared with those two previous static scaling works.
Table 13 The Scaling optimization outcomes for 256-point radix-2 FFT
Method
Integer bits of each stage
SQNR
1 2 3 4 5 6 7 8
Oppenheim [49] 2 3 4 5 6 7 8 9 46.07dB
Ramakrishnan [50] 2 2 3 3 4 4 5 5 10.18dB
BFP [1] N/A 85.67dB
Proposed
(Uniform distribution) 2 3 4 5 6 6 7 7 51.75dB Proposed
(Normal distribution) 2 3 4 5 5 6 6 7 54.04dB
4.6 Summary
In this dissertation, we present an efficient static scaling technique for output SQNR optimization targeting FFT processor designs with the fixed wordlength constraint. Unlike most of conventional methods, it relies on fast probability-based analysis instead of time-consuming simulation to precisely model the noises induced from quantization and saturation. It works with various FFT sizes, radices, wordlengths, and most commonly presumed input distributions. The experimental results clearly show that the proposed technique is superior to existing static scaling approaches in all circumstances [49, 50]. Specifically, our technique can generate an 8192-point radix-2 FFT implementation with three bits shorter in wordlength than Oppenheim’s method [49] while still achieving the same output SQNR, which implies a significant improvement in area, latency, and power consumption. Besides, it generally performs as nearly well as the BFP-based dynamic scaling technique [1], which requires an extra hardware unit. Therefore, we believe our fast static probability-based scaling optimization technique is very practical and helpful for creating area-efficient fixed-wordlength (e.g., memory-based) FFT processor designs
Chapter 5
Conclusion and Future Works
5.1 Conclusion
Since the DSP algorithms take an important role in the communication systems, the hardware implementations must carefully consider many parameters, such as the bitwidth, the base architecture, and the number scaling. In order to deal with the design issues at crafting the DSP algorithms, we propose three techniques in this dissertation: 1) a bitwidth-aware synthesis algorithm for MCM designs, 2) an EMDC-based FFT architecture, and 3) a static scaling technique for pipelined FFT processor designs.
First, we present an ILP-based bitwidth-aware area minimization algorithm for MCM designs, which points out that the total adder bit count rather than the total adder count can better estimate the hardware cost in a real implementation. Then, for a given MCM design, those target constants are first represented in a specified number format. Next, a subexpression graph is created to record all feasible decompositions for every target constant. The graph also keeps track of the required adder bitwidth as well as two subexpressions for every decomposition. At last, the area minimization problem is formulated as a set of ILP constraints derived from the subexpression graph and optimally resolved within an acceptable runtime.
Then, we propose an expandable multi-path delay commutator (EMDC) based FFT architecture. We show that the proposed architecture can be easily and flexibly expanded to satisfy throughput-hungry applications. In addition, a parameterizable
hardware generator is also developed to automatically produce the specified HDL code so that the design cost and time can be drastically minimized. Finally, the theoretical analyses and/or experimental results demonstrate that the proposed architecture does consume less area and power than the existing foldable Pease architecture under the same throughput constraint.
Finally, we present an efficient static scaling technique for output SQNR optimization targeting FFT processor designs with the fixed wordlength constraint.
Without using the time-consuming simulation to precisely model the induced quantization and saturation noises, we proposed a probability-based static scaling analysis to model the probabilistic behavior of the output signal at each stage. It works with various FFT sizes, radices, wordlengths, and most commonly presumed input distributions. The experimental results clearly show that the proposed technique is superior to existing static scaling approaches in all circumstances [49, 50].
Specifically, our technique can generate an 8K-point radix-2 memory-based FFT processor without compromise in the output SQNR. Besides, it generally performs as nearly well as the BFP-based dynamic scaling technique [1], which requires an additional hardware unit.
5.2 Future Works
Although the problem of multiplier-less constant multiplication has been studied for many decades, it still attracts a large number of attentions. In general, the digit-based algorithms can provide a better solution than the graph-based algorithms, but the quality of result of the digit-based algorithms is highly depended on the decomposition method. For example two numbers, 3 and 29, can be decomposed as follows in MSD form:
MSD graph-based algorithm, RAG-n [14], allows the usage of right shifters and accepts a mapping result that induces extra adders for a coefficient to maximize the global subexpression sharing, it is capable of finding a design solution that is not presented in the digit-based algorithms. Figure 28 shows an alternative design that only two adders are needed. Obviously, the solution is outside of the current digit-based decomposition. Thus, the exploration of finding a valid and a limited number of decomposition is a research topic.
Furthermore, in order to achieve the high-data-rate communication, many new algorithms are proposed. For example, polor codes [81, 82] derived from the concept of channel polarization have emerged as the important channel codes for the capacity-achieving property. The hardware architecture of a (8, 4) polar code is given in Figure 29. Similar to the FFT core design, the same techniques on the hardware folding and the scaling analysis can be applied to the polar decoder. However, the data
Figure 28 An alternative implementation for the number 3 and 29.
+
propagation is always performed in logarithmic domain which is not a linter time-invariant (LTI) operation. The non-linear property needs further research to apply the proposed techniques.
Figure 29 The factor graph of (8,4) polar code.
=
=
=
=
=
=
=
=
=
=
=
= Stage 1 Stage 2 Stage 3
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