Constant On-time Control
The basic concept of constant on-time control is introduced in chapter 2. Besides, constant on-time control is more popular than constant off-time control owing to the conversion efficiency at light loads. In this section, we will analyze the system stability of constant on-time control in time-domain and frequency-domain, respectively.
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Fig. 16. Small ESR caused double-pulse problem.
In conventional constant on-time control with small ESR value on the output capacitor, the converter is easily affected by the noise due to small output ripple, which is dominated by the ripple on the output capacitor. Besides, the loop phase delay may further decrease the system stability owing to the double-pulse problem. As illustrated in Fig. 16, the delayed output voltage, Vout, is unable to reach the reference voltage, Vref, even after the first constant on-time period. Consequently, the second constant on-time is inserted after the minimum off-time period to raise Vout higher than Vref. The constant on-time control can’t regulate the output voltage within one switching cycle and thus induces the double-pulse problem. That is, the system needs two or more switching periods to regulate the output voltage. The output voltage ripple is increased to ensure the system stability due to the decreased switching frequency.
In Fig. 16, the slope of the inductor current is m, which is expressed in Eq. (17), during the on-time period.
29 variation during one on-time period.
( ) 1 ( )
LThe output ripple is composed of three components including ESR part, capacitor part and ESL part. In Eq. (18), the second term indicates the contribution of the ESR while the third term represents the ripple on the output capacitor. The last term indicates the contribution of the ESL. To ensure the system can be regulated for each switching cycle. At t=TON, the value of Vout(TON) needs to be larger than Vref as shown in Eq. (19).
The arrangement of Eq. (19) can be expressed in Eq. (20).
2
Generally speaking, as the ESL of output capacitor is not sufficient large, the criterion of system stability is decided by the time constant, ResrCO, and it can be derived in Eq. (21).
2
ON esr O
R C T (21)
That is, the time constant, ResrCO, must be larger than half of on-time period to ensure
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the system stability. Consequently, the ripple contributed by the ESR dominates the whole output ripple to guarantee the system stability. Therefore, a large ESR is utilized in the conventional constant on-time control at the sacrifice of large output ripple. However, for certain applications of output capacitor combination, as the total ESL of the output capacitor becomes larger, the double-pulse problem will appear as shown in Fig. 17. At the beginning of the minimum off-time, the voltage across ESL will step down since the negative slope of inductor current. If the voltage spike on the ESL is larger enough to let the output voltage smaller than Vref, the second constant on-time period will appear. Large ESL will cause the system unstable due to large step voltage on ESL.
Fig. 17. Large ESL caused double-pulse problem.
Considering the noise causes the variation of reference voltage as shown in Fig. 18, the rising edge of the power MOSFET switching signal is perturbed to induce a large jitter. The time deviation of tn indicates the jitter caused by the noise. Unfortunately, the switching frequency can’t be kept constant and thus the system suffers from the electromagnetic interference (EMI) problem. The performance of system is seriously deteriorated. Thus,
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small jitter and constant switching frequency are also demanded in the constant on-time control.
Fig. 18. The noise effect on feedback voltage and power MOSFET switching signal.
Fig. 19 shows the enlarged waveform of Vfb with a negative slope of a when the inductor current decreases. If the slope becomes more sharp and has a value of a’, the new waveform of Vfb’ decides another switching period. Once the noise perturbs the reference voltage from Vref to Vref’, the variation of switching period can be decreased from t1 to t0
due to the sharp slope. Basically, the slope can be expressed as Eq. (22), which is proportional to the value ESR. Eq. (22) is under the assumption of neglecting the voltage across ESL and capacitor. In other words, the ESR value can determine the system stability in the constant on-time control. Thus, the conventional design uses a large ESR value to suppress the jitter problem. A lower jitter effect can be derived by a larger ESR value. But, a large ESR value will cause the increase of output ripple and transient dip voltage.
2
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Fig. 19. Enlarged waveform of feedback voltage and reference voltage that affected by noise.
A large ESR is usually selected to avoid the double-pulse problem. In other words, the ripple content at the output voltage should have a minimum value to maintain the system noise margin. The larger ESR value causes the larger output voltage ripple. For the purpose of solving the dependence of ESR value, the proposed constant on-time control DC-DC converter provides sufficient noise margin without using large ESR capacitor so that the low jittery behavior can be attained to eliminate the double-pulse problem.
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3.2 Topology of the Proposed System
Fig. 20. Topology of proposed constant on-time control DC-DC buck converter.
Fig. 20 shows the proposed constant on-time control DC-DC converter without ESR compensation. The Vout is regulated by the loop comparator through the voltage divider, RFB1 and RFB2. The Vr from the zero ESR compensation circuit and the feedback voltage Vfb
are compared by the loop comparator. The output of loop comparator is used to decide the timing to store energy in the inductor. The minimum off-time signal Voff is used to provide a minimum off-time period to ensure a minimum off-time during startup interval and extreme duty condition. Besides, the zero current detector signal, Vzcd, is used to avoid the reverse inductor current. The deadtime control circuit is used to avoid the short-through current.
The output stage of converter can be viewed as an integrator. As a result, the output voltage ripple can be recognized as an integration of the inductor current ripple. Therefore, the inductor current information can be derived by differentiating the output voltage. As shown in Fig. 21, the proposed zero ESR compensation technique generates a differential
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signal Vs to get the inductor current information. Vs can be viewed as a ramp signal, providing good noise immunity for system operation [19]. However, the ESL, Lesl, on output capacitor CO will distort the differential signal of the conventional differentiator. The output voltage Vout contains high frequency component caused by Lesl. It will deteriorate the system stability due to the double-pulse problem. Afterwards, the Vs goes through the reflector, which produces the reflective signal Vr. Once the inductor current rises up, Vr
starts to fall. Fortunately, the Vr can generate a sufficient noise margin at the input node of loop comparator.
crooked curve due to small ESR
small ESR effect
off-time period on-time period
Fig. 21. The concept of the proposed technique.
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Fig. 22. The operational scheme of the proposed technique.
At the beginning of the inductor charging period, the control signal Vclr clears the on-time timer in order to recount on-time period. As on-time period ends up, the signal Vreset
goes from low to logic high. The high-side power MOSFET SWP turns off to start the inductor discharging period to release the stored energy. When the Vr rises above the Vfb, the high-side power MOSFET SWP turns on and the on-time timer is cleared, again, to restart the inductor charging period as shown in Fig. 22. The Vfb is compared with the Vr, which represents the opposite shape of the differential signal Vs. The ripple of Vfb is much smaller than Vr. That is, Vr can be regard as the feedback voltage in the original constant on-time control and the Vfb can be regard as the reference voltage. In other words, the Vfb
can be viewed as the peak voltage of the Vr. When the Vr starts to decline from the level of Vfb, the slope of Vr is sufficient steep and thus it can provide good noise immunity. That is, a sufficient noise margin is proposed to avoid the double-pulse problem.
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Chapter 4
Circuit Implementation
In this chapter, the sub-circuits of the proposed constant on-time control DC-DC buck converter are introduced. In section 4.1, zero ESR compensation circuit is presented. It consists of differential circuit part and reflection circuit part. In section 4.2, the on-time timer is presented. It generates one on-time pulse each switching cycle to control switches.