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Study on Stress Behavior of MIM Capacitors by Constant Voltage

Constant Voltage Stress

Fig. 6-1 (a) C-V and (b) J-V characteristics of the 30 nm TiHfO/TaN MIM capacitors with Ni or TaN top electrode……….68 Fig. 6-2 (a) The temperature-dependent normalized capacitance and (b) ΔC/C-V

characteristics of TiHfO MIM capacitors with Ni or TaN top electrodes………69 Fig. 6-3 The effect of constant-voltage stress on (a) VCC-α (b) J-V and (c) TCC of [Ni or TaN]/TiHfO/TaN capacitors………71 Fig. 6-4 (a) ΔC/C as a function of stress time and (b) extrapolated ΔC/C for a 10

year lifetime as a function of stress voltage for [Ni or TaN]/TiHfO/TaN

Chapter 7 Using High Work Function Ni Metal to Improve the

Stress Reliability of RF SrTiO

3

MIM Capacitors

Fig. 7-1 Band diagrams before contact for (a) TaN or (b) Ni /SrTiO3/TaN MIM capacitors………..………..78 Fig. 7-2 C-V characteristics of (a) [Ni or TaN]/STO/TaN at 25ºC or 125ºC and (b)

J-V characteristics of [Ni or TaN]/STO/TaN under CVS test at 25ºC or

125ºC………..79 Fig. 7-3 (a) Measured and simulated two-port S-parameters for SrTiO3 MIM

capacitors (b) The equivalent circuit for capacitor value extraction from measured S-parameters……….…………..80 Fig. 7-4 The ΔC/C of [Ni or TaN]/STO/TaN capacitors which measured (a) at 25ºC and 125ºC, (b) fresh and stressed devices and (c) stressed devices at 25ºC and

125ºC……….…….82

Table 3-1

Table Caption

Chapter 2 Performance Improvement of TiHfO MIM Capacitors by

Using a Dual Plasma Treatment on Lower Electrode

Table 2-1 Comparison of MIM capacitors having various dielectrics and metal electrodes………..…………22

Chapter 3 Low Temperature Crystallized TiO

2

Dielectrics for

DRAM Application

Comparison of MIM capacitors which have various dielectrics and metal electrodes………33

Chapter 4 Improved High-Temperature Leakage in High Density

MIM Capacitors by Using a TiLaO Dielectric and an Ir

Electrode

Table 4-1 Comparison of MIM capacitors with various dielectrics and metal electrodes………..43

Chapter 5 MIM Capacitors Using a High-κ TiZrO Dielectric for

Analog and RF Applications

Table 5-1 Comparison of MIM capacitors with various dielectrics and metal electrodes………54

Chapter 1

Introduction

1.1 Motivation to Study High-κ Dielectrics

In the scaling of CMOS devices, reducing the thickness of gate stack with lower leakage current plays an important role. Although the leakage current of the devices with the same gate dielectric reduces with the scaling gate length and width, that leakage current density increases with the scaling of gate dielectrics exponentially.

Therefore, the gate leakage current increases as the device size decreases. The larger leakage current will not only cause the higher power consumption but also degrade

the reliability of the devices.

Using the material with high dielectric constant (high-κ), the physical thickness

of the dielectric in the devices can be increased without sacrificing capacitance density. According to the ITRS (International Technology Roadmap for Semiconductor) [1-1] of SIA as shown in Figure 1-1, the thickness of gate oxide have to be below 1nm after 2009. Moreover, the gate length and bias voltage reduces by 11

% every year while the driving current has to be maintained. Therefore, the continual scaling of gate dielectric is a trend in CMOS technology. Even some high-κ

those at RF region could possibly degrade. Therefore, it is necessary to find out the high-κ dielectrics that can exhibit good analog characteristics for RF application.

After years of research, some high-κ dielectrics (HfO2, ZrO2 and TiO2) have

been widely studied and related characteristics and issues of these materials have also been reported. In addition, high-k gate dielectrics and metal gate electrodes has been introduced in 45nm and achieved good performance for both NMOS and PMOS

transistors. To build next-generation transistor, it is important to find out the most suitable high-κ dielectrics for the use of CMOS devices built upon conventional Si

substrate or non-silicon high-mobility materials, such as Ge or III-V substrates.

1.2 The Background of High-κ Dielectrics used for DRAM and RF Application

The first of the above requirements is that the oxide’s κ value should be over 12,

preferably 25-30. There is a trade off with the band offset condition, which requires a reasonably large band gap. Figure 1-2 and Figure 1-3 show that the κ of candidate

oxides tends to vary inversely with the band gap, so we must accept a relatively low κ value. There are numerous oxides with extremely large dielectric constant, such as

SrTiO3 (κ ~50-200) or BaSrTiO3 (κ ~250-350), which are candidates in DRAM capacitors, but these materials have a small conduction band offset and band gap.

According to International Technology Roadmap for Semiconductors (ITRS), the continuous increasing capacitance density (ε0κ/tκ) is required to scale down the

device size of Metal-Insulator-Metal (MIM) capacitors that are widely used for Analog, RF and DRAM functions. To meet these requirements, the using higher κ

dielectric is the only choice since the decreasing dielectric thickness (tκ) increases the

unwanted leakage current exponentially. To achieve this goal the only choice is to increase the κ value of the dielectrics, which have evolved from TiO2 (κ~50-80) [1-13], TiHfO (κ~40-50) [1-6], TiTaO (κ~40-50) [1-7]-[1-9] to SrTiO3 (STO;

κ~50-200) [1-10]-[1-12].

It has been reported that titanium oxide (TiO2) exhibits some better properties

that is the good thermal stability when it was integrated with TiN electrode. It allows TiO2 shows dielectric characteristics after high temperature process for silicide formation. Besides, the heat conduction rate for TiO2 is higher than that for SiO2. With the scaling of integrated circuits, the issue of power dissipation should also be taken into account. Although TiO2 exhibits the above merits, there are still some other issues that should be considered and overcome such as the higher leakage current than that of other dielectrics with the same effective oxide thickness, lower breakdown voltage and interface oxide layer formation after post implant RTA. However, it has been reported that thickness of the interface oxide layer can be reduced by using NH3 plasma treatment, but the effect of N+ plasma for bottom interface is limited beyond 1nm of EOT.

SrTiO3 (STO) has been widely studied as a substrate for high TC oxide superconductors. Its alloy BaSrTiO3 has been widely studied as a high dielectric constant dielectric for DRAM capacitors. SrTiO3 (STO) well-known perovskite-type structure is a potential candidate to increase the κ value beyond a value of 45. To achieve the high κ value, the STO requires a heat treatment at 450~500oC under an oxygen ambient for crystallization. Therefore, it also requires a Pt or RuO2 lower electrode to withstand the high temperature oxidation, but the high cost and

The continuous scaling of design rules for DRAM leaves us some difficulties to overcome. From the requirement of stacked capacitor showed in Fig. 1-5 (a) and trench capacitors showed in Fig. 1-5 (b) in ITRS roadmap, the major obstacle in scaling of the DRAM capacitor is scaling of teq for capacitor dielectrics. According to 2007 ITRS roadmap [1-1], one of the difficult challenges is scaling of the physical

dielectric thickness, Tphy (physical thickness) while maintaining dielectric constant and leakage current of dielectrics. In general, as the physical thickness of high-κ

materials such as SrTiO3 decreases, the dielectric constant decreases and the leakage current increases. This means higher Tphy while decreasing Teq.. In the G-bit DRAM generation, the memory cell density is so high that the cell space can only allow dielectrics no thicker than 20nm. This requirement of thickness for dielectrics makes it impossible to use quaternary metal oxide such as SrTiO3 or BaSrTiO3 as the dielectric layers. Because of the difficulty of conformal CVD for these quaternary oxide, the high aspect ratio of the trench for DRAM seems to be the other challenge to integrate these dielectrics into G-bit DRAM generation.

Owing to the high dielectric constant, good step coverage and minimum thickness limit, simple metal oxide such as Ta2O5, Al2O3, ZrO2, HfO2,La2O3 and SrTiO3 are thought the promising materials in the application of DRAM. Among the

discontinuity (ΔEc ~1.4-2.3 eV), dielectric constant (κ ~25-30) and bond enthalpy (Figure 1-6) to prevent from higher leakage current and degradation after high temperature process. Similar to high-k/Si CMOSFET, the larger conduction band offsets is the better choice for MIM capacitor.

Due to their moderate permittivity, it is difficult to achieve dielectric structures

with an EOT well below 1.0 nm. One approach to increase permittivity is combining it with very high-κ material, such as TiO2 with a permittivity value of 50-80 due to a

contribution from soft phonons. Chiang et al. reported that permittivity of approximately 50 have been obtained from physical-vapor deposited TiHfO thin film.

Therefore, TiO2-based material which combined high-κ and large conduction band offset materials will be a good solution for logic devices (metal-gate/high-κ) beyond

32nm node or DRAM technology beyond 60nm node.

To fabricate monolithic microwave integrated circuits successfully, both active and passive components with reliable, repeatable and predictable performance are required. Among them, the capacitor used in filtering, decoupling and network matching plays a significant role in front end or mixed signal circuits. The requirement for capacitors includes high capacitance density, low voltage coefficients, good capacitor matching, precision control of values and low parasitic effects. The

occupied by capacitors, is utilizing thin dielectrics with high dielectric constant.

Recently, some kinds of dielectrics and approaches have been proposed to achieve the goal of high capacitance and the other good performance. Instead of SiO2 with low dielectric constant, Si3N4 deposited by plasma enhanced chemical vapor deposition (PECVD) has been studied in the past years. Although Si3N4 shows good linearity and reliability, the capacitance density still needs to be increased. However, Si3N4

fabricated by PECVD has the minimum thickness limit and the defect density of nitride is higher than that of other high-κ dielectrics. Therefore, high-κ dielectrics

with good linearity and quality can be a choice to develop the innovative and useful RF capacitors.

1.3 The Background of Metal Electrodes

MIM structure (metal-insulator-metal) can reduce contact resistance and raise storage charge comparing to MIS structure. MIM capacitors are integrated in the backend process. The maximum temperature of deposition is restricted by the thermal budget of back end processes.

As DRAM density increasing, devices shrinkage and higher charge storage is inevitable. It is difficult for conventional MIS structure to meet the requirements due to high-temperature-process limitation, so MIM structure is expected to apply in trench DRAM process. On the other hand, since high-k material interacts with bottom electrodes during dielectric activation, an interfacial layer will be formed between high-k material and metal electrode. The bottom interface will degrade the property of the dielectrics, such as interface roughness, interface stress, electron barrier height and thermal stability, etc.

Metal electrodes have been applied for CMOS devices as a gate material in 45nm process and for DRAM devices as electrodes in 90nm process. A full MIM structure with high-k dielectric may be required for the DRAM technology of 2009.

The use for electrodes of MIM capacitors, such as TiN, TaN, Ru, Ir, Ni and Pt, are deposited by using CVD, ALD or MOCVD methods. MIM capacitors used for

deposition process (typically less than about 450oC)

1.4 The Deposition method of High-κ Dielectrics

Some methods to deposit ultra thin high-κ dielectrics on substrates have been

proposed in recent years and various methods exhibit the merits as well as some other

issues that have to be solved.

Among the proposed high-κ dielectrics, HfO2, La2O3 and ZrO2 show the

promising properties and are thought the candidate of the next generation. It has been reported that many process technologies can be used to deposit high quality HfO2. Atomic layer chemical vapor deposition has attracted much attention due to its self-limit and mono-layer deposition properties. Atomic layer chemical vapor deposition (ALCVD) is the method using MCl4 (M: Hf, Ti, Zr…) and H2O as sources to deposit HfO2 as well as high-κ dielectrics. The precursors are introduced into the heated chamber and substrates. The reaction only happens on the substrate surface instead of the deposited layer and one layer is deposited at a time. Thus, the thickness of dielectrics can be controlled precisely and is dependent on the process cycles linearly. Although the excellent uniformity and initiation of deposition can be achieved on SiO2 and Si3N4, the deposition directly on H-terminated Si substrate can lead to rough surface. However, H-terminated Si substrate is inevitable after HF dipping. Therefore, the improvement of process precursor is the key point to

extensively used in VLSI fabrication. The deposition of dielectrics has been carried out using metal organic precursor vapor. The precursors are introduced into low-pressure chamber and the substrate is heated to some suitable process temperature. The uniform and conformal deposition of dielectrics can be obtained.

That is the reason why MOCVD process is integrated into fabrication process flow extensively. Although MOCVD suggests many merits, it still exists some issues such as the carbon contamination and the impact of precursors to the environment, health and safety.

Depositing the metal or metal oxide directly on the substrate using PVD method followed by thermal oxidation and annealing is the other method to deposit high quality dielectrics. In the past, many studies on the dielectrics by PVD have been reported and the related process flow was described as the following. The pre-clean Si substrate is loaded into high vacuum chamber immediately to prevent from the formation of native oxide. Then, the bottom electrode was deposited using reactive dc magnetron sputtering with a mixed gas of oxygen and argon. The deposited dielectrics was then followed a full oxygen ambient under 400oC furnace-annealing to finish the dielectric activation. Although the flow is already the standard DRAM process, the poor low-k interlayer and the property for easy-to-crystallize are still the issues that

dielectrics with a stable thermal property, both of the issues mentioned above can be

minimized.

In this study, we used the PVD method to fabricate the high-κ dielectrics.

Instead of plasma treatment, we utilized NH3 plasma treatment to prevent from the formation of interface oxide. The pre-cleaned wafer was loaded in E-beam evaporator under high vacuum condition and then oxidized at 400 oC in O2 ambient followed by annealing. The devices using TiHfO, TiLaO, TiZrO and SrTiO3 are fabricated and measured at high and low frequencies.

1.5 The Measurement and Analysis of the MIM Capacitors

To investigate the electrical characteristics of our devices, we measured the leakage current, stress induced leakage current using HP 4156A semiconductor parameter analyzer. Besides, HP4284A precision LCR meter was used to evaluate the capacitance and the conductance ranging from 100 kHz to 1 MHz. Furthermore, to investigate the characteristics of our devices at the frequency above 1 MHz, we measured the scattering parameter using HP8510C network analyzer and the test set. .

Fig. 1-1 The International Technology Roadmap of SIA for Semiconductor 2007 [1-1]

Fig. 1-2 Comparison of the calculated conduction band offset and experimental values for various gate oxides, by various authors [1-13]

Fig. 1-3 Static dielectric constant versus band gap for candidate gate oxides, after Robertson [1-13]

Fig. 1-4 Static dielectric constant versus band gap for candidate gate oxides, after Robertson [1-13]

(a)

(b)

Fig. 1-5 The 2007 International Technology Roadmap for Semiconductors for DRAM (a) stacked capacitors and (b) trench capacitors.

20 30 40 50 60 70 80 0

200 400 600 800 1000 Si

Fig. 1-6 Bond enthalpy for M-O, M-N and M-C in the Periodic Table

Metal-Oxide Metal-Nitride Metal-Carbide

Bond Enthalpy (KJ/mol)

Atomic Number

Ti

HfTa Zr La

Tb

Yb Ir

Chapter 2

Performance Improvement of TiHfO MIM Capacitors by Using a Dual Plasma Treatment of the Lower

Electrode

2.1 Introduction

The technology roadmap for Metal-Insulator-Metal (MIM) capacitors [2-1]-[2-16],

which are used for analog, RF and DRAM functions in Integrated Circuits, specifies a continuing increase of the capacitance density (ε0κ/tκ) and lower leakage currents. To achieve this goal, higher κ TiO-based dielectrics - such as TiTaO, TiLaO, TiHfO

[2-11]-[2-13] and SrTiO3 (STO) [2-14]-[2-16] – are need for the MIM devices.

Unfortunately, there is an interfacial reaction, during device processing, at the lower high-κ dielectric/metal interface [2-14]. This reduces the capacitance density and

increases the leakage current, and this reaction increases in importance as the capacitance equivalent thickness (CET) decreases to 1 nm. To inhibit the reaction a nitrogen plasma treatment can be applied to the TaN or TiN bottom electrodes [2-14]-[2-16]. Here we report an improved surface treatment for TaN electrodes. Following a conventional nitrogen plasma treatment, exposing the bottom TaN to an oxygen plasma increased the

nitrogen plasma treatment also improved the leakage current by 2 orders of magnitude.

Such an improvement occurs because the interfacial reaction is reduced during device

processing. This was seen in cross-sectional transmission electron microscopy (TEM).

We measured a leakage current of 4.8×10-6 A/cm2 in our 28 fF/μm2 density TaN/TiHfO/TaN MIM capacitors. This data compares well with other high-κ MIM

capacitors [2-1]-[2-16], even when higher work-function Ir [2-11]-[2-15] or Ni [2-16]

electrodes are used.

2.2 Experimental procedure

The high-κ TiHfO MIM capacitors were fabricated on standard Si wafers. For VLSI backend integration, a 2-μm-thick SiO2 isolation layer was deposited on the Si substrates.

Then a TaN/Ta (50-nm/200-nm) bi-layer was deposited and used as the bottom capacitor electrode. The nitrogen plasma was applied to the TaN surface [2-13]-[2--15]. This was

followed by an O2 plasma treatment to increase the oxidation resistance, before the high-κ dielectric deposition and post-deposition annealing (PDA). A ~12 nm thick

TixHf1-xO (x~0.67) film was deposited by PVD, followed by a 400oC PDA in an oxygen ambient, to reduce the defects and the leakage current [2-3]. Finally, 50 nm layer of TaN was deposited and patterned to form the top electrode. The TiHfO thickness and the

A large capacitor size of 150-μm×150-μm was used to ensure that any dimensional

variations were unimportant. The fabricated MIM devices were characterized by C-V and

J-V measurements.

2.3 Results and discussion

In Figures 2-1 (a) and (b) we show the C-V and J-V characteristics of TiHfO

capacitors with and without the second oxygen plasma treatment. The capacitance density increased from 22 to 28 fF/μm2, as the lower TaN electrode was exposed to the oxygen

plasma for longer times. Correspondingly, the leakage current at -1 V decreased from 2.5×10-4 to 4.8×10-6 A/cm2 with increasing oxygen exposure. Therefore, the increasing

exposure time to oxygen plasma improves both capacitance density and leakage current.

The comparison of our data with those for other MIM capacitors appears in Table 1. The

performance of our TaN/TiHfO/TaN capacitors is comparable with the best reported MIM devices, such as Ir/TiTaO/TaN (23 fF/μm2 density) [2-11]-[2-12] or Ni/STO/TaN (25 fF/μm2 density) capacitors [2-16], which used higher work-function Ir (5.3 eV) and Ni

(5.1 eV) top electrodes than this TaN (~4.6 eV) case. The high work-function electrode is especially important for leakage current at low voltage due to the Schottky emission mechanism [2-17]-[2-18]. Our result indicates the importance of an additional oxygen

We have also measured the variation of the capacitance (ΔC/C) as a function of

voltage. In Fig. 2-2 we show such ΔC/C-V data. The voltage dependence of ΔC/C is expressed as βV+αV2 [2-8]-[2-12], where β and α are the linear and quadratic

coefficients of ΔC/C-V, respectively. Here α is the important factor for capacitors, since the effects of β can be compensated in the circuit design [2-8]. Increasing the exposure time of the bottom TaN to an oxygen plasma decreased α from 17858 to 3851 ppm/V2. Since the α improves rapidly with decreasing capacitance density [2-14], further α

reduction is possible at lower capacitance density used for analog/RF application.

To understand these performance improvements, we examined the devices using cross-sectional TEM. In Figs. 2-3 (a) and (b) we compare the TEM images for the TiHfO structure without and with the oxygen plasma treatment. A clear interfacial region, ~3 nm wide, can be seen in the conventional nitrogen-only plasma-treated TaN, giving a total thickness of ~15 nm. In contrast, the combined oxygen and nitrogen plasma-treated TaN

shows reduced interfacial reactions. A thickness of ~12 nm was measured for the TiHfO dielectric – indicating a κ value of 38, at a capacitance density of 28 fF/μm2.

In the Fig. 2-4 (a) and (b) the surface roughness of the lower TaN with O2 plasma is

analysis in Fig. 2-5 shows that a significant improvement with less Hf diffusion is obtained by using O2 and N2 plasma treatment.

The possible reason for the large improvement, given by the oxygen plasma treatment, may be the larger bond enthalpy of TaO (799 kJ/mol) compared with that of TaN (611 kJ/mol) [2-19]. When applying only a nitrogen plasma treatment, the lower TaN will be oxidized to TaON during unavoidable PDA, due to the thermodynamically favorable larger bond enthalpy – this would lower the capacitance density. The significantly smaller interfacial layer with oxygen plasma treatment may be de to the formation of high quality TaON by highly reactive oxygen plasma, which decreases further oxygen diffusion into underneath TaN to form poor quality thermal TaON at low temperature during PDA.

2.4 Conclusion

We have shown that a nitrogen plasma treatment cannot, alone, suppress the interfacial layer formation that causes degraded capacitance density and leakage current in TaN/TiHfO/TaN MIM capacitors. By using an additional oxygen plasma treatment the

We have shown that a nitrogen plasma treatment cannot, alone, suppress the interfacial layer formation that causes degraded capacitance density and leakage current in TaN/TiHfO/TaN MIM capacitors. By using an additional oxygen plasma treatment the

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