Suggestion on Future Works

In this thesis, we have proposed a digital background calibration scheme for multi-stage ADCs; as a result, an obvious future work is the pipelined ADC implemen-tation with multi-stage calibration using this technique. Using multiple open-loop stages in the converter front-end will result in larger power saving and high conver-sion rate.

Other opportunities exist in exploring more efficient estimation that cancels the input signal interference in the estimation. At the same time, an optimization of this work based on the implementation in each stages could be a future research topic.

A third, more aggressive vision, is to extend the digital correction in ADCs to include dynamic, frequency dependent error. The benefits of fully digital dynamic error compensation could be revolutionary.

More generally, a similar estimation concept to analog distortion could be consid-ered in audio, video, and other communication systems that are limited by nonlinear effects.

Bibliography

[1] Y. Chiu and P. R. Gray, “A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39, pp. 2139–2151, Dec. 2004.

[2] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606, May 1999.

[3] B. Murmann and B. E. Boser, “A 12b 75ms/s pipelined adc using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, pp. 2040–2050, Dec. 2003.

[4] C. Grace, P. Hurst, and S. Lewis, “A 12b 80MS/s pipelined ADC with boot-strapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, pp. 1038–

1046, June 2005.

[5] J. McNeill, kMichael C. W. Coln, and B. J. Larivee, ““split” ADC Architecture for Deterministic Digital Background Calibration of a 16-bit 1-MS/s ADC,”

IEEE J. Solid-State Circuits, vol. 40, pp. 2437–2445, Dec. 2005.

[6] O. E. Erdogan, P. J. Hurst, and S. H. Lewis, “A 12-b 2.5MHz digital-background-calibrated algorithmic ADC with -90-dB THD,” IEEE J. Solid-State Circuits, vol. 34, pp. 1812–1820, Apr. 1999.

[7] J. Li and U.-K. Moon, “Background Calibration Techniques for Multistage Pipelined ADC With Digital Redundancy,” IEEE Transections on Circuits and Systems-II Analog and Digital Signal Processing, vol. 50, pp. 531–538, Sept.

2003.

[8] H. Khorramabadi, EE247 Course Notes. University of California, Berkeley, 2004.

[9] M. J. Story, “Digital to analogue converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling signal,” U.S.

Patent 5 138 317, Aug. 11, 1992.

[10] D. A. Johns and K. Martin, Analog Integrated Circuit Design. Canada: John Wiley and Sons, Inc., 1997.

[11] S. Wong and C. A. T. Salama, “Impact of Scaling on MOS Analog Perfor-mance,” IEEE J. of Solid-State Circuits, vol. SC-18, pp. 106–114, Feb. 1983.

[12] A. M. Abo, Design for reliability of low-voltage, switched-capacitor circuits.

PhD Thesis, University of California, Berkeley, 2004.

[13] T.-H. Tsai, P. J. Hurst, and S. H. Lewis, “Time-Interleaved Analog-to-Digital Converters for Digital Communications,” in Conf. on Circuits, Signals and Systems, Nov. 2004, pp. 193–198.

[14] Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, “Least Mean Square Adap-tive Digital Background Calibration of Pipelined Analog-to-Digital Convert-ers,” IEEE Transection on Circuits and Systems-I:Reqular Papers, vol. 51, pp.

38–46, Jan. 2004.

[15] X. Wang, P. J. Hurst, and S. H. Lewis, “A 12-Bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background Calibration,”

IEEE J. Solid-State Circuits, vol. 39, pp. 1799–1808, Nov. 2004.

[16] H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration,” IEEE J. Solid-State Circuits, vol. 40, pp. 1047–1056, May 2005.

[17] J. P. Keane, P. J. Hurst, and S. H. Lewis, “Background interstage gain cal-ibration techniques for pipelined ADCs,” IEEE Transections on Circuits and Systems-I, vol. 52, pp. 32–43, Feb. 2005.

[18] A. N. Karanicoas, H.-S. Lee, and K. L. Bacrania, “A 15-b 1-MSample/s digitally self-calbrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1207–

1215, Dec. 1993.

[19] SIMULINK and MATLAB, User’s Guides. MA: The MathWorks, Inc., 1997.

[20] S. H. Lewis, “Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital converters for Video-Rate Applications,” IEEE Transections on Cir-cuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 516–523, Aug. 1992.

[21] S. H. Lewis and P. R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 22, pp. 954–961, Dec. 1987.

[22] B.-S. Song, S.-H. Lee, and M. F. Tompset, “A 10-b 12-MHz CMOS Recycling Two-Step A/D Converter,” IEEE J. Solid-State Circuits, vol. 25, pp. 1328–

1338, Dec. 1990.

[23] L. Singer and T. Brooks, “A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter,” in Dig. Symp. VLSI Circuits, Dec. 1996, pp. 94–95.

[24] S. H. Lewis, H. S. Fetterman, G. F. Gross, R. Ramachandran, and T. R.

Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J.

Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992.

[25] M. Gustavsson, J. J. Wikner, and N. N. Tan, CMOS DATA CONVERTERS FOR COMMUNICATIONS. Boston: Kluwer Academic Publishers, 2000.

[26] Y.-T. Wang and B. Razavi, “An 8-Bit 150-MHz CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol. 35, pp. 308–317, Mar. 2000.

[27] W. Yang, I. M. K. Kelly, M. T. Sayuk, and L. Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85dB SFDR at Nyquist input,” IEEE J.

Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.

[28] L. Singer, S. Ho, M. Timko, and D. Kelly, “A 12-b 65-Msample/s CMOS ADC with 82dB SFDR at 120 MHz,” in ISSCC Dig. Tech. Papers, Feb. 2000, pp.

38–39.

[29] Y. M. Lin, B. Kim, and P. Gray, “A 13-b 2.5MHz self-calibrated pipelined A/D converter in 3-um CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991.

[30] S. H. Lee and B. S. Song, “Digital-domain calibration of multistep analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 27, pp. 1679–1688, Dec.

1992.

[31] S. U. Kwak, B. S. Song, and K. Bacrania, “A 15-b, 5-Msample/s low-spurious CMOS ADC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1866–1875, Dec. 1997.

[32] I. Galton, “Digital cancellation of D/A converter noise in pipelined A/D con-verters,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 36, pp. 185–196, Mar. 2000.

[33] K. Nair and R. Harjani, “A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipelined A/D converter,” in ISSCC Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 456–457.

[34] E. Siragusa and I. Galton, “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC,” IEEE J. of Solid-State Circuits, vol. 39, pp. 2126–2138, Dec. 2004.

[35] E. J. Siragusa and I. Galton, “Gain error correction technique for pipelined analogue-to-digital converters,” Electron. Lett., vol. 36, pp. 617–618, Mar. 2000.

[36] ITRS, International Roadmanp for Semiconductors. available in http://public.itrs.net, 2004.

[37] E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully dig-ital correction of monolithic pipelined ADCs,” IEEE Transections on Circuits and Systems-II, pp. 143–153, Mar. 1995.

[38] J. Tsimninos, Identification and Compensation of Nonlinear Distortion. Uni-versity of South Australia: PhD Thesis, 1995.

[39] B. Murmann and B. E. Boser, Digitally Assisted Pipeline ADCs. Boston:

Kluwer Academic Publishers, 2004.

[40] E. B. Blecker, T. M. McDonald, O. E. Erdogan, P. J. Hurst, and S. H. Lewis,

“Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue,” IEEE J. Solid-State Circuits, vol. 38, pp. 1812–1820, June 2003.

[41] M. K. Mayes and S. W. Chin, “A 200mW, 1 Msample/s 16-b pipelined A/D con-verter with on-chip 32-b microcontroller,” IEEE J. Solid-State Circuits, vol. 31, pp. 1862–1872, Dec. 1996.

[42] I. E. Opris, L. D. Lewicki, and B. C. Wong, “A single-ended 12-bit 20Msample/s self-calibrating pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 33, pp. 1898–1903, Dec. 1998.

[43] S.-Y. S. Chuang and T. L. Sculley, “A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 37, pp.

674–683, June 2002.

[44] J. Ming and S. H. Lewis, “An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration,” IEEE J. Solid-State Circuits, vol. 36, pp. 1489–1497, Oct. 2001.

[45] R. G. Massolini, G. Cesura, and R. Castello, “A Fully Digital Fast Convergence Algorithm for Nonlinearity Correlation in Multistage ADC,” IEEE Transection on Circuits and Systems-II, vol. 53, pp. 389–393, May 2006.

[46] B. Widrow and S. D. Stearns, Adaptive Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1985.

[47] C. J. Stone, A Course in Probability and Statistics. USA: Duxbury, 1991.

[48] J. Walrand, Course Notes. University of California, Berkeley, 2004.

[49] R. T. Baird and T. S. Frez, “Improved delta-sigma DAC linearity using data weighted averaging,” in Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, May 1995, pp. 13–16.

[50] I. Fujumori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, C. Jun, and S. L.

Chan, “A 90-dB SNR 2.5 MHz output-rate ADC using cascaded multibit delta-sigma modulator at 8x oversampling ratio,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1820–1828, Dec. 2000.

[51] F. Chan and B. H. Leung, “A high resolution multibit sigma-delta modulator

[52] R. Schreier and B. Zhang, “Noise-shaped multibit D/A converter employing unit elements,” Electron. Lett., vol. 28, pp. 1712–1713, Sept. 1995.

[53] I. Galton, “Spectral shaping of circuit errors in digital-to-analog converters,”

IEEE Trans. Circuits Syst. II, vol. 31, pp. 808–817, Oct. 1997.