一個適用於多級類比數位轉換器的嶄新數位背景修正方法

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國

立交通大學

電

機與控制工程研究所

碩

士論文

一個適用於多級類比數位轉換器的

嶄新數位背景校正方法

A Novel Digital Background Calibration

Scheme for Multistage ADCs

研究生：吳孟軒

指導教授：洪浩喬教授

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一個適用於類比數位換轉換器的嶄新數位背景修正方

法

A Novel Digital Background Calibration Scheme

for Multistage ADCs

研究生：吳孟軒

Student : Meng-Shuan Wu

指導教授：洪浩喬教授

Advisor : Hao-Chiao Hong

國立交通大學

電機與控制工程研究所

碩士論文

A Thesis

Submitted to Department of Computer and Information Science College of Electrical Engineering and Computer Science

National Chiao Tung University In partial Fulfillment of the Requirements

for the Degree of Master

in

Electrical and Control Engineering July 2006

Hsinchu, Taiwan, Republic of China

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誌謝

在這兩年的研究生生涯中，我學到了很多。我一直覺得我是一個很幸運的人，在每一個階段的學習過程，我都遇到了對我幫助很多的好老師。一樣的，在就讀研究所的階段裡，我依然遇到了一個對我幫助很多，甚至更多的好老師。我要感謝我的指導教授，洪浩喬教授。在每一次我們討論到對於新的方法裡的問題時，他都能以他豐富的經驗與學識提供我一個可行的方向。除了研究的本身，老師也教導了我許多研究所應該要有的態度，這對我幫助很大。並且，老師也常以他的經驗，指導我做人處事的方向。不啻是學術或是人生旅程上，我真的很慶幸能遇到洪老師。我要感謝林清安教授。由於林教授對於adaptive system的了解，使我得以推導出這本論文中的LMS loop 的式子。也感謝林教授肯花時間與我討論我的研究，縱使我不是他的指導學生，謝謝。我要感謝我的實驗室同學：國銘(Kevin)，鼎鈞(Danny)，宏慶(Cris)。我們在碩一時一起度過了許多快樂時光。比如一起出去遊玩，吃飯，或是大家在為了期末專題，一起熬夜寫作業的過程，這些都令人回味再三。我要感謝學弟振綱(Vincent)，榮州 (Allen)，芳毅(Frank)，謝謝你們在我為了我的模擬時所提供的幫助，以及感謝你們的“幫忙” 訂便當 ^^。最後，也是最重要。我要感謝我的家人。感謝他們每一次都相信我，當我說“我想出了一個新方法，可以畢業了”。而事實是，每次當我隔天在學校驗證時，我想的方法卻都失敗。雖然每一次的畢業宣言都失敗 (除了最近這一次) ，但是我的家人始終相信我，這給了我很大的力量去繼續我的研究，謝謝他們。

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一個適用於類比數位轉換器的嶄新數位背景校正方法

學生：吳孟軒

指導教授：洪浩喬博士

國立交通大學

電機與控制工程研究所碩士班

摘要

當 CMOS 的製程朝向尺寸越來越小演進時，由於低電壓以及低基本增益的關係，設計類比電路如管線式類比數位轉換器中的殘餘量放大器是一項相當具有挑戰性的工作。信號不再線性的被放大而開始有了失真。因而在本篇論文裡，我們提出了一個嶄新的數位背景校正方法，可以精準的量測與修正殘餘量放大器中的線性與非線性增益誤差。我們所提出的方法 multi-correlation estimation (MCE) technique，利用加入不同振幅的隨機序列，而得以得知有關於誤差的訊息。除此之外，利用此種方法的數位校正電路可以被大幅的簡化。此外，本篇論文探討了類比數位轉換器被校正過後的精準度與其在校正電路裡校正參數之間的關係，同時建立了一個對於電路實現的設計流程。應用所提出的方法，模擬結果展示出一個 12-bit 200MSample/s 管線式類比數位轉換器在校正之前 ENOB=6，SNDR=38dB，DNL=2.6/-0.7 LSB，INL=27/-27，校正後的ENOB=11.7，SNDR=72.3，DNL=0.43/-1，INL=0.66/-0.6。從以上結果可以驗證我們所提出的方法是可行的。

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A Novel Digital Background Calibration

Scheme for Multistage ADCs

Student: Meng-Shuan Wu Advisor: Professor Hao-Chiao Hong

Department of Electrical and Control Engineering National Chiao Tung University

Hsin-Chu, Taiwan, R.O.C.

Abstract

As the trend for the CMOS process scaling continues advancing, the design of analog circuits such as the residue amplifier in the pipelined ADCs has become a much challenging work due to the lowed intrinsic gain and the voltage swing. The signal amplification by the residue amplifier is no longer linear but has distortions. This thesis presents a novel digital background calibration that accurately estimate and correct the linear and the nonlinear gain errors arising from the residue amplifier. The proposed estimation technique, called the multi-correlation estimation (MCE) technique, estimates residue gain errors by injecting random sequence alternatively, allowing extractions of linear and nonlinear gain errors orthogonally. In addition, the circuits enabling background estimation is largely simplified.

This thesis also discusses the relationship between the recovered ADC resolution and the correction parameters associated with the calibration function. Therefore, a design strategy related to the practical implementation as well as the design con-sideration is built in this thesis.

Employing the proposed scheme, the simulation result shows that a 12-bit 200 MSample/s pipelined ADC before calibration only has an effective number of bit (ENOB) of 6 bits, an SNDR of 38.4 dB, a DNL of 2.55/ − 0.75 LSB, and an INL of 27/ − 27 LSB. After calibration, its ENOB and SNDR are improved to be 11.7 bits and 72.3 dB respectively, and its DNL and INL are 0.43/ − 1 and 0.66/-0.6 LSB respectively. These results verify the proposed technique does work well.

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List of Figures

2.1 Example of the multi-step amplitude quantization. . . 5

2.2 Pipelilned ADC diagram [1]. . . 6

2.3 Residue plot with sub-ADC offsets. . . 7

2.4 Residue plot using extra comparators in next stage. . . 8

2.5 Residue plot with reduced half gain. . . 9

2.6 Switched-capacitor implementation of a 1.5bit pipline stage [2]. . . 9

2.7 Digital output with bit-shifting . . . 10

3.1 Single-bit architecture: (a) sampling phase (b) amplification phase. . 12

3.2 Transfer function of single-bit architecture. . . 13

3.3 MDAC with practical loading during amplification phase. . . 15

3.4 Output voltage with slewing during amplification phase. . . 17

3.5 ADC with open-loop architecture [3]. . . 18

4.1 Queue-based calibration [4]. . . 21

4.2 “Split ADC” architecture [5]. . . 22

4.3 Queue-based calibration [6]. . . 23

4.4 Timing scheme [6]. . . 23

4.5 Correlation based estimation [7]. . . 24

5.1 Pipelined ADC stage macro model [8]. . . 26

5.2 Precision requirements . . . 27

5.3 ADC block diagram . . . 27

5.4 Complete digital correction [3]. . . 31

6.1 Transition height of digitized residue. . . 33

6.2 Error correction of pipelined ADC [1]. . . 33

6.3 “Split” ADC architecture [5]. . . 34

6.4 Two channel ADC architecture [7]. . . 35

6.5 Residue plot when adding RNGs. . . 36

6.6 Reduced model with proposed calibration scheme. . . 37

6.7 Adaptive system performing system identification. . . 39

6.8 Recursive iteration using LMS. . . 40

7.1 Modified capacitor array. . . 42

7.2 Block diagram of the background calibration scheme. . . 43

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7.4 Sensitivity of σp3. . . 49

7.5 SNDR versus mismatch. . . 51

7.6 Modified capacitor using DWA [9]. . . 52

8.1 DNL without correction. . . 54

8.2 INL without correction. . . 55

8.3 DNL with perfect adjust p1,p3 . . . 56

8.4 INL with perfect adjust p1,p3 . . . 57

8.5 FFT without correction. . . 58 8.6 FFT with correction. . . 59 8.7 p1 convergence. . . 61 8.8 p3 convergence. . . 62 8.9 ENOB convergence. . . 63 8.10 ENOB distribution. . . 64

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List of Tables

8.1 Open-looop amplifier parameters. . . 53

8.2 LMS Loop Parameters. . . 60

8.3 ADC Performance. . . 60

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Chapter 1 INTRODUCTION

1.1 Motivation

As the fabrication technology continues to scale down, digital circuits have much superiority over analog ones. Digital circuits benefit from the scaled CMOS technol-ogy, making them smaller, consuming less power, and capable of operating at high speed. That is, more digital signal processing (DSP) capability is available for the same area at a reduced power consumption. On the other hand, the analog circuits suffer from reduced voltage headroom and intrinsic gain of the scaled devices. Both add design challenges in high-gain feedback loops [10–12]. Meanwhile, the reduced supply voltage limits the usage of traditional gain-enhancement design techniques such as cascode and gain-boosting. It also lowers the ratio of useful signal range, leading to increased power dissipation in the noise-limited circuits to keep the same Signal-to-Noise Ration (SNR).

In modern SoC (System-on-Chip) devices, the analog-to-digital converter (ADC) is a fundamental building block for connecting the real world to the digital proces-sors. The demands for high performance ADCs with high resolution, high speed, and low power keep increasing in various applications such as audio, portable, and telecommunication. High performance ADCs, however, are usually power inefficient and difficult to design using the advanced process. Based on above observations, a new design scenario, digital-assist analog design, is getting more and more pop-ular [3] and digital processing of analog signals has become more attractive [13] in communication systems. Circuit designers now tend to use fast-but-imprecise ana-log functional blocks, while employing DSP to compensate for the errors due anaana-log circuits. Such ADCs composed of digital calibration circuits therefore have the abil-ity to facilitate compensation in digital domain to sustain their performance even under the scaled technology.

1.2 Overview

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pro-limitations, recovering the degraded ADC accuracy.

The multistage ADC, e.g., the pipelined ADC, has been the most popular ADC architecture because of its versatility. Typical applications include audio, video, ultrasound, base station, and telecommunications. Flexible and suitable for a wide range of specification, the pipelined ADC has the potential of achieving high reso-lution, high speed, and low power. Because of its advantages, the pipelined ADC is used to demonstrate and validate the effectiveness of our scheme described in this thesis.

Among the key building blocks in the pipelined ADC are the residue amplifiers in each stages. In general, we require the residue amplifier providing precise am-plification and operating at high speed. Hence, both features need high open-loop gain and large unity-gain bandwidth at the same time. However, large open-loop gain is difficult to realize without sacrificing bandwidth especially using closed-loop topology. With the closed-loop topology, although robust and highly linear, design-ers inevitably have to make tradeoff between the precision, speed, and power in an ADC design, making a constraint loop.

To break the constraint loop, numerous researches have been proposed to tackle the technology limitation. The main concept of these algorithms lie in using analog or digital circuits for the calibration of the non-ideal analog functions. Those works can be classified into two scenarios:

• Area Redundancy • Time Redundancy

The area-redundancy scheme uses an additional slow-but-accurate reference ADC to calibrate the main ADC by comparing the digital raw codes of the main ADC to those of the reference one [14, 15]. This reference ADC may be a Σ∆ ADC or a cyclic ADC. The added ADC just for calibration may consume significant area and power; besides, designing such highly linear ADCs is a challenging task especially under reduced supply voltage.

On the contrary, the time-redundancy scheme takes the ADC digital output codes for calibration rather than the comparison results, leading to less hardware overhead and being easy to implement [3, 7, 16]. Such methodology may employ complex digital circuits (to carry out statistical functions) instead of analog ones; therefore, it is more robust and adaptable to the continuing scaled process. The statistical algorithm enables the ADC itself to estimate the analog errors of the residue amplifier so as to digitally compensate them.

Among previous works, two researches that can calibrate linear and nonlinear gain errors of residue amplifiers have been proposed [3,17]. They have the advantages of performing calibration in digital domain and working in background. However, the calibration algorithm in [3] has large dependence on input signal statistics owing to the way that it estimates the analog errors. Some specified residue values must be toggled such that the information of errors can be obtained. This condition is hard to fulfill since information itself cannot be predicted or assumed having specific distribution. Moreover, redundant stages are required to precisely estimate

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the error of analog components. In [17], it is only suitable for weakly nonlinear amplifiers due to its calibration mechanism and not easy-to-implement because of using very complex digital calibration circuits.

Faced with these issues and driven by the trends using calibration to improve ADC accuracy while maintaining high speed, this thesis proposes an alternative scheme. The scheme relaxes the design challenges on precise analog circuits by us-ing open-loop amplifiers exhibitus-ing high speed, low power, and low noise that then can be corrected in digital domain. Assisted by the digital circuits, the proposed scheme can adaptively calibrate the linear and nonlinear gain errors introduced by the residue amplifiers while performed in background without interrupting the nor-mal conversion. In particular, incorporated with statistical functions, it is featured in that the quantization noise of backend ADC does not affect the system identi-fication process as compared with [3, 18]. Therefore, the linearization parameters for the calibration of the ADC can be obtained through an unaffected identification process. In addition, calibrations of multistage ADCs using conventional precision feedback amplifiers is available owing to the characteristics described in the scheme. A 12-bit 200 MSample/s pipelined ADC with open-loop amplifiers design exam-ple using MATLAB [19] is used to demonstrate the effectiveness of the proposed scheme. The simulation results show that before calibration, the pipelined ADC only has an effective number of bit (ENOB) of 6 bits, an SNDR of 38.4 dB, a DNL of 2.55/-0.75 LSB, and an INL of 26.5/ − 26.4 LSB. After calibration, its ENOB, SNDR, DNL, and INL are improved to be 11.7 bits, 72.3 dB, 0.43/-1 LSB, and 0.66/-0.6 LSB respectively.

1.3 Chapter Organization

This thesis is divided into nine chapters. Chapter 2 reviews the fundamentals of pipelined ADC.

Chapter 3 discusses the error sources relating to pipelined ADCs and the error models for further analysis.

Chapter 4 reviews previously proposed calibration techniques while giving anal-ysis on their applications and limitations in depth.

Chapter 5 describes a digital correction mechanism that assists the proposed estimation technique described in chapter 6 and 7.

Chapter 6 and 7 aim at giving comprehension of the proposed digital background calibration scheme with its implementations and design considerations.

Chapter 8 gives the simulation results that validate the proposed concepts. From the simulation results, we have shown a great improvement on the ADC performance: a nearly ideal digital output is possible even extremely nonlinear stages are used in the front-end stages.

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Chapter 2 PIPELINED ADC OVERVIEW

Resolving engineering issues needs a thorough understanding to the question itself, which helps the engineers find more elegant solutions to the problem and save the design period. This chapter introduces the basis of the pipelined ADC and aims at giving a straightforward insight into the ADC architecture, prepared for the topics in depth of the following chapters. Sec. 2.1 introduces the basic principles of the operation and the structure. Sec. 2.2 describes a technique, digital error correction, that is commonly used in pipelined ADCs to relax the requirement on accurate comparators in the sub-ADC.

2.1 Fundamentals of Pipelined ADC

A pipelined ADC is featured in performing a multi-step amplitude quantization as indicated by Fig. 2.1. Shown in Fig. 2.2 is a pipelined ADC with its conventional transfer function in the stage 2, where V2 is a function of stage’s input voltage V1.

In this stage, it resolves two bits at a time and therefore has four segments in its transfer function. A general pipelined ADC cascades plural similar stages in which each stage resolves a few bits at a time. Within each stage, the analog input signal is first sampled and held. Then, a sub-ADC resolves the held analog signal into a coarse n-bit output. After that, a sub-DAC converts the coarse digital output back to an analog level that is being subtracted from the original input signal, yielding the quantization error. This quantization error is then restored to the original full-scale range by the residue amplifier. As a result, the locally amplified quantization, usually called residue, is further quantized by the remanding stages to resolve each n-bit respectively. Finally, the digital output is obtained by the recombination of digital raw codes of each stages. Hence, the digital output is expressed as

Dout= D1+ D2 G1 + D3 G1G2 + . . . + DN G1. . . GN −1 , (2.1)

where Di and Gi are the digital raw codes and the gain of the residue amplifier

within each stage, respectively, and N is the ADC resolution. Accordingly, higher resolution can be achieved by cascading more stages with the penalty of about linearly growing area. The number of bits that each stage can resolve depends on the

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First Stage

Second Stage

Amplification by 2

2

MSBs

LSBs

11

10

00

01

11

10

00

01

11 V

in

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εa

Stage 1

Stage 2

Stage N

Vin V1 V2 V1 _G V2 a Sub-ADC Sub-DAC V2 V1 n1bits n2bits n2bits nNbits e.g. n2= 2

Figure 2.2: Pipelilned ADC diagram [1].

applications. For instance, with conventional architecture, high speed specification favors the architecture with a low number of bits per stage because the interstage gain is lowered, allowing high speed operation due to the fundamental unity-gain bandwidth trade-off of the residue amplifier. On the contrary, low speed, high resolution tends to favor higher number of bits per stage. A detailed analysis can be found in [20].

The concept of the pipeline architecture comes from the digital signal processing. This configuration trades the process latency with the throughput with the aid of inherent sample-and-hold function [21]. Also, since each stage resolves a few bits at a time, this approach increases the throughput and reduces the number of the comparators compared to the flash architecture.

Several attributes of the pipelined ADC architecture can be observed from the introduction above. First, the circuit complexity increases about linearly when each additional bit is added. Because of the involvement of the binary search algorithm, the number of comparators roughly grows linearly, while that of the flash ADC grows exponentially. Second, the ADC throughput is as fast as the flash ADC but the pipelined ADC consumes less power provided their resolutions are greater than 6 bits. Finally, the pipelined ADC has a wide range of specifications since the functional blocks within the stage can be implemented with a variety of topologies. Hence, the ADC fulfills the demands on various applications such as radio, video, instrumentation, imaging, and communication systems.

Within the pipelined stages, the presence of the residue amplifier largely relaxes the accuracy requirements of the comparators. That is, the ADC needs no accurate comparators with very small threshold levels as compared with the two-step ADC.

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However, since the opamps have to perform precise amplifications, they usually dominate the power dissipation and limit the maximum speed of the ADC in stead of the comparators. This phenomenon has become an emerging issue especially in advanced process on account for the reduced intrinsic gain and supply voltage.

Although a precise comparator with very small threshold levels is not necessarily required, the inherent offset issue is not resolved. To suppress the effect of offsets, a technique in digital domain, called digital error correction (DEC) [21] technique, is commonly used in almost every pipelined ADC. It largely alleviates the ADC sensitivity to the offsets in the sub-ADC, making the high-speed but low accuracy comparators available in the sub-ADC design. The concept of digital error correction will be described in Sec. 2.2

2.2 Digital Error Correction

V

in

V

_res

ε

b

V

_{re f}

−V

re f

V

re f

−V

re f

Figure 2.3: Residue plot with sub-ADC offsets.

The digital error correction scheme can tolerate the presence of nonidealities in pipelined ADCs. These nonidealities consists of the offsets of the comparators and opamps, capacitors mismatch, finite opamp gains, and charge injections. They may induce deviations of the transfer curve (dashed line) from the idea one (solid line) as indicated by Fig. 2.3. Thus, the residue may saturate the following stages resulting in missing levels thereby introducing distortion in the spectrum due to the deviation. With the cascaded topology, the errors that saturate next stage’s input range can be seen as offsets of the sub-ADC in the next stage. Under this condition, several techniques have been proposed to ease such problem of saturation

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by employing digital error corrections. Usual implementations of digital correction schemes include:

• over-range detection, [21]

• reducing residue amplification gain by half. [21–23]

An over-range detection topology detects out-of-range residue signals in the next stage and converts them back to correction bits, which are then added/substracted to the coarse digital output of the previous stage. To make detection, a common approach is to use two extra capacitors in the MDAC or two extra comparators in the sub-ADC of next stage. Fig. 2.4 illustrates this idea.

LSB (of local Sub-ADC)

1/2

-1/2

V

res

V

_{re f}

−V

re f

V

in

Normal Input Range

Figure 2.4: Residue plot using extra comparators in next stage.

Compared with the over-range detection scheme, another technique reduces the local stage’s gain by half, thereby lowering the next stage’s input range. This scheme is commonly used in practical designs. As a result of the lowed output range, large comparator offsets in the local stage can be tolerant as far as they are less than ±1/2LSB of local sub-ADC’s threshold levels. As a result, when the next stage’s input falls in the upper/lower half input full-range of next stage, digital error correction is performed by adding/subtracting extra bit to the raw codes of the previous stage. This ideal is shown in Fig. 2.5.

However, both topologies require some encoding logics to recalculate the true digital output. The encoding logic would be greatly simplified if some offsets are added to the transition thresholds of the sub-ADC or sub-DAC. An example of a popular 1.5bit/stage architecture as indicated in Fig. 2.6 demonstrates this concept [2, 24]. Although a single-ended architecture is represented here for simplicity, a

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Vin

Vres 1/2Vre f

−1/2Vre f

εb

Figure 2.5: Residue plot with reduced half gain.

Vre f 4 −Vre f 4 Vre f 4 −Vre f 4 Vi Cf Cs S1 S2 S3 Vo MUX LA TCH 0

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fully differential topology is adopted in many practical designs. In Fig. 2.6, only 2 comparators are needed to resolve 3 levels for a 2bit sub-ADC, while 3 comparators are required for a nominal 2-bit sub-ADC. Thus, the architecture tolerates sub-ADC offsets up to ±1/2LSB in the local stage. As a result, the requirements on precise comparator are greately relaxed. With this concept, the digital output is obtained by shifting bits of each stages and then added together as shown in Fig. 2.7.

Stage 1

Stage 2

Stage 3

Stage 4

Stage 5

010

111 01010101111

MSB

LSB

Digital Output

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Chapter 3 ANALOG ERROR MODELS

This chapter describes the common error sources affecting the performance of the pipelined ADCs and tries to build adequate mathematical models for prior design considerations. First, the error sources commonly encountered in conventional archi-tecture are addressed in Sec. 3.1, 3.2, 3.3, including errors arising from the capacitors mismatch, the residue amplifier.

Then, an alternative residue amplifier approach, i.e., the open-loop residue am-plifier topology, is discussed in Sec. 3.4 and demonstrated as a calibrating machine in the proposed calibration scheme in Chapter 6 and 7.

3.1 Introduction

Shown in the Fig. 3.1 is a conventional demonstration-by-concept single-bit/stage architecture intended to be used over Sec. 3.1-3.3 in this chapter. This architecture uses switched-capacitor technique that can be switched between the input, the ref-erence voltages, and ground, realizing the sample-and-hold, DAC, and subtraction functions. It performs two phase operations as following. During the first phase, usually called the sampling phase, the input is connected to the bottom plates of the capacitors while the top plates connected to virtual ground. The charges Q = (Cs+ Cf)Vin are then stored onto the capacitors. In the second phase, the

am-plification phase, the bottom plate of Cf is connected to the output of the residue

amplifier and that of Cs is connected to positive Vref or negative Vref depending on

D = 1 or D = −1, where D is the local conversion result of the sub-ADC. As a re-sult, total charges of Q = CfVres+ CsDVref are stored during that phase. By charge

conservation with Cf = Cs, the ideal residue transfer function in the amplification

phase is given by Vres = ( (1 + Cs Cf)Vin− Cs CfVref = 2Vin− Vref if Vin ≥ 0 D = 1 (1)2 (1 + Cs Cf)Vin+ Cs CfVref = 2Vin+ Vref if Vin < 0 D = −1 (0)2,

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V

out

V

in

C

f

C

_s

V

out

C

f

C

s

DV

re f

(a)

(b)

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V

re f

−V

re f

V

res

V

in

V

re f

−V

re f

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3.2 Capacitors Mismatch

Consider the capacitors mismatch only, if Cs 6= Cf, an error proportional to the

mismatch is generated at the residue output. Defining the difference between the capacitors is ∆C, we have ∆C = Cs− Cf (3.1) and C = Cs+ Cf 2 , (3.2) Therefore, Cs = C + ∆C 2 , (3.3) Cf = C − ∆C 2 , (3.4) and Cs Cf = C + ∆C 2 C −∆C₂ ≈ 1 + ∆C C , (3.5)

if | ∆C/C | 1. From (3.5), the transfer function considering the mismatch now becomes Vres ≈ (2 + ∆C C )Vin± (1 + ∆C C )Vref. (3.6)

From (3.6), it is evident the capacitors mismatch result in linear gain error and wrong subtraction of the reference voltages. Both errors are proportional to the difference ∆C provided in the absence of no other circuit imperfections.

Due to the limited fine-line process, the phenomenon of capacitors mismatch mainly stem from variations at the edges of the capacitor plates. Under the sta-tistical manner, capacitors with larger area to perimeter ratios tend to have better matching. However, variations in the oxide thickness between the capacitor plates also affect the matching. This variation is small especially for small, adjacent capac-itors. If we only consider the variations of capacitor edges, the standard deviation of the fractional matching error between two adjacent square capacitors can be models as:

σ∆C/C =

AC

S , (3.7)

where S is one side of the capacitor in µm. The value of AC is technology dependent,

but can typically vary between 2 − 5%µm. For instance, if AC is 5%µm, then

two adjacent, 15µm×15µm capacitors will match to better than 1% with 99.7% probability [2].

3.3 Impairment of Residue Amplifier

Ideally, the residue amplifier produces an output proportional to the input. In prac-tical implementations, the finite open-loop gain and limited unity-gain bandwidth (GBW) make the amplification non-precise or nonlinear. Hence, the finite open-loop

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gain and GBW give rise to static and dynamic errors, limiting the ADC achievable resolution and speed as a consequence.

3.3.1 Opamp’s Open-Loop Gain

A gain error occurs at the residue signal when the open-loop gain is finite. Assume the actual opamp open-loop gain is A0, we can derive the transfer function with

regard to A0:

Vres= (

1 1 + βA0

)(2Vin± Vref), (3.8)

where β is the return ratio of the feedback network. Of the feedback network in Fig. 3.1 during the amplification phase, β can be expressed as

β = Cf

Cs+ Cf + Cp

,

where Cp is the parasitic capacitance at the inputs of the opamp.

Taking the first-order Taylor expansion of (3.8), we have the approximation of the transfer function:

Vres ≈ (1 −

1 βA0

)(2Vin± Vref). (3.9)

Observed in (3.9), the relative error 1/βA0 results in a static error if the residue

is fully settled, therefore limiting the ADC resolution. Since β is well-controlled by the capacitor ratios that can achieve about 10-bit in modern technology, high resolution ADCs above 10-bit often require high open-loop gain.

3.3.2 Opamp’s Settling

V

out

C

f

C

s

DV

re f

C

p

C

_L

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Because the opamp has finite bandwidth, the output takes time to settle to its final value. As a result, the opamp determines the ADC’s speed in most cases. Consider Fig. 3.3, the GBW can be derived as

GBW = gm

2π[CL+

Cf(Cs+Cp)

Cs+Cf+Cp]

.

Hence, the bandwidth (BW) related to the unity-gain bandwidth is obtained by BW = β × GBW = gm 2πCef f , where Cef f = CL+ Cs+ Cp+ CL(Cs+ Cp) Cf .

Assume the opamp is a single-pole system with time constant τ , the settling behavior at the end of the amplification phase is given by

Vres = (1 − exp−t/τ)(2Vin± Vref), (3.10)

where | exp−t/τ | is the relative gain error and τ = 1/(2πβGBW ).

To make the residue error of the first stage’s amplifier tolerable in the following stages, i.e. this error is less than 1/2LSB of the backend ADC, the GBW of the opamp must satisfy the criteria such that

GBW > (N − N1) ln(2)

2πβ(T /2) , (3.11)

where N and N1are the resolution of ADC and the first stage accordingly. Therefore,

it can be seen GBW will almost increase 2× when each additional bit is added in the first stage. Note that above equations validate when the opamp does not slew.

However, some circuit configurations can hardly meet the condition in (3.11), e.g., the pipelined ADCs with low gain stages [25]. Furthermore, in many appli-cations, slewing is often inevitable under the speed and power constraints. As a consequence, the residue error if slewing occurred now becomes

Verror = Vref − Vres(T /2) = (Vref − ∆VSR) exp

−T /2−TSR

τ . (3.12)

Given the bias current IBias of the opamp, we have

∆VSR = IBias CL+ Cf(Cs+Cp) Cs+Cf+Cp TSR.

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t

T/2

V

out

V

re f

∆V

SR

T

_SR

V

_error

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3.4 Open-Loop Amplifier

3.4.1 Introduction

The function of the opamp in the closed-loop is to provide an output signal pro-portional to the input. Because feedback topology desensitizes the environment variation, a precise residue amplification is available and the close-loop implemen-tation has been a standard in lots of ADCs. However, an amplifier using open-loop architecture can provide gain in an equivalent manner. Recently, certain ADCs with open-loop structure have shown the availability and capability to achieve both power efficiency and high resolution [3, 26]. Fig. 3.5 shows a conceptual diagram of this kind of topology.

Sub-ADC

Switches

±Vre f

C

s

[1:N]

V

in

V

res

G

m

D

V

x

Figure 3.5: ADC with open-loop architecture [3].

The operation of this circuit is similar to the conventional topology except the amplification phase. The charges onto the feedback capacitor are not fed to the output of the residue amplifier, but remained in place to generate a voltage, Vx, at

the input of the amplifier. Vx is then amplified to the desired level to be the input of

the next stage. With this topology, the demand for high open-loop gain is no longer necessary and the power dissipation drops as well. As a consequence, the ampli-fication function is available using a simple differential pair. These advantageous, however, come at the price of nonlinearities in the signal amplification.

3.4.2 Behavioral Model of the Open-Loop Amplifier

While using open-loop residue amplifiers in pipelined ADCs, the absence of feedback no longer assists desensitizing the environment variations; that is, a linear model is insufficient to describe the amplifier behavior because of increased nonlinearity and

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input-dependent amplification. Therefore, a simple but sufficient accurate model is required for prior design considerations.

The nonlinear behavior can be divided into two categories: static and dynamic. Dynamic frequency-dependent distortion, however, becomes significant and domi-nant when the operating frequency near the domidomi-nant pole of the system. Because of a simple differential pair being used as an open-loop amplifier, the assumption of a fully settled system is reasonable for its inherent potential operating at high speed. Thus, the complexity of modeling an open-loop amplifier is quite reduced. Meanwhile, since high performance ADCs often adopt fully differential architecture, this configuration advantages less significant even harmonics. High order harmonics such as fifth or above is negligible with appropriate choice of the overdrive voltage of the input pair of the amplifier according to [3]. If above conditions are satisfied, a simple polynomial model is sufficient to describe the fully differential residue am-plifier implementation. As a result, the behavior of the amam-plifier can be described by a third order polynomial

y = a1x + a3x3. (3.13)

This model is then used in our simulation to validate the effectiveness of our cali-bration scheme.

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Chapter 4 ADC CALIBRATION

TECHIQUES

Limited by the process and noise consideration, the resolution of pipelined ADCs without calibration usually may achieve no more than 10 bits. With optimized design and careful layout, some state-of-the-arts ADCs are capable of reaching res-olution of 12 bits [27, 28] or above without trimming or calibration. However, to achieve the same performance like these state-of-art ADCs is often paid with large design efforts and periods due to the supply voltage and intrinsic gain constraints as well as the process variations. Therefore, designing high resolution ADCs has become a much challenging work among circuit designers. As a result, many tech-niques that can calibrate nonlinear errors arising from the inaccurate blocks in the ADC have been proposed in literature [6,18,29–31]. Hence, this chapter gives a brief review of the ADC calibration techniques and relative subjects.

4.1 Introduction

For the past decade, many researches have been proposed to improve the ADC performance and focusing on being compatible with CMOS technology, therefore relaxing the stringent demands on highly linear analog components. Multistage ADCs, e.g. the pipelined ADCs, are well suited for such trends. In the error correction techniques, digital error correction and the use of residue amplifier greatly relax the design of accurate comparators in the sub-ADC and the following stages. However, the ADC linearity is still sensitive to the error arising from the sub-DACs as well as the static and/or dynamic performance of the residue amplifier such as finite dc gain, slew rate, finite GBW, and so on. Hence, a calibration mechanism that is capable of correcting errors arising from the non-perfect MDAC is demanding and promising in recent years. Among the calibration techniques, correcting errors using digital signal processing rather than analog has become an attractive scheme [3, 16, 17, 32, 33]. In these schemes, the analog errors are treated into distortions in the digital domain, therefore we can digitally correct them.

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Having understood how bad the ADC is or what/where the error is, we can correct errors according to the estimation results. For example, the digital output of a pipelined ADC is obtained by the recombination of each stage’s raw codes. That is, the digital gains must match the analog gains of each stage otherwise the ‘noise-leakage’ would occur, causing performance loss [34]. Under this condition, if only the linear gain error is concerned, the errors in the digital output is proportional to the difference between the analog and the digital gains. If the accurate estimate of this difference is available, we can adjust the digital gain accordingly, recovering the ADC accuracy.

Based on the error correction/estimation mechanism, the calibration techniques can be categorized into four types: analog/digital and foreground/background cal-ibrations. Foreground calibration techniques estimate the errors when the input is not applied to the converter and then the correction is performed in analog or digital domain; background ones estimate the errors during the normal operation, and then the correction is performed in analog or digital domain. Thanks to the robustness of digital signal processing and their easy-to-implement feature in the CMOS technol-ogy, digital background calibrations compare favorably to analog/digital foreground ones. The key concepts of various proposed calibration schemes in literature can be classified into two topologies: area-redundancy and time-redundancy. They will be explained in this chapter in detail.

4.2 Area-Redundancy

SHA Pipelined ADC Core Algorithmic ADC Digital Post Processing Raw Code Algorithmic Output Calibrated Code Vin Vin1 fs/M fs fs

Figure 4.1: Queue-based calibration [4].

An area-redundancy topology uses extra analog circuits such as a slow-but-accurate reference ADC [4, 14, 15], split-ADC architecture [5, 7], or more than one SHA [4, 6], etc., to measure and calibrate the main ADC. In Fig. 4.1, a slow-but-accurate reference ADC takes the same input as the pipelined ADC core and then compares one out of M samples of its output to the corresponding digital output of the ADC core. As a result, the difference between both outputs is used as an

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advantage of deterministic calibration process since the error information is obtained directly through the outputs instead of statistical manner. Although the reference ADC can achieve very high resolution using a Σ∆ or an algorithmic ADC, the refer-ence ADC usually limits the achievable resolution of the main ADC after calibration. On the other hand, the linearity of the reference ADC is still confined and may not adaptable to the continuing scaled process. Prior calibration of the reference ADC may be necessary before calibrating the main ADC.

ADC 'A'

ERROR

ESTIMATION

ADC 'B'

x

_A

x

_B

v

IN

Digital Out put

!

"#

$

x =

x

A

+ x

B

2 ∆x = x

B

− x

A

!

"#

$

Di f f erence

Figure 4.2: “Split ADC” architecture [5].

The split-ADC architecture, as shown in Fig. 4.2, works in the way that the ADC is split into two channels. Each of them takes the same input and produces individual outputs. If both channels are completely calibrated, the average of the individual outputs agrees; otherwise, the difference is served as a calibration signal so as to develop the background calibration. Hence, this technique plays a role analogy to the channel equalization commonly encountered in communications and tries to make the average error power as small as possible. Compared with [3,17,35], this method has the benefit of short calibration time. However, if one of the channels drifts more severe than the other one, the calibration results would be biased, leading to imperfect calibration result.

Shown in Fig. 4.3 is a queue-based architecture [6] with its timing plot illustrated in Fig. 4.4. This architecture uses two or more sample-and-hold circuits in order that some reference signals can be inserted within the same conversion cycle. The inserted signal is then used to calibrate the main ADC due to use of faster clock than the conversion rate. However, the faster clock may lead to large over-design, leading to large area overhead; it is because all the components must be able to operate at the high clock rate rather than the conversion rate. Another drawback

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SHA

1 SHA

1 Logic

ADC

x(t)

f

s

f

c

Figure 4.3: Queue-based calibration [6].

S1

S2

S3

S4

S5

S1

S2

S3

S4

CAL.

S5

SHA

1 ADC

f

_c

f

_s

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is the limitation on the available acquisition time that is often shorter than half the clock period.

4.3 Time-Redundancy

A time-redundancy topology estimates the nonlinear information for a period of time, and then the statistical result is processed or fed into an iterative function so as to calibrate the ADC. Recently, one such kind of technique called correlation-based [35] calibration becomes more and more popular. This technique features negligible hardware overhead for calibration and the capability to work concurrently during the normal operation. The basic concept lies in modulating the input signal with a pseudo-random sequence that is uncorrelated with the input, then the digital outputs are demodulated in order to extract the modulated error information. Since the modulated errors take same analog path as the input, demodulated information thus contains the characteristic of the ADC. Then the information is applied to the calibration circuits for the ADC calibration. A conceptual diagram is depicted in Fig. 4.5. Generally, the insertion of pseudorandom sequences is realized by changing the threshold levels in the sub-ADC [3, 7] or abstractly adding scaled references to the sub-DAC [17, 35]. Whichever is used, both result in the residue shifting up or down, leading to different distribution. By observing the distribution, we can extract the nonlinear information.

S/H

Scrambler

Backend ADC

2

n

n-b

A/D

n-b D/A

RNG

2

n

2

n

2

n

e

V

in

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Chapter 5 DIGITAL CALIBRATION

5.1 Introduction

Digital calibration performs the task of digitally correcting the gain errors of im-precise residue amplifiers due to the finite open-loop gain, slewing, and capacitors mismatch. Some techniques can correct errors by means of carrying out digital sig-nal processing on the ADC output codes and therefore remain the residue amplifier inaccurate. This implies the need of calibrating error by using analog circuits is reduced. Also, high order harmonics such as third, fifth order nonlinearities of the residue amplifier can be corrected through the use of more complex digital circuits. This feature is desirable since the cost/function of digital circuits decreases by 29% each year [36].

Generally, all calibration techniques are built based on their analog error models; that is to say, only the errors capable of being modeled as an equation or any other analytical problems can be calibrated. Therefore, only the deterministic errors can be corrected. As a result, model-based error estimation and calibration turn to be the key concept among the self-calibration techniques.

Many digital calibration techniques have been proposed to tackle the non-perfect analog functional blocks. Those blocks include the imprecise capacitors ratio in the sub-DAC or the non-ideal residue amplifier, including the finite open-loop gain and incomplete settling, etc. Sine the errors arising from these blocks can be mod-eled as deterministic representations, equations that include error terms, the basic calibration concept among these techniques is quite similar. The ADCs are self-calibrated in the manner: the residues of each stage are individually observed using their remaining stages of the pipeline ADC. Then based on the observed results, the weighting of the gain within each stage can be recalculated, therefore obtaining the accurate outputs. For example, since the contribution of each stage to the origianl digital output can be represented as its weight [18, 37], we can adjust the estimated

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εa Sub-ADC Sub-DAC

Backend

ADC

G

₁

1/ ˆ

G

1

D

₁

V

in

D

out

ε

b

D

b

V

x

Figure 5.1: Pipelined ADC stage macro model [8].

gain in the digital domain to match the analog gain. Considering Fig. 5.1, we have Dout = D1+ Db ˆ G1 = (Vin+ εa) + G1(−εa) + εb ˆ G1 , (5.1)

where D1(= Vin + εa) is the conversion result of the first stage and and Db the

digitized residue of first stage. εa and εb represent the quantization noises in the

sub-ADC and the backend ADC accordingly, and ˆG1 is the estimate of G1 of the

residue amplifier in the first stage. If G1 is linear and invertible such that ˆG1 = G1,

(5.1) becomes Dout = Vin+ εb ˆ G1 . (5.2)

As a consequence, the output can be represented as the original input plus the total ADC quantization noise. In general, G1 is intentionally designed to the power

of 2 and therefore the digital output is obtained just by shifting bits and then adding together. In fact G1 deviates from its ideal value, shifting bits results in the

quantization noise of the sub-ADC leaking to the next stage. Odd harmonics thus arise in the spectrum due to the quantization noise of the sub-ADC correlating with the input, leading to performance degradation. Therefore, calibration is required to find out the digital gain ˆG1 that match the analog gain G1 of the residue amplifier.

5.2 Overview

In the following sections, we will describe a fully digital background calibration tech-nique that is capable of correcting the errors arising from the non-perfect residue

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amplifiers [3]. Then this technique is used and combined with the proposed estima-tion technique to highlight the proposed calibraestima-tion scheme in this thesis.

εa Sub-ADC Sub-DAC

error

G

1

D

1

V

in

ε

b

V

x

B bits

Calibrated Stage

Backend ADC

Figure 5.2: Precision requirements

Shown in Fig. 5.2 is the precision requirement after calibration. It indicates errors from the stage to be calibrated can be modeled as an additive term at the input of the backend ADC. To make the error have no impact on the ADC performance, its value must be within 1/2 LSB (the quantization noise εb) of the backend ADC.

Stage 1 Stage 2 Stage N-i Stage N

RNG Estimation Calibration Estimation Calibration RNG D1 D2 DN−i Dout Vin Ctrl 1/GN−i D_b,N−i+1 Db1 DN

Figure 5.3: ADC block diagram

Fig. 5.3 shows the block diagram of the proposed calibration scheme includ-ing three main digital calibration functions: the pseudorandom sequence generator (labeled as ‘RNG’), the calibration (labeled as ‘calibration’) block, and the estima-tion (labeled as ‘estimaestima-tion’) block. The pseudorandom sequence generator injects multiple uniform distributed noise sequences (dithers) at the sub-DAC input. The estimation block performs the task of system identification so as to blindly find the

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Fig. 5.3, the backend ADC does not need to be calibrated since the resolution of the backend ADC is low (usually 6-8 bits); therefore, it is less significant compared with the front-end stage.

The calibration processes in the way that the least significant stage (e.g., stage i-1) is calibrated using the backend ADC (the remaining stages). Once the calibration of that stage is done, the calibration proceeds toward its front stage (e.g., stage i), and therefore the total resolution grows linearly with the calibration process, which shows similarity to the ‘accuracy bootstrapping’ [37]. Although the completion of the calibration within each stage is done once at a time, calibrations of each stage can work concurrently. That is, the calibration of each stage comes about simultaneously and ends after the calibration of the most significant stage is done.

To simplify the analysis, all stages are assumed to be ideal except for the first stage as represented in Fig. 5.1. Since the fully differential architecture is often adopted all over the high resolution ADCs, the even harmonics are much less signif-icant as a consequence. Under this condition, the fundamental tone and the third harmonic will dominate the overall performance [3, 17]. If those above conditions are satisfied, the object to be calibrated, the open-loop residue amplifier in the first stage, can be approximated as a third-order polynomial:

G1(Vx) = Vres= a1(Vx) + a3(Vx)3, (5.3)

where Vx= −εa. Alternative models can be found in [38].

5.3 Calibration Mechanism

Nonlinear gain error of the residue amplifier are first calibrated since it will affect the estimation of the linear gain error. In order to correct the nonlinear errors, one possible solution is finding the nonlinear term a3(Vx)3 in (5.3) then being

sub-tracted from the original residue, which can be realized by using an inverse function described in [3].

After the nonlinear term a3(Vx)3 is corrected, linear gain error can be calibrated

by recalculating the digital gain with respect to each stage, thus obtaining a lin-earized output.

5.3.1 Nonlinear Gain Error Calibration

Rearranging (5.1) in a more general form, we have Dout = D1+ G−11 (Db)

= (Vin+ εa) + G−11 [G1(−εa) + εb], (5.4)

where G−1₁ is the inverse of G1 provided that G1 is invertible.

Taking the first order Taylor expansion of the last term in (5.4) gives Dout ∼= Vin+ εa+ G−11 [G1(−εa)] + εb dG−1₁ dDb = Vin+ εb dG−1₁ dDb = Vin+ εb dG1 d(−εa) −1 . (5.5)

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According to (5.5), the output can be represented as an input and an output-referred inverse function. To make the residue linear, the nonlinear term a3(Vx)3 needs to be

removed; therefore a linearized residue can be obtained by

Vres,linear= G1(Vx) − e(Vx). (5.6)

Observing this equation, we can represent e(Vx) as

e(Vx) = G1(Vx) − a1G−11 (Vres). (5.7)

Using the fact Vx = −εa= G−11 (Vres), Vres= Db− εa and substituting them into

(5.7), we obtain e(Db) represented in digital domain [39]:

e(Db) ∼= Db− a1G−11 (Db) − εb " 1 − a1 dG1 dVx −1# ∼ = Db− a1G−11 (Db). (5.8)

As a result, (5.8) is used to correct the nonlinear error. Observing the neglected term εb[1 − a1(dG_dV_x1)−1], how much will it affect the precision of the calibration?

Considering εb[1 − a1(dG_dV_x1)−1] in (5.8) while taking the differential of G1 with respect

to Vx, we can further expand it as

εb[1 − a1( dG1 dVx )−1] = εb· " 1 − a1 dG₁ dVx −1# = εb 1 − a1 1 a1+ 3a3ε2a . (5.9)

If dividing both sides by εb, we obtain a relative error with respect to the backend

quantization error in LSB such that error = εb/εb 1 − a1 a1+ 3a3ε2a ≈ 1 − 1 − 3a3 a1 ε2_a = 3a3 a1 ε2_a. (5.10) Indicated by (5.10), it implies a multi-bit architecture is preferred because of a1 in the denominator, resulting in less harm to DNL; however even with a

single-bit architecture, the redundancy topology makes εa a relatively small value when

compared to εb. Thus, the neglected term makes an relatively small error on DNL

and the accuracy consequently.

To find G−1₁ (Db) in (5.8), a trigonometric approximation is used [3]

e(Db) = Db− 2 s −a3 1 3a3 cos   π 3 + 1 3cos −1   Db 2 q −a3 1 27a3    . (5.11)

The above equation points out e(Db) only depends on the digitized residue Db and

the ratio a3/a31; that is, once this ratio is found, the linear residue can be recovered

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5.3.2 Linear Gain Error Calibration

Considering Fig. 5.1 and rearranging (5.1), we have ˆ

G1 · Dout = ˆG1· D1+ Db.

The digital output Dout thus becomes

Dout= ˆG1D1+ Db. (5.12)

Observing this equation, the local conversion result D1 has become ˆG1D1, which

results in a global gain error of the whole ADC; however, this global gain error is tolerable in most applications such as digital communication in which the ADC is preceded by an automatic gain control (AGC) amplifier. As a result, the linear gain calibration is accomplished by recalculating the digital gain that matches the analog gain.

5.4 Summary

Fig. 5.4 summarizes the digital calibration mechanism. Two arguments p1 and

p3 depicted in Fig. 5.4 are the correction parameters to compensate for the linear

and nonlinear gain errors respectively. According to the description above, their optimum values are expressed as

p1,opt = a1 p3,opt = a3 a3 1 , (5.13)

where they correspond to a1 and the ratio in (5.11).

In practice, the characteristics of the residue amplifier may drift due to temper-ature, time, process, etc, resulting in varying p1 and p3. For open-loop amplifier

implementation, these variations become even sever in the absence of feedback. As a result, in next chapter we propose a novel digital calibration scheme that can accurately estimate the real amplifier operating condition and adaptively update p1

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e(D

b

)

p

1

p

₃

D

1

D

out

Calibration

Estimation

D

b

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Chapter 6 MULTI-CORRELATION

ESTIMATION (MCE)

TECHNIQUE

6.1 Introduction

In the following sections, we propose a novel calibration scheme that can accurately estimate and correct errors arising from the residue amplifiers and continuously track and update the correction parameters against environmental variations. Because us-ing the open-loop amplifier rather than closed-loop one in the pipeline stages, the amplifier may substantially changes its transfer function due to the absence of feed-back. This condition dictates the need of fast updating the correction parameters. Under this condition, the proposed scheme enables fast and continuous estimation for the varying amplifier in short time intervals as compared to [35]. Meanwhile, the scheme operates during the normal ADC conversion with no scheduled calibra-tion cycles or use of redundant hardware [15] or slots queues [4, 40] to enable the background feature.

To estimate the error information about the MDAC or the amplifier, many cal-ibration techniques have been proposed. Some techniques need additional stages [3, 18, 37] to reduced the backend ADC quantization noise, enabling precise estima-tion of the transiestima-tion heights that relate to amplifier’s gain. Fig. 6.1 indicates that the transition height of the residue is proportional to the amplifier’s gain [41–43]. However, some of such techniques need to stop the input then a calibration signal can be applied as in [18], which is not allowed in many applications. Other ap-proaches acquire the nonlinear information by using a parallel ADC to compare the difference of an ideal output (from the parallel ADC) and a real one (from the main ADC) [1, 44]. Fig. 6.2 demonstrates this idea.

For instance, the split-ADC architecture extracts the nonlinear information using separated ADC channels [5, 7]. If these channels were non-perfect, the unbalanced channels generate different outputs that can be used for nonlinearity correction as shown by Fig. 6.3 and 6.4. While such techniques have the advantages of de-terministic error extraction therefore reducing the calibration time, they increases

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0

0 H

V

in

V

res

V

re f

−V

re f

1/4V

re f

3/4V

re f

−3/4V

re f

−1/4V

re f

Figure 6.1: Transition height of digitized residue.

S/H

Pipelined

_ADC

Slow-but-accurate

ADC

f (D)

e

V

in

D

ˆD

_in

D

in

+ Q

(44)

analog circuits’ complexity, imposing penalties of larger die area, power, and band-width [45].

ADC 'A'

ERROR

ESTIMATION

ADC 'B'

x

A

x

B

v

_IN

Digital Out put

!

"#

$

x =

x

A

+ x

B

2 ∆x = x

B

− x

A

!

"#

$

Di f f erence

Figure 6.3: “Split” ADC architecture [5].

Some calibration techniques, called the correlation-based technique, use statisti-cal functions to estimate errors therefore being able to correct gain errors have been presented in literature [17,35,44]. In these techniques, the analog error is modulated using a pseudo-random noise sequence and then the digital output is processed in order to extract the error information useful to calibrate the ADC.

Having described the features of above techniques, we propose a technique that has the following superiorities:

• No limitation on the input amplitude:

The benefit of the proposed technique relative to that presented in [3] is that it works for any input signal, and the benefits relative to that presented in [17] are that it does not have restrictions on dc input and it is not sensitive to amplifier offsets.

• Reduced circuit complexity:

The proposed calibration scheme cooperated with statistics-based estimation enables the use of a low resolution backend ADC. Unlike the work in [3], the resolution of the backend ADC is no longer limited by the target resolution minus one. Therefore, employing simple circuits yields the potential toward high speed and/or low power. To facilitate the estimation, the required pseu-dorandom noise sequences (RNGs) only needs negligible modifications on the sub-DAC.

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ADC

DAC

ADC

DAC

G+ G− Backend ADC Backend ADC Post cal. 1/4 1/4

RNG

1

RNG

2

V

_i+

V

_i−

V

_o+

V

_o−

D

out

Figure 6.4: Two channel ADC architecture [7]. • Digital background calibration:

All the calibration circuits are built using digital circuitry. Given that the input acts as a stimulus and is modulated with the RNGs, the scheme performs error estimation and calibration during the normal operation of the ADC. • Unbiased gain error information extraction:

With the simple statistical function (mean function) and the estimation pro-cedure, the linear and nonlinear gain error information of the amplifier can be extracted independently. Notably, error information of high order nonlineari-ties, e.g., 5th order, is possible if more RNGs are merged.

In the following sections, we will describe the technique with the associated functions in detail.

6.2 Modulation Approach

The proposed scheme makes use of the fact that the offsets in the sub-ADC does not affect the ADC conversion results based on the digital redundancy [21]. As a result, the scaled random noise sequences whose values no more than the tolerable offsets can be applied using either the sub-ADC or the sub-DAC. Because of the added random sequence, the residue moves up/down. Fig. 6.5 shows one possible residue plot when the RNG is added. It shows that one input signal may have two different residues. However, their conversion results agree provided that the gain errors are perfectly corrected. Similar approaches can be found in [3, 7, 17, 35, 44].

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V

_in

V

res

V

re f

−V

re f

V

re f

−V

re f

RNG=1

RNG = -1

(47)

In order to unbiasedly estimate the correction parameters, the RNG is designed as a uniformly distributed pseudorandom binary number sequence, i.e., (RN G ∈ {1, −1}) and is uncorrelated with the input. As a result, the RNG is continuously applied to the stage being calibrated to continuously estimate and update the cor-rection parameters.

In the remainder of this chapter, we propose a multi-correlation estimation (MCE) technique using the modulation approach, allowing continuous background estimation of the correction parameters p1 and p3 described in the previous chapter.

6.3 Multi-Correlation Estimation (MCE) Technique

In this section we will describe a technique based on statistics that can estimate the correction parameters. Using two different modulated sequences, this approach results in the residue having different distributions. Then the statistical results associated with the residues are used to find the nonlinearities, i.e., the error infor-mation. With the help of this information, we can approach the optimum values of p1 and p3 using Least Mean Square (LMS) algorithm [46].

Calibration εa Sub-ADC Sub-DAC εb

Backend

ADC

D

1 Estimation RNG

p

1

p

3 Ga

V

d1

,V

d2

C

trl

V

in

D

out

_D

_b

Figure 6.6: Reduced model with proposed calibration scheme.

Considering Fig. 6.6, the digitized residue Db when the random sequences are

applied is

Dbi = a1(Vx) + a3(Vx)3 + εb

= a1(−εa+ Ri· Vdi) + (−εa+ Ri· Vdi)3+ εb, i ∈ {1, 2} (6.1)

(48)

Therefore, Ri times Vdi, i.e., RiVdi add offsets of ±Vd1 or ±Vd2 LSB (of local

sub-ADC) to the sub-DAC. They are

R1Vd1 ∈ {+Vd1, −Vd1},

R2Vd2 ∈ {+Vd2, −Vd2}.

Taking the correlations of Dbi and Ri, we have

E[RiDbi] = Ea1(−Riεa− Vdi) + a3(−Riε3a− 3ε 2 aVdi− 3RiεaVdi2 − V 3 di) + Riεb . (6.2) Because Ri are uncorrelated with the input, correlations of Ri and the quantization

errors εa, εb will be zero. Under this circumstance, (6.2) is further reduced to

E[RiDbi] = a1(−Vdi) + a3(−3ε2aVdi− Vdi3). (6.3)

This finding reveals the quantization noise of backend ADC has no effect on the estimation accuracy as compared with [3].

Considering the terms a1(−Vdi) and a3(−3ε2aVdi) in (6.3), if they can be

elimi-nated, the result is proportional to a3. For such a reason, we propose a technique

called “multi-correlation estimation technique” that can accurately estimate the er-ror information.

Using (6.3) and Vd2= Vd1/2 = LSB/4 gives

ε3 = E[R1Db1] − 2E[R2Db2] = −

3 4a3V

3

d1. (6.4)

In this equation, ε3 represents the sum of correlations E[R1Vd1], E[R2Vd2] and is

directly proportional to a3, leading to an unbiased estimation. If the correction

function (5.11) is applied, we obtain ε3 = − 3 4a3V 3 d1= − 3 4a 3 1V 3 d1· (p3,opt− p3). (6.5)

This result indicates the deviation of parameter p3 from its ideal value is directly

proportional to ε3. According to this result, we can use iterative functions, e.g.,

LMS algorithm, trying to minimize the deviation so as to obtain the ideal value of p3.

As can be seen from the derivation of ε3, it only represents the degree of nonlinear

term a3. Hence, we need another error information related to the linear gain a1.

Indicated by (6.3), the resulting correlation is proportional to a1 when a3 = 0. That

is, when the nonlinear gain error has been corrected, we define (6.3) as

ε1 = E[R1Db1] = a1(−Vd1), (6.6)

where ε1 represents the linear gain error information. In addition, correlation of

R2 and Db2 can be used as well. Since p1,opt = a1 as indicated in (5.11), it is

straightforward that dividing ε1 by Vd1is p1,opt. However, this procedure takes large

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samples are required to obtain sufficiently accurate estimate of a1 [5]. Above results

suggest that fast updates of p1 and p3 is desirable. As a result, we employ LMS

algorithm to achieve this goal. Although making use of LMS still needs an amount of time to converge the corrections parameters to a sufficient accuracy, once they have converged, each update is fast enough to track the environment variations. In order to be merged in the LMS loop, ε1 is modified as

ε0₁ = ε1 p1 + Vd1 = − a1Vd1 p1 + Vd1. (6.7)

In this modification, p1 will approaches p1,opt when ε01 = 0 by using LMS.

6.4 Adaptive Signal Processing

G(z)

d(n)

y(n)

e(n)

x(n)

W(z)

unknown system

linear combiner

Figure 6.7: Adaptive system performing system identification.

Adaptive signal processing performs the task of identifying the “model” of an unknown “system” based on the knowledge of a certain input x(n) and its corre-sponding output d(n) to the system [46]. Fig. 6.7 shows a typical block diagram of an adaptive system. The error signal e(n) is made by subtracting the adaptive linear combiner’s output y(n) from the desired output d(n). Then e(n) is fed back to W (z) in order to update parameters of the combiner; as a result, W (z) tries

一個適用於多級類比數位轉換器的嶄新數位背景修正方法

國

立 交 通 大 學

電

機 與 控 制 工 程 研 究 所

碩

士 論 文

一個適用於多級類比數位轉換器的

嶄新數位背景校正方法

A Novel Digital Background Calibration

Scheme for Multistage ADCs

研 究 生：吳孟軒

指導教授：洪浩喬 教授

一個適用於類比數位換轉換器的嶄新數位背景修正方

法

A Novel Digital Background Calibration Scheme

for Multistage ADCs

研 究 生：吳孟軒

Student : Meng-Shuan Wu

指導教授：洪浩喬 教授

Advisor : Hao-Chiao Hong

國 立 交 通 大 學

電 機 與 控 制 工 程 研 究 所

碩 士 論 文

誌謝

一個適用於類比數位轉換器的嶄新數位背景校正方法

學生：吳孟軒

指導教授：洪浩喬博士

國立交通大學

電機與控制工程研究所碩士班

摘要

A Novel Digital Background Calibration

Scheme for Multistage ADCs

Abstract

Table of Contents

List of Figures

List of Tables

Chapter 1

INTRODUCTION

1.1

Motivation

1.2

Overview

1.3

Chapter Organization

Chapter 2

PIPELINED ADC OVERVIEW

2.1

Fundamentals of Pipelined ADC

First Stage

Second Stage

Amplification by 2

MSBs

LSBs

11

10

00

01

11

10

00

01

01

11

V

Stage 1

Stage 2

Stage N

2.2

Digital Error Correction

V

in

V

res

ε

b

V

re f

−V

re f

立交通大學

機與控制工程研究所

士論文

研究生：吳孟軒

指導教授：洪浩喬教授

研究生：吳孟軒

指導教授：洪浩喬教授

國立交通大學

電機與控制工程研究所

碩士論文

_res

_{re f}

_s