Chapter 2 Analysis of Current Distribution and Excited Radiation in
2.4 Summary
In this chapter, an efficient analysis method for MTL systems is proposed, with which the voltage/current distribution, mode conversion, and crosstalk can be predicted.
Besides, this method can be also applied for radiation estimation by employing the concept of antenna mode. Once the amount of AM current is known, the relative radiation power among different structures or discontinuities can be calculated. The accuracy of the proposed method is proved by comparing the analyzed/simulated results with the commercial full-wave simulation tool.
Fig. 2.15. Simulate radiated power (by HFSS) versus the square of the peak of AM current under CM excitation (by proposed method).
Chapter 3
pter 3 A Compact TSV-Based Common-Mode Filter (TSV-CMF) in Three-Dimensional Integrated Circuits
Common-mode noise coupling problems become more critical in three-dimensional integrated circuits (3-D ICs), which have been considered as one of the main technologies to keep Moore’s law [49]. By stacking chips vertically and shortening the length of interconnects with the help of through-silicon vias (TSVs), higher throughput in signal transmission can be attained. However, due to the special process limit such as keep-out zone and metal coverage, as well as unavoidable asymmetric grounded-lines placement, imbalance in the differential signaling channel will become more serious. In addition, heterogeneous integration and increase of circuit density also enhance the noise coupling.
Fig. 3.1 shows a typical scenario of 3-D ICs for millimeter wave (mmW) wireless communication circuits including the baseband and RF transceiver, which are packaged on a silicon (or glass) interposer. A central processing unit (CPU) stacked with dynamic random access memory (DRAM) is located at the center of the package, and a graphics processing unit (GPU) stacked with graphics double data rate (GDDR) memory is adjacent to the CPU. High bandwidth data access between CPU and GPU is through the
differential channels on the interposer. An mmW transceiver stacked with microelectromechanical systems (MEMS), and an antenna is also placed on the interposer for wireless communication. Significant noise coupling from the high-speed digital channels (or memory access) to the mmW transceiver (and antenna) is expected.
These noise problems will reduce the sensitivity of the transceiver and degrade the data throughput of the mmW communication. Hence, a common-mode filter embedded inside 3-D ICs to reduce the undesired common-mode radiation and corresponding noise coupling is essential and proposed here.
Fig. 3.1. A configuration of a 3-D ICs for an mmW wireless communication circuits and common-mode noise coupling problems.
3.1 Proposed Circuit Topology for TSV-CMF
3.1.1 Theories and Models of Proposed TSV-CMF
The full circuit of proposed TSV-CMF is illustrated in Fig. 3.2. It is a four-port circuit with a pair of differential input ports (in+ and in-) and a pair of differential output ports (out+ and out-). Ports in+ and out+ are connected with a lumped transmission line in terms of second-order T model. The lumped transmission line looks like a 5-order low-pass filter with three series inductance (0.5L1, L1, and 0.5L1) and two shunt capacitances (both C1). Another lumped transmission line with the same elements is used to connect ports in- and out-. The return paths of the two lumped transmission lines are connected to the system ground with an additional common inductance L2.
Since the proposed circuit in Fig. 3.2 is fully symmetric, even- and odd-mode analysis can be applied to characterize the electrical behaviors of common mode and differential mode, respectively.
-3.1.2 Equivalent Circuit and Analysis of Differential Mode
Fig. 3.3 shows the odd-mode half circuit, where the inductance L2 is replaced with a short circuit due to the perfect electric conductor (PEC) boundary. Then only the transmission line part is left in the circuit. And it is expected that the odd-mode signal (and equivalently for differential mode) can pass through it.
3.1.3 Equivalent Circuit and Analysis of Common Mode
The even-mode half circuit is shown in Fig. 3.4. Due to the perfect magnetic conductor (PMC) boundary, the additional inductance is equivalently with twice the value, or noted as 2L2. When the transmission line part resonances with the inductance 2L2, it will form a path that is short to ground and then prevent the transmission of the incident wave.
Fig. 3.3. The odd-mode half circuit (and also equivalent for differential mode) of the proposed TSV-CMF in Fig. 3.2.
C
1C
10.5L
1L
10.5L
1
To estimate the transmission zeros (TZs) for this circuit, even- and odd-mode analyses are applied here again to the even-mode half circuit in Fig 3.4, and two one-port circuits are formed. As illustrated in Fig. 3.5(a) and Fig. 3.5(b) respectively, the Fig. 3.4. The even-mode half circuit (and also equivalent for common mode) of the proposed TSV-CMF in Fig. 3.2.
C
1C
12L
20.5L
1L
10.5L
1(a) (b) Fig. 3.5. The equivalent one-port circuit by applying even- and odd-mode analysis to
the half circuit in Fig. 3.5(b). (a) The even-odd quarter circuit. (b) The even-even quarter circuit.
even-odd quarter circuit and even-even quarter circuit are with input impedance Zin_eo
and Zin_ee, which can be calculated as
( )
1where ω is the angular frequency.
Then from the formula of S21e which can be written as
( )
it is obvious that the TZs for even mode (and equivalently for common mode) will occur when Zin_eo is equal to Zin_ee , as introduced in the previous chapter. Then the equation of ω for the TZs can be derived as
4 2
or can be rewritten in frequency with unit of Hz as :
1
3.1.4 Designed Electrical Parameters and CM Responses
Two cases are simulated to demonstrate the relationship between the electrical parameters (L1, L2, C1) and the CM stopband in the circuit tool (ADS). As listed in Table 3.1, (L1, L2, C1) for Case 1 and Case 2 are (0.25 nH, 0.325 nH, 0.1 pF) and (0.57 nH, 0.46 nH, 0.15 pF), respectively. Fig. 3.6 shows the simulated |Scc21| for both cases. As expected by (3.6), two TZs in Case 1 are located at 14.8 GHz and 42.5 GHz, whose separation is far due to the small value of L1/2L2 = 0.385. The CM stopbands (defined with insertion loss of 10 dB) around these two TZs are narrow with a fractional bandwidth (FBW) of 21% and 35%, respectively.
Parameter Case 1 Case 2
Inductance L1 0.25 nH 0.57 nH
Inductance L2 0.325 nH 0.46 nH
Capacitance C1 0.1 pF 0.15 pF
Expected frequency of the 1st CM TZ f1 14.8 GHz 10.7 GHz Expected frequency of the 2nd CM TZ f2 42.5 GHz 21.9 GHz
Table 3.1. Electrical parameters of the design
And as in Case 2, the ratio of L1 to 2L2 is chosen as 0.69, which is much larger than that in Case 1, to reduce the separation between the two TZs. Besides, the values of L1
and C1 are also increased to shift the two TZs to lower frequency band (10.7 GHz and 21.9 GHz). From the dashed curve in Fig. 3.6, it is clear that a broader CM stopband with FBW of 91% is formed since the two TZs are close enough.
However, in most of the conditions, it takes more chip area to implement larger L1
and C1, which implies a higher cost. Hence, a TSV-based CMF is proposed here to save the space and solve these problems.
3.2 Implementation of Proposed TSV-CMF
3.2.1 Fabrication Process: ABF-Coated Interposer
The proposed TSV-CMF is implemented in a silicon interposer process named Ajinomoto build-up film-coated (ABF-coated). The main differences between this and Fig. 3.6. Simulated CM response of proposed TSV-CMF with electrical parameters in Table 3.1.
typical interposer processes are the material and process of the TSV insulator layers. By using a PCB-like method to form the vias and ABF-based insulators, this process becomes relatively cost-efficient compared with the typical ones [50]. In addition, thicker insulator around TSVs can be achieved in this process, which can reduce the slow-wave factor (SWF) and improve the quality of transmitted signal [51], [52]. But on the other hand, in this ABF-coated process, the minimum line width and spacing are limited by the lithography (about 50 μm), which is much larger than those in typical chip processes or integrated passive devices (IPDs).
The chip and interposer, which are mounted together with bumps, are fabricated with an identical process in this demonstration. The corresponding stack-up and the cross-section are illustrated in Fig. 3.7 with the physical parameters listed in Table 3.2.
A little difference between the chip and the interposer is that TSVs are formed only in the chip but not in the interposer. The metal lines and TSVs are formed with copper, and the ABF-based insulator has a relative permittivity of 3.35.
Fig. 3.7. The stack-up of the chip and interposer in the ABF-coated process.
Parameter Value
Thickness of metal M1 (tM1) 25 μm
Thickness of metal M2 (tM2) 40 μm
Thickness of metal M3 (tM3) 40 μm
Thickness of substrate between M1and M2 (tS1) 20 μm Thickness of substrate between M2and Si (tS2) 35 μm Thickness of substrate between M3and Si (tS3) 35 μm
Height of TSV (hTSV) 100 μm
Diameter of TSV (DTSV) 70 μm
Thickness of insulator around TSV (tins) 15 μm
Diameter of via (Dvia) 60 μm
Diameter of via pad (Dpatch) 110 μm
Separation of metal (s) 90 μm
Conductivity of metal (σm) 5.8 × 107 S/m Conductivity of silicon (σSi) 10 S/m
Table 3.2. Physical parameters of the ABF-coated interposer process.
3.2.2 Physical Structure and Layout
Typically, vertical interconnections, such as bumps and TSVs, are part of the high-speed channels in 3-D IC. These elements will contribute unwanted parasitics and cause SI problems if not designed well. In this work, smartly employing the equivalent inductive and capacitive effects of those vertical interconnects, a compact common-mode filter could be designed and embedded in the high-speed channel without consuming much horizontal chip area.
Fig. 3.8(a) shows the 3-D view of the proposed TSV-CMF while the layouts of each layer are illustrated in Fig. 3.8(b) to (e). The balanced input and output ports of the TSV-CMF are on the M2 of the interposer (bottom layer, noted as Interposer M2) as shown in Fig. 3.8(d). The input signal will go up vertically through bumps and TSVs (#1 and #2) to metal layer M1 of the chip (noted as Chip M1). The rectangular loops are designed on M1 of the chip (detail in Fig. 3.8(b)), and then the signal goes down through TSVs and bumps (#3 and #4) to the balanced output port on M2 of the interposer. It is noted that two ground pads are formed on M2 and M3 of the chip respectively (noted as Chip M2 and Chip M3, detailed in Fig. 3.8(c)). There is another TSV (#5) connecting between these two ground pads. The relative positions of those 5 TSVs are shown in Fig. 3.8(e). Mapping the TSV-CMF equivalent circuits in Fig. 3.2 to the 3-D layout in Fig. 3.8, it is found inductance L1 as well as L2 can be achieved by the TSVs, bumps (#1 to #4 for L1 and #5 for L2), and the rectangular loops on M1 of the chip. The capacitance between rectangular loops on Chip M1 and the ground pad on Chip M2 contribute the capacitance C1. The designed physical parameters listed in Table 3.3 are chosen to achieve the electrical parameters of Case 1 in Table 3.1 and make the first stopband of common mode located near 15 GHz.
(a)
(b) (c)
(d) (e) Fig. 3.8. The implementation of proposed TSV-CMF. (a) 3-D view of the structure
A testing sample of the TSV-CMF (Case 1) is fabricated based on the proposed structure illustrated in Fig. 3.8 under the ABF-coated silicon interposer process described in the previous section. Photographs of the sample from both chip side and interposer side are shown in Fig. 3.9, where the silicon substrate on the interposer is removed and four ground pads are added for probing measurement.
Parameter Value (mm)
Lengths of lines in Chip M1 (l1, l2, l3) (0.25, 0.25, 0.7)
Length of lines in Chip and interposer (l4) 0.15 Size of reference plane in Chip and interposer (l5, l6) (0.7, 0.8)
Table 3.3. Physical parameters of the design. The symbols are correspond with those in Fig. 3.8.
3.3 Results and Validation
3.3.1 Frequency-Domain Response
A pair of differential probes with a pitch of 250 μm (Cascade GSSG) and a 4-port vector network analyzer (Agilent N5247A) are used in measurement, where SOLT calibration is applied to remove the effect of cables and probes. The measurement and full-wave simulation results of the TSV-CMF are shown in Fig. 3.10. It can be seen that the insertion loss for differential mode is less than 3 dB from dc up to 25 GHz, which implies that this TSV-CMF will not degrade the high-speed differential digital signals of throughput around 25 Gbps. A CM transmission zero exists around 15 GHz, with insertion loss of about 15 dB and 20 dB in measurement and simulation, respectively.
The CM stopband, defined as |Scc21| < -10 dB, is from 13.7 GHz to 16.8 GHz in
(a) (b) Fig. 3.9. Photographs of the sample implemented with the ABF-coated process. (a)
The view from chip side. (b) The view from interposer side where four probing pads are added. It should be noticed that silicon substrate on the interposer is removed for probing measurement.
measurement with an FBW of 20%. Good agreement between the full-wave simulation and measurement results is clearly seen by applying the feature selective validation technique. The correctness of the 3-D IC fabrication process and the measurement setup is also validated. Fig. 3.10 also shows the modeled results based on a simple equivalent circuit illustrated in Fig. 3.4(b), whose element values (Case 1) are listed in Table 3.1. It is worth noting that only one TZ at 15 GHz is seen in Fig. 3.10 since as mentioned in Section 3.1.4, the other TZ at 42.5 GHz is far away and is not shown here.
It is found that the equivalent circuit model could favorably predict the TZ of common mode at 14.8 GHz. However, the differential-mode transmitted coefficient
|Sdd21| predicted by the equivalent circuit does not drop that much as the measured or full-wave simulated results. This discrepancy results from the conductor loss and Fig. 3.10. Comparison of results from equivalent circuit model, full-wave simulation and measurement.
dielectric loss which are not considered in the equivalent circuit model with only inductive and capacitive elements. Therefore, the model could give the designer a physical view of the TSV-CMF with good initial L/C values estimation, but fine tuning in the layout of the circuit is needed to obtain the optimized performance for the TSV-CMF. The chip area required for this design example is 0.72 mm2 (0.8 mm by 0.9 mm), which corresponds to 0.005 λg2 (λg is the wavelength in the dielectric at the lower bound of the CM stopband).
Fig. 3.11 shows measured mode conversion including |Scd21| and |Sdc21|, which are both less than -35 dB from dc to 25 GHz since the design is fully symmetric. Ideally, there should be no mode conversion (minus infinite in dB) for this structure, but the fabrication may induce some unavoidable imbalance. As a result, the mode conversion level is shifted a little higher but still tolerable.
Fig. 3.11. The measured mode conversion of the proposed TSV-CMF.
0 5 10 15 20 25
As shown in Fig. 3.12, the DM group delay is around 13 ps and with a small variation versus frequency. With such a small insertion loss and flat group delay for DM, this TSV-CMF is expected to keep a good eye for the digital signal, which will be shown and discussed in the next section.
3.3.2 Time-Domain Response
To compare the eye diagram with and without the proposed TSV-CMF, a reference board with 0.9-mm straight differential lines is added to be compared with the proposed TSV-CMF. A differential (213-1)-bit pseudorandom binary sequence (PRBS) with bit rate of 10 Gbps and rising/falling time of 20 ps is excited to both structures, respectively.
Fig. Fig. 3.13(a) displays the eye diagram of reference board, while that of proposed Fig. 3.12. The measured DM group delay of the proposed TSV-CMF.
0 5 10 15 20 25
TSV-CMF is shown in Fig. 3.13(b). As listed in Table 3.4, the eye height and eye width of the TSV-CMF are 489 mV and 97.1 ps, respectively, which are very close to those of the reference board (498 mV and 96.7 ps, respectively). This indicates that the proposed TSV-CMF would not degrade the quality of digital signal even the bit rate is as high as 10 Gbps.
Reference board Proposed TSV-CMF
Eye Height (40%-60%) 498 mV 489 mV
Eye Width (50%) 96.7 ps 97.1 ps
Table 3.4. Parameters of the DM eyes.
(a)
(b)
Fig. 3.13. Comparison of the DM eye diagrams under 10-Gbps PRBS. (a) Reference board. (b) Solution board with proposed TSV-CMF.
The suppression of CM noise can be validated in the time-domain waveform, too.
Both the structures (reference board and solution board with proposed TSV-CMF Case 1) are excited with the same PRBS source, but the positive and negative channels are with a time skew of 15 ps. This skew is used to model the unwanted imbalance in the real channel, and will induce some CM noise. As shown in Fig. 3.14, it is clear that with the help of proposed TSV-CMF, the peak-to-peak CM noise can be reduced from 240 mV to 140 mV, with a reduction ratio of 42%.
Fig. 3.14. CM suppression in the time domain of the TSV-CMF.
3.4 Results of TSV-CMF with More Stacked Chips
It is worth noting that by vertically stacking more chips, the stopband bandwidth of the TSV-CMF can be enhanced without increasing the chip size. Fig. 3.15 shows the concept of inserting one more chip (Chip B) between the interposer and the original chip (Chip A). TSVs and bumps are employed in Chip B to interconnect Chip A above and interposer below.
(a) (b) Fig. 3.15. The configuration of the proposed TSV-CMF with multiple stacking chips
(two chips stacked on an interposer as an example). (a) The 3-D view of the structure.
(b) The cross-section view (yz-plane) of the structure.
Fig. Fig. 3.16 shows the CM transmitted coefficients |Scc21| for the cases of 2 stacked chips (chip A and B with interposer) and 1 chip (chip A with interposer). It is seen that there are two transmission zeros, one is around 11 GHz and the other is around 22 GHz, for this 2-chip case. The stopband, which is defined by |Scc21| < -10 dB, is from 9.2 GHz up to 30 GHz. Compared with the 1-chip case, the fractional bandwidth is significantly increased from 20 % to 106 %.
The reason is that the effective length of the TSV #1 – TSV #5 is doubled by inserting one more chip (Chip B) in the stack, which will increase the equivalent inductance of L1 and L2 for the simplified LC model. The effective C1 will also rise slightly due to the coupling of TSVs and metal lines. As introduced in (3.6), the two transmission zeros will be shifted lower if the L1 and C1 are with larger values.
Fig. 3.16. The simulated CM response of proposed TSV-CMF with two stacked chips.
0 5 10 15 20 25 30
Besides, by routing more in the metal layers on Chip B, inductance L1 can be enhanced more than inductance L2. As explained in Section 3.1.3, the separation of two transmission zeros will decrease when the value of L1/2L2 is increased. As a result, the parameters of Case 2 in Table 3.1 can be realized. The transmission zeros are located closer and, as a result, 10-dB suppression for CM is achieved in a wide band, as shown in Fig. 3.16. By leveraging the parasitic effect of TVSs, which are the inherent parts for 3-D ICs, the TSV-CMF can be miniaturized in horizontal size and enhanced in common-mode stopband without degrading the differential-mode signal integrity.
Because the fabrication cost for stacking more chips is much higher, this part is demonstrated only in full-wave simulation.
The improvement of CM suppression can be also observed in time-domain. All of the three structures (reference board, Case 1, and Case 2) are under the same differential PRBS excitation with the same skew. It is obvious that from Fig. 3.17, the output CM noise after Case 2 is 80 mV (peak-to-peak), which is much smaller compared with the reference board (240 mV) and Case 1 (140 mV). That the suppression is so significant is because the CM noise converted from the DM signal is always broadband, so the bandwidth of CM suppression plays an important role. Here, the benefit from stacking chip is proved again.
3.5 Summary
In this chapter, a TSV-based common-mode suppressing filter is proposed to solve the noise coupling and EMI/RFI problems in 3-D ICs. By taking the vertical interconnects as part of design, the L/C parasitics of the TSVs can be beneficial for CM suppression. In addition, since some of the circuit elements have been implemented with vertical interconnects, the area for RDL lines can be reduced. This TSV-CMF is based on a differential second-order T-model circuit and can contribute two TZs for common mode. By analyzing the circuit model, design methods of the CM stopband are also proposed. Both the TZs can be controlled by choosing the suitable combination of lumped inductance and capacitance. To validate the proposed concept, a TSV-CMF is implemented in an ABF-coated silicon interposer process with a compact size of 0.72 Fig. 3.17. CM suppression in the time domain of the TSV-CMF.
mm2. The CM stopband is located at 15 GHz with an FBW of 20%. Good agreement among equivalent circuit simulation, full-wave simulation and measurement can be
mm2. The CM stopband is located at 15 GHz with an FBW of 20%. Good agreement among equivalent circuit simulation, full-wave simulation and measurement can be