Chapter 2. One Bit Quantized Digital PLL System Overview
2.3. Summary
In this chapter, we introduce a general block diagram of PLL and explain the function of each block. Besides, we know that ADPLL is easier to design than the analog PLL. For reducing the complexity of ADPLL, we employ one bit quantization.
Then, we discuss the one bit quantization in PLL and explain one bit phase estimation.
As we know, PLLs are widely used in tracking systems, and they usually have narrow capture range. The characteristic is based on analog PLL. However, even though ADPLL had been investigated, their capture range is still limited. Next, we will study how to use ADPLL to achieve ultra-wide capture range.
Chapter 3.
One Bit Quantized Digital PLL in Noiseless Environment
As we know, most of the PLLs work in a limited capture range. Take the popular PLL IC CD4046B for example; its capture range is about 10% of the natural frequency. In this chapter, we focus on the capture range and propose a new method to reach an ultra-wide capture range in one-bit quantized PLL. The work is done without any prior information about input signal frequency.
3.1. Frequency detection
By definition, the phase error of PLL is zero or constant when in lock, and the frequency of input signal and output signal (of NCO) are the same as well. Here, we discuss the method to adjust the NCO frequency so as to lock the input signal frequency.
Phase
Fig. 3.1 One bit quantized digital PLL in details.
The signals within the one-bit quantized PLL circuit are defined as follows:
The input signal ( ) cos(2s t = π f tc +θ), where f is the carrier frequency and c θ is the initial phase.
The output signals of NCO are cos(2πf to ) and sin(2πf to ), where f is the o NCO output frequency.
T is the sampling period. s
The multiplication of quantized input signal and quantized output signal (cosine branch) is a , where k k =mN+i, i=0,1,...,N−1 and m=0,1, 2,....
The multiplication of quantized input signal and quantized output signal (sine branch) is b , where k k=mN+i, i=0,1,...,N−1 and m=0,1, 2,....
The phase difference (phase error) between input and output signal isφ( )m , given by
( ) sgn[ ( )] [1 ( )] 2
m Q m I m
N
φ = − ⋅π − over [−π π, ]. (3.1)
Ωi( )m is 1
L times of the difference between φ( )m and φ(m−1), where 1 L is the attenuation parameter. In our implement, 1 1
=10
L is taken.
Ωo( )m is the input of NCO.
f is the natural frequency of NCO and n KVCO is the conversion gain. Here we
take fn =10 (K Hz)and KVCO =10 (rad−1).
As we see in Fig. 3.1, there is an algorithm for part A (enclosed by dashed line) to adjust the output frequency to match the input frequency. Note that the range of phase estimation is over [−π π, ] in Eq. (2.16). For better understanding, we illustrate the algorithm graphically as in Fig. 3.2-Fig. 3.4. First, we demonstrate the method as two runners on the playground. We would like to measure which one of the runners is faster or slower, and then adjust the velocity of the runner. Our purpose is to keep the two runners at the same velocity.
In the above case, suppose we can measure the distance between the two runners but can not measure the velocity of them. Besides, the velocity of runner B is adjustable while that of the runner A is fixed. Assume that is runner A and is the runner B whose velocity is adjustable.
Case Ⅰ:
1 t= −T t =T
Starting point
Direction
Fig. 3.2 Graphical illustration of CaseⅠ.
As shown in Fig. 3.2, we observe that the distance between runner A and B at time T is longer than the one at time T-1. It means runner B is slower than runner A.
To keep the two runners at the same pace, we increase the speed of runner B.
Case Ⅱ:
In contrast, as shown in Fig. 3.3, the distance of the two runners at time T is less than that at time T-1. To keep them in the same velocity, we slow down runner B.
t =T
1 t = −T
Starting point
Direction
Fig. 3.3 Graphical illustration of CaseⅡ.
Case Ⅲ:
1 t= −T
t=T
1 t= +T
Starting point
Direction
Fig. 3.4 Graphical conception of CaseⅢ.
In the case of Fig. 3.4, we notice that the distance between the runners is the same at any time. It means that the velocity of the runners is the same, so no modification is made.
Corresponding to Fig. 3.2-Fig. 3.4, we describe the phase-adjustment method in Fig. 3.5-Fig. 3.7. Similarly, the one bit quantized digital PLL can only measure:
1. The phase difference between input signal and NCO output signal at time m, which is presented by φ( )m .
2. The difference between φ( )m and φ(m−1).
In the case of Fig. 3.5-Fig. 3.7, we assume the phase moves counterclockwise and the origin is at phase zero. Besides, the frequency of input signal is fixed and our goal is to adjust the frequency of NCO output signal until it matches input signal. Here, we may regard the input signal as the runner A, and the output signal of NCO as the runner B. The phase of input signal at time T is presented by the distance from the starting point to runner A at time T; the phase of NCO output signal corresponds to runner B. Therefore, the phase error φ( )m is the distance between the two runners at time m. The velocity is referred to the signal frequency. We describe the system again
in these notations.
Case Ⅰ:
In Fig. 3.5, it shows that the phase error at time m (φ( )m ) is larger than the phase error at time m-1 (φ(m−1)). It means the frequency of NCO is lower than the frequency of input signal, so we have to increase the frequency of NCO.
1 t = −m
t=m
(m 1)
φ
−( )m φ
Fig. 3.5 The phase variation with time, where the angle of is the phase of input signal, the angle of is the phase of NCO output signal.
Case Ⅱ:
(m 1)
φ −
1 t = −m ( )m
φ
t=m
Fig. 3.6 The phase variation with time, where the angle of is the phase of input signal , the angle of is the phase of NCO output signal.
In this case, φ( )m is smaller than φ(m−1) as shown in Fig. 3.6. The phenomenon represents that the frequency of NCO output signal is higher than the frequency of input signal. Hence, we decrease the frequency of NCO.
Case Ⅲ:
1 t = +m (m 1)
φ
+( m 1)
φ −
1 t = − m
( )m
φ t = m
Fig. 3.7 The phase variation with time, where the angle of is the phase of input signal, the angle of is the phase of NCO output signal.
In this case, Fig. 3.7 shows that the phase error keeps the same at time m-1, m and m+1. According to the definition of locked state, it means the PLL is in lock.
Thus, we do not have to adjust NCO frequency.
As a result, the operation principle of part A in Fig. 3.1 can be shown as
if φ( )m −φ(m− ≥1) 0 then Ωi( )m ≥ (3.2) 0, if φ( )m −φ(m− <1) 0 then Ωi( )m < (3.3) 0.
If Ωi( )m ≥ , the frequency of NCO will be slightly increased after 0 Ωi( )m passes through an accumulator which is made for a finer resolution. On the contrary, if Ωi( )m < , the frequency of NCO will be slightly decreased. Besides, there is a 0 limitation onφ( )m −φ(m−1). To distinguish the polarity of φ( )m −φ(m−1), we have to limit φ( )m −φ(m−1)over[−π π, ]. In other words, we have to revise Eq. (3.2)-(3.3) as
if 0≤φ( )m −φ(m− <1) π then Ωi( )m ≥ 0, (3.4) if − ≤π φ( )m −φ(m− <1) 0 then Ωi( )m < 0. (3.5) However, becauseφ( )m is over [−π π, ], therefore φ( )m −φ(m−1) may have problems when the adjacent φ( ) and (m φ m−1)cross the boundary. Thus, we modify the value ofφ( )m −φ(m−1)if it is out of [−π π, ]. The modifications are
if −2π φ≤ ( )m −φ(m− < −1) π
then φ( )m −φ(m− =1) φ( )m −φ(m− +1) 2π, (3.6) and
if π φ< ( )m −φ(m− ≤1) 2π
then φ( )m −φ(m− =1) φ( )m −φ(m− −1) 2π. (3.7)
3.2. Analysis of one bit digital quantized PLL with ultra-wide capture range
f
o( f
c)
min( Hz ) Capture range 10K
50
Fig. 3.8 The expected capture range of the thesis.
In the thesis, we would like to implement a one bit quantized digital PLL with ultra-wide capture range. Specifically, our purpose is to obtain the capture range to be over 90% of the natural frequency.
As shown in Fig. 3.8, f is the input frequency we would like to track, c f is o the NCO output frequency and the initial value of f is 10K Hz. In our system, o f o can track f without any prior information about c f and c f could be any value c
The tracking procedure of our system is mainly separated into two steps:
Step 1. Information collection:
The frequency detection φ( )m −φ(m−1) is not always accurate, so in the beginning we run the one bit quantized digital PLL many cycles (in our case, we take 200 cycles) without changing the output frequency f . The average frequency o deviation of the first 200 cycles will be much more accurate.
Step 2. Fine frequency adjustment:
After step 1, we obtain an estimate of φ( )m −φ(m−1). Then we take the advantage of digital PLL, which transfers the output frequency f from 10K Hz to o around f at once. In other words, c f is near o f at the 201st cycle. Thus, we can c use the method in Section 3.1 to slightly adjust NCO output frequency until f is in o lock with f . c
Parameter determination:
A. Sampling frequency:
The sampling frequency f is the inverse of sampling period s T . We take s f s as about 320K Hz, for a fine resolution of initial f . o
B. Accumulate N times in the beginning:
The value N is adaptive for different input and output frequency variation.
However, we take N as a fixed value for the first 200 cycles mentioned in step 1. The followings are the process of the determination of N.
In our system, the first phase difference is shown as
(1) 1 2 ( ) 2 fo f NTc s
φ = ⋅ π − + , θ (3.8)
which contains the average phase detection from t=T to t=s NT and the initial phase s difference θ . The second phase difference is
(2) 1 2 ( ) (1) experiment. The result may cause a serious error in phase estimation. To avoid the problem, we take N as
In our implementation, if N is an even number, a serious problem may happen, that is, φ
( 1)
sgn[ ( ) 0] 0, ( )
+ −
=
= = =mN
∑
N kk mN
Q m where Q m b . (3.13) Therefore, we take N as the maximum odd number of Eq. 3.12 in the simulation.
C. 200 cycles of information collection:
We would like to make sure that the number of sampling is sufficient for detecting the phase. At least, the total sampling time has to reach almost one period of every signal. The step makes sure that we can collect the phase information of four quadrants in every signal. In our case, the lowest possible frequency is 50 Hz, so we take 200 times information collection to confirm that we still have enough frequency variation information even if the frequency is only 50Hz. From Eq. (3.12).
( )
min2πNTs× fc ×200≈2π . (3.14)
3.3. The tracking procedure
In this section, we will discuss the whole process of one bit quantized digital PLL, including details of every parameter. However, the different input frequency results in the different process. Here, we divide the input frequency into three parts and discuss the process of each situation.
Note that the following discussion is based on the assumption of f =10K Hz o and fs ≈320K Hz
A. Middle input frequency ragne
f
o( Hz )
f
c10K
50
270 8k
Fig. 3.9 General range of middle input frequency.
The range of middle input frequency is shown in Fig. 3.9, which is about 270 Hz to 8K Hz . The method we deal with middle input frequency is as mentioned in the beginning of Section 3.2.
Step 1. Information collection
The function of step 1 has been introduced previously, so we directly take N=25 by Eq. (3.11). The concept can be illustrated graphically in Fig. 3.10.
As shown in Fig. 3.10, we observe that the output frequency is unchanged when m=1~199. In the period, the system keeps accumulating φ( )m −φ(m−1). Until m=200, we finish our last accumulation and measure an accurate value of ∆f . We employ ∆f in Eq. 3.15 as the input of NCO. After adjusted, the output frequencyf o is quite close to the input frequency f , where c
200
Fig. 3.10 The block diagram when m=1~200.
Phase
Fig. 3.11 The block diagram when m>200.
Step 2. Fine frequency adjustment:
Starting from m=201, the system enters another state which is one bit quantized digital PLL with narrow capture range as shown in Fig. 3.11. One parameter which we have to emphasize is N. Now, f is quite close too f , so we do not have to worry c about the limitation of φ( )m −φ(m−1). As a consequence, we take N=1001 to achieve a much finer resolution and assure the sampling time in one cycle is sufficient for phase estimation.
Fig. 3.12 Expected outcome with middle input frequency.
As shown in Fig. 3.12, the ideal outcome should graphically be similar to the figure.
B. Lower input frequency range
f
o( Hz )
f
c10K
50
270
Fig. 3.13 General range of middle input frequency.
In this case, the range of lower input frequency as shown in Fig. 3.13 is around 50Hz to 270 Hz. The process of tracking the lower input frequency is quite similar to part A of Section 3.3.
Step 1. Information collection
As shown in Fig. 3.10, we observe that the output frequency is unchanged when m=1~199. In the period, the system keeps accumulating φ( )m −φ(m−1).
Until m=200, we obtain an accurate value of ∆f . We use ∆f to be the input of NCO as Fig. 3.10. Afterwards, the output frequency f is very close to the input o frequency f . c
Step 2. Fine frequency adjustment:
Starting from m=201, the system enters another state which is one bit quantized digital PLL with narrow capture range as shown in Fig. 3.11. Still, we have to emphasize the parameter N. Now, f is quite close too f , so we do not need to c consider the limitation of φ( )m −φ(m−1). However, if we take N=1001, the sampling time in one cycle is not sufficient for lower frequency. For instance, assume
the signal of 100 Hz to nearly a period in one cycle. Because the sampling frequency f is about 320K Hz, we have to take almost 3200 times. Obviously, N=1001 is not s
sufficient for lower frequency.
In this case, the parameter N is given by
201
Fig. 3.14 Expected outcome of one bit digital quantized PLL with lower input frequency.
As shown in Fig. 3.14, the ideal outcome should be graphically similar to the figure.
C. Higher input frequency range
f
o( Hz ) f
c10K
50
Fig. 3.15 General range of higher input frequency.
The following discussion is based on the input frequency which is located around 8K Hz to 10K Hz as shown in Fig. 3.15. The process of tracking higher input frequency is mainly split into three parts.
Step 1. Information collection
Repeating the process of step 1 in part A of Section 3.3, we would like to measure an accurate frequency difference between input and output signals. However, with higher input frequency, some problems may occur.
When m=1~200, we take N=25 as usual. It is a coarse resolution for phase estimation. This is also the reason why we have to take an average of phase estimation on the first 200 cycles. Consider the value of φ( )m −φ(m−1), given by
( )m (m 1) 2 (fo f NTc) s over [0, 2 ]
φ −φ − = π − π . (3.17)
A
B
C
Fig. 3.16 Phase diagram of φ( )m −φ(m−1).
For higher input frequency, the value of φ( )m −φ(m−1) is quite small comparing with middle and lower input frequencies. Therefore, we might misjudge
( )m (m 1)
φ −φ − . As shown in Fig. 3.16, the value A is the correct value of ( )m (m 1)
φ −φ − . In the process of estimation, the misjudged value might locate between value B and value C. We take the value B for instance. Note that
system will present, for example, A=0.2π but B=1.8π . If we take the misjudged value into the estimation system, the outcome of ∆f will be erroneous.
Step 2. Information re-collection
Therefore, we set a counter in the first 200 cycles. The counter is to calculate the number of ( )φ m −φ(m− ≤1) 50. Once the number of ( )φ m −φ(m− ≤1) 50 is over 70 within the first 200 cycles, we assume that the outcome of ∆f will not be accurate.
To be more specific, we regard the input frequency as sufficiently high when the number of ( )φ m −φ(m− ≤1) 50 is over 70 within the first 200 cycles. To avoid the mistake, we drop the outcome of ∆f and re-estimate φ( )m −φ(m−1) with longer sampling times in each cycle. In other words, we increase N as follows:
( )m (m 1)=2 (fo 7.8 )K NTs 2
φ −φ − π − < π
10 7.8 1.
⇒ = − − fs
N K K (3.18)
If we modify N as 2 (π fo−8 )K NTs <2π , the value of φ( )m −φ(m−1) might cross the boundary 0 and 2π when fc ≈8 (K Hz) . On the other hand, when fc ≈10K (Hz) , N should be large enough to assure φ( )m −φ(m−1) is sufficient. To satisfy the tradeoff, we take N with Eq. (3.18).
Besides, in the re-estimate part, we do not need 200 cycles to estimate ( )m (m 1)
φ −φ − because we have already known that input frequency is sufficient
high. In other words,
( )
fc min in Eq. (3.14) is sufficient large. Therefore, we take 100 cycles to estimate φ( )m −φ(m−1) in this case. The re-estimate part is graphically depicted in Fig. 3.17.In Fig. 3.17, we observe that the output frequency is still fixed as original value when m=201~299. In the period, the system keeps accumulatingφ( )m −φ(m−1) and
estimate ∆f ' as
When m=300, we finish our last accumulation and measure an accurate value of '
∆f . We employ ∆f ' as the input of NCO. After adjusted, the output frequencyf o is quite close to input frequency f . c
In summary, there are two advantages to increase N in Step 2:
1. Get finer resolution: decrease the range of misjudging.
2. Keep the value of φ( )m −φ(m−1) away from the boundary 0 and 2π .
Fig. 3.17 The block diagram when m=201~300.
Step 3. Fine frequency adjustment:
The block diagram is shown in Fig. 3.11. The only parameter we revise here is that the block diagram occurs when m>300. Starting from m=301, the system is in another state which is one bit quantized digital PLL with narrow capture range. In the period, we take N=1001 for the same reason as before. After a few adjustments, the output frequency is supposed to be in lock with input frequency. As shown in Fig.
3.18, the ideal outcome should be graphically similar to the figure.
cycles
Fig. 3.18 Expected outcome of one bit quantized digital PLL with higher input frequency.
D. Summary
Fig. 3.19 is the flowchart of distinguishing f in the first 200 cycles. Define c : number of cycles
m ,
: number of samples in each cycle
N ,
counter: numbe of r φ( )m −φ(m− ≤1) 50 within the first 200 cycles.
10 , 320 .
o s
f K Hz
f K Hz
=
≈
counter<70
201
13 1001
16( )
s o
N f
f
= >
Yes
No
No
Yes
when m=201
lower f
cmiddle f
chigher f
cFig. 3.19 Flowchart of distinguishing input frequency
After distinguishing the input frequency during the first 200 cycles, we start the process of fine frequency adjustment. Finally, we achieve the one bit quantized digital PLL with ultra-wide capture range.
3.4. Simulation Results
We simulate the system with MATLAB. The followings are simulation results of the one bit quantized digital PLL.
A. Middle input frequency range
Here we illustrate the tracking process for four values of f over middle c frequency range and show the NCO output frequency at a specific cycle where X is the number of cycles and Y means the value of NCO output frequency in Hz.
0 500 1000 1500 2000 2500 3000
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
f o(Hz)
number of cycles fc = 7800(Hz)
X: 201 Y: 7793 X: 200 Y: 1e+004
X: 2001 Y: 7800 X: 1
Y: 1e+004
Fig. 3.20 The locking process of f 7800 Hz. c
0 500 1000 1500 2000 2500 3000
0 500 1000 1500 2000 2500 3000
0
0 500 1000 1500 2000 2500 3000 0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
X: 200 Y: 1e+004
f o(Hz)
number of cycles fc = 770(Hz)
X: 201 Y: 761 X: 1
Y: 1e+004
X: 2001 Y: 769.9
Fig. 3.23 The locking process of f 770 Hz. c
B. Lower input frequency range
Here, we depict the locking procedure for four values of f over lower c frequency range and show the output frequency at a specific cycle where X is the number of cycles and Y means the value of NCO output frequency in Hz.
0 500 1000 1500 2000 2500 3000
0 500 1000 1500 2000 2500 3000
0
0 500 1000 1500 2000 2500 3000
0 500 1000 1500 2000 2500 3000
0
C. Higher input frequency range
We illustrate the tracking process for four values of f over higher frequency c and show the output frequency specifically at a specific cycle.
0 500 1000 1500 2000 2500 3000
9960 9965 9970 9975 9980 9985 9990 9995 10000 X: 1 Y: 1e+004
f o(Hz)
number of cycles fc = 9999(Hz)
X: 300 Y: 1e+004
X: 2222 Y: 9999
X: 301 Y: 9964
Fig. 3.28 The locking process of f 9999 Hz. c
0 500 1000 1500 2000 2500 3000
0 500 1000 1500 2000 2500 3000
5000
0 500 1000 1500 2000 2500 3000
D. Simulation results of a ultra-wide capture range
Finally, we observe the locking results of a wide input frequency range. Instead of showing the locking process, we define that if the final value of f is located o within [fc−1,fc+ when m=3000, the system is called “locked”. We just have to 1]
observe the value of f at m=3000, and then we can determine whether the system o is in-lock or not.
We increase f logarithmically from 50 Hz to 9976 Hz in Fig. 3.32. On Y-axis, c Y=1 indicates the system is locked and Y=0 shows the system fails to lock. As we see, our design can lock all the frequencies from 50 Hz to 9976 Hz successfully in noiseless environment.
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5
0 0.5 1 1.5
X: 50 Y: 1
fc (Hz)
1:in-locked 0:not in-locked
Locked situation in noiseless environment
X: 9976 Y: 1
Fig. 3.32 Locked situation in noiseless environment.
3.5. Summary
In this chapter, we propose methods to deal with different input frequency signals and then demonstrate one bit quantized digital PLL with ultra-wide capture range. In the process, the number N is quite important for either the resolution or the error of phase estimation. Therefore, we modify N to fit different situations. The unique features of our system are:
1. f is an unknown frequency over [50 Hz, 10K Hz]. c
2. In noiseless environment, the system achieves almost 99.5% capture range of the natural frequency.
The outcomes of simulation justify our design in noiseless environment.
Chapter 4.
Noise effect
It is known that most of the PLL systems would be affected by noise in reality. In this chapter, we analyze the performance of one bit quantized digital PLL in noisy environment. Our discussion is based on the simulation outcomes of different signal-to-noise ratio (SNR) in dB. We use additive white Gaussian noise (AWGN) to simulate the noise affect in our system.
4.1. Overview
The model of one bit quantized digital PLL with noise is the same as that in Chapter 3. The only change is the input signal s t( ), given by
( ) cos(2 c ) ( )
s t = πf t+θ +n t , (4.1)
where n t( ) is the additive white Gaussian noise.
In addition, we relax the setting of determining whether the system is in-locked
In addition, we relax the setting of determining whether the system is in-locked