Chapter 4 Architecture Design and Hardware Reduction
4.5 RTL and Gate Level Simulation Results
4.5.2 Synthesis and Simulation Results
The synthesis results are listed in Table 4-5. The process is TSMC 65 nm 1P9M at 1.2 V and the system required sampling rate of IEEE 802.15.3c is 1728 MHz. The synthesis tool is Synopsys Design Compiler and design constrains set the operation speed at 216 MHz. The area report comes from the Design Complier, and the power consumption report is from the Prime Power. The maximum power consumption appears at data transmission stage since the whole circuit executes the functions of equalization and adaptive algorithm. The maximum power consumption of main functional units is listed in Table 4-6. The gate-level simulation result is shown in Fig.
4-9, which shows that it can achieve the criterion at Eb/N0 of 10 dB under the channel model mentioned in Section 2.2.
Table 4-5 Synthesis result of the proposed FDE
Process TSMC 65 nm 1P9M (1.2V)
Clock rate 216 MHz
Gate count (including memory) 504k
Power 81.87 mW
Memory
(generated by memory compiler)
ROM: 64 × 144 RAM: 64 × 64
Table 4-6 Power consumption percentage of each functional unit
Total 81.87 mW (100%)
Complex multiplier 36.51 mW (44.6%)
Memory 12.53 mW (15.3%)
Others 32.83 mW (40.1%)
0 1 2 3 4 5 6 7 8 9 10 11 12 10-5
10-4 10-3 10-2 10-1 100
Eb/N0(dB)
BER
AWGN pi/2 BPSK pi/2 QPSK pi/2 BPSK, RTL pi/2 QPSK, RTL
Fig. 4-9 BER vs. Eb/N0 of RTL simulation
The related work can be found in [19]. In [19], the channel model is NLOS residential model with 6.26 ns RMS delay spread. Other non-ideal effects include nonlinear power amplifier and phase noise. Compared with [19], we choose the LS-LMS combined algorithm instead of MMSE. The difficulty of realizing MMSE is the information of noise variance. In [19], the noise variance is assumed well known.
Since we take hardware design into account, only the realizable algorithm is in our consideration. Furthermore, our channel model includes Doppler Effect to simulate the time-variant channel effect. The comparisons between the proposed FDE and related work in [19] are listed in Table 4-7.
Table 4-7 Comparisons between the proposed FDE and related work
Proposed [19]
Sampling rate 1728 MHz 1728 MHz
Modulation π/2 BPSK, π/2 QPSK QPSK,8PSK
Channel model LOS residual model[14]
RMS delay spread: 12.73 ns
NLOS residential model [14]
RMS delay spread =6.26 ns
Non-ideal effects Doppler Effect Nonlinear power amplifier and phase noise
Synchronization Perfect Perfect
Equalization LS-LMS FDE MMSE FDE
FEC No Reed-Solomon coding
RS (255, 239, 23) Eb/N0 at 1.54*10-4
BER
10 dB 10 dB
Chapter 5 Conclusion and Future Work
We propose a fast convergent adaptive FDE that can satisfy the specification of IEEE 802.15.3c SC mode. The proposed FDE combines LMS adaptive algorithm with LS channel estimation. The LMS algorithm has the advantage of low computational complexity and sufficient convergence speed with the aid of LS channel estimation.
The proposed FDE can overcome the multi-path fading channel and Doppler Effect.
The required Eb/N0 is 10dB to achieve the criterion of 1.54*10-4 BER, and we have built both floating- and fixed-point behavior models in C language.
In RTL design, we reduce the division required by LS. The division circuit is replaced with a table lookup scheme, which mainly uses the pre-stored information.
By using the data behavior of inverse, truncating the LSB and doing shifting can successfully reduce the size of the table down to 0.01%. The hardware resources between LMS and LS are also reduced by using the hardware sharing technique. The area of the related complex multipliers and register file are 47% and 44% off respectively, and the total area reduction is 38%. To achieve the sampling rate of 1728 MHz, we use both pipeline and parallel structure. The design is 8 times parallel with the clock rate of 216 MHz. The total gate count after the synthesis is 504k (excluding FFT/IFFT). With two modulation schemes, π/2 BPSK and π/2 QPSK, the data rate can be up to 2.9 Gbps. We also design the proposed FDE with Verilog HDL and the simulation result shows that the proposed FDE can achieve the 1.54*10-4 BER (uncoded) at 10 dB of SNR.
In the future, we will consider the modifications on the algorithm to deal with the effects of inter-carrier-interference (ICI) and the reduction of FFT blocks.
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