Chapter 4 ECG System-on-Chip Design
4.3 System Control
The system control unit (SCU) is responsible for initialization of the system, decoding of the current configuration, and generating control signals decoded from the current configuration to corresponding modules. The ECG SOC receives configurations from a remote station via the UART interface to startup the system. In addition, a trigger signal is employed to enable a manual start so that the system can reset to a default mode without the need of configuration commands from the remote station. The command packet and corresponding configurations are shown in Figure 4.3.
Figure 4.3 Command packet and corresponding configuration
After receiving a configuration command, the SCU decodes the command and if system re-configuration is required issues an internal reset to all modules. The system then restarts with the new control signals and the configuration is loaded. The control flow diagram of the SCU is shown in Figure 4.4.
Figure 4.4 System control flow diagram 4.4 HRV Processor
A VLSI hardware implementation of an HRV processor that is power efficient and analytical accurate has been presented in this thesis. The architecture of the HRV engine was discussed in Chapter 2 and the overall architecture is shown in Figure 4.5(a). The HRV processor is implemented The HRV engine performs time-frequency HRV analysis on a heart rate window of two minutes with fifty percent overlap. Spectral analysis using the Lomb periodogram is calculated using a novel low area fixed-point hardware design.
The HRV processor can operate in various modes, shown in Figure 4.5(b), and has gated clocks to turn off the processor when HRV calculation is not performed. The proposed HRV engine is cost-effective in obtaining accurate time-frequency domain HRV analysis without the need for microprocessors or software on remote stations.
4.5 Compression Engine
It is well-known that wireless data communication takes up a large share of the total power consumption in most portable wireless devices or systems, with power dissipation proportional to the amount of data transferred.
With the energy consumption of today’s wireless transceivers ranging between 0.6 nJ/bit to 75 nJ/bit depending on modulation scheme, protocol, data rate and transmitter power output [59,60], data compression performed in a submicron technology domain is expected to result in overall power savings. For example, a microcontroller-based lossy
(a)
(b)
Figure 4.5 (a) Architecture of the HRV processor (b) Top level module view of the HRV processor
compressor [61] can already achieve an energy consumption of 31 pJ/bit, which is an order of magnitude lower. For our ECG processor, a lossless compression technique was chosen instead of lossy in order to avoid the possibility of losing ECG artifacts of potential diagnostic value.
The architecture of the compression engine, shown in Figure 4.6, comprises a precision adjust unit, a context determiner, a differential pulse code modulation (DPCM) predictor, a context-based k-parameter estimator, a prediction memory array (3ch ECG), a set of context variable upkeep modules, a remap to unsigned unit, a Golomb-Rice entropy coder and a 40-bit multi-stream packer/multiplexer. To enhance the compression performance, each ECG sample was classified according to a context rule based on a finite number of previous samples[62], with the Golomb-Rice k-parameter estimated for each context and particular sample. To minimize area and latency, the need for sample buffers was eliminated by employing an adaptive k-parameter estimation algorithm [63]. The compression unit also accepts RR interval and HRV coefficient data, which, together with compressed or raw ECG data are packetized and multiplexed onto a single data stream.
Figure 4.6 Architecture of the lossless compression engine
Table 4-2 shows the specifications of the compression engine compared to previous works.
Table 4-2 Specifications of the Compression Engine
Parameters This work [64]
Compression Ratio 2.50 1.70
Technology 90nm CMOS 90nm CMOS
4.6 Wireless Communication
As the UART standard is used for output of data, many forms of communication protocols can be utilized. Through UART, the system can be interfaced with a wireless chip solution, a PC, or any other device with UART. To verify the capabilities of various output methods, wireless transmission using the IEEE 802.15.4 standard as well as the Bluetooth standard were implemented in this study.
The IEEE 802.15.4 is a standard which specifies the physical layer and media access control for low-rate wireless personal area networks and is the basis for protocols such as ZigBee. In this thesis, a Jennic-JN5121 chipset was used for development of the IEEE802.15.4 compliant wireless protocol. The IEEE802.15.4 compliant module is shown in Figure 4.7.
Figure 4.7 Photo of the IEEE802.15.4 wireless module
In IEEE802.15.4 the physical medium is accessed through a CSMA/CA protocol where nodes wait until the channel is clear before transmitting data. If packet collision occurs, a back-off time is allotted before data resend is attempted. In cases where there are multiple nodes this will result in a constant resending of packets which in turn will increase power consumption. To avoid packet collision, and thus reduce power consumption from re-transmission, a round-robin scheme is employed. In the round-robin scheme the wireless coordinator activates each registered node in rotation. A node can only send data if it is activated and after a pre-configured amount of time will revert back to an idle state. This ensures that only one node will transmit at a time. A diagram of the round-robin scheme is shown in Figure 4.8.
Figure 4.8 The flow of the round-robin scheme
For validation of the use of Bluetooth with the proposed system, a module using CSR BlueCore4-External single chip Bluetooth system was used. Bluetooth is a wireless technology standard for exchanging data over short distances from fixed and mobile devices. Bluetooth is a packet-based protocol with a master-slave structure also using a
round-robin scheme. Through the use of the SPP profile of Bluetooth, the proposed system can wirelessly transmit data using Bluetooth via UART. The Bluetooth module is shown in Figure 4.9.
Figure 4.9 Photo of the Bluetooth module
A comparison of IEEE802.15.4 and Bluetooth wireless standards is shown in Table 4-3. In our studies, the IEEE802.15.4 wireless standard demonstrated more flexible system configurations. However, in cases of large numbers of connecting nodes, the communication protocol would need re-evaluation in consideration of limited bandwidth and packet collision. The ubiquity of devices with Bluetooth standard is a prospective advantage; however, the one-to-one characteristics of Bluetooth might also introduce problems with mass multiple connections.
Table 4-3 Comparison of Bluetooth and IEEE802.15.4
Parameters Bluetooth
IEEE802.15.4 (ZigBee)
Operating Frequency 2.4 GHz 2.4 GHz
Modulation Technique Frequency Hopping Spread Spectrum
Direct Sequence Spread Spectrum
Transmission rate (kbit/s) 1000 250
Range 10-100 meters 10-100 meters
Typical network join time 3 seconds 30 milliseconds
Power Consumption Medium Low
4.7 System Verification
An SOC development platform from Socle Technology was initially used to verify the system blocks. The SOC development platform provides an ARM926EJ-S processor and various peripheral modules, including a Xilinx FPGA, which are connected to the ARM processor through an AMBA High-performance Bus (AHB). The designed HRV processer was implemented on the FPGA and verified with patterns sent from a PC.
In-circuit emulator (ICE) was used to feed ECG patterns into the ARM processor which then passed the data to the FPGA on the AHB bus. To connect the HRV processor on the FPGA to the AHB bus, an AHB wrapper was added to the original architecture. The AHB wrapper provides a handshaking interface between the HRV processor and the AHB bus.
The UART module was also implemented so that the capability to communicate with the Bluetooth module using a system clock of 24 MHz could be verified. The setup of FPGA verification is shown in Figure 4.10.
Figure 4.10 Verification of the HRV processor on FPGA
Tests using the Socle Development Platform have verified that the HRV processor is capable of calculating time-frequency analysis in real-time and is possible to
implement using VLSI technology. Results also show that the UART module was successful in communicating with the IEEE802.15.4 module, Bluetooth module, as well as a PC using RS-232. Wireless transmission with the Bluetooth module was enabled for a prolonged time to check for possible data-loss during transmission. Final results have verified that the FPGA system can effectively operate and send data without data-loss.
Chapter 5 Chip Implementation
5.1 Chip Tape-out
The ECG System-on-Chip design proposed in Chapter 4 is scheduled for tape-out under UMC 90nm SPHVT 1.0V 1P9M process technology. To reduce static power consumption, the chip has been implemented using high Vt process (HVT) library. The floorplan and I/O plan of the chip is shown in Figure 5.1. The total number of pads is 36, with 14 power pads and 22 logic pads.
Figure 5.1 Floorplan and I/O plan
Table 5-1 Description of the I/O Pads
Input Pins Bits Function
CLK 1 System clock signal
RESET 1 System reset signal
MANUAL_START 1 Start the system in default mode
ADC_EOC 1 End of conversion from ADC
ADC_DATA 10 Converted data from ADC
RX 1 UART receive port
Output Pins Bits Function
AIC_CLK10K 1 10KHz clock to ADC
AIC_CLK1200K 1 1.2MHz clock to ADC
ADC_RESET 1 Reset signal to the ADC
ADC_START_CONVERSION 1 Start ADC conversion
ADC_CHSEL 2 ADC Channel select
0: Lead I 1: Lead II 2: Lead III 3: Unused
TX 1 UART transmit port
Figure 5.2 Chip layout of the ECG SOC with on-board HRV processor
Figure 5.2 shows the layout of the chip. The die size is 800µm by 800µm, and the core size is 512µm by 512 µm. The gate count of chip is 93701. A total 3.2KB of SRAM is used on the chip. The working system clock frequency is 24MHz. By using HVT library, a reduction of 31% in total power consumption was achieved compared to RVT library. The overall power consumption of the chip is 523µW as simulated with Synopsys Prime Power. The details of the chip are shown in Table 5-2.
Table 5-2 Summary of the ECG SOC Chip Design
Parameters Value
Technology Process UMC 90nm SP_HVT Process 1.0V
Die size 800µm x 800µm
5.2 Setup of the Integrated ECG Health-Care System
The fabricated ECG SOC will be applied to the prototype of an integrated ECG health-care system. The integrated ECG system includes front-end circuits for amplification and filtering of three channel ECG signals. As the ECG is a bioelectric signal, its amplitude is relatively small and easily corrupted by noise. Therefore an instrumentation amplifier (IA) is used in the front-end circuits to amplify the ECG signal at the first section. Next the signal is filtered using a notch filter with cut-off frequency of 60Hz for rejection of power-line interference. Then a high-pass and low-pass filter limits the ECG signal to 0.05Hz and 150Hz before another IA amplifies the final output signal.
The schematic of the front-end circuits is shown in Figure 5.3. After the front-end circuits there is an analog mux and 10-bit ADC that can be controlled by the ECG SOC for acquisition of ECG data. Finally a Bluetooth module is included to transmit data to a remote base station.
The integrated ECG system prototype will be implemented on a printed circuit board (PCB) using direct chip attachment (DCA) to bond the fabricated ECG SOC die directly to the PCB. The setup of the system is shown in Figure 5.4.
Figure 5.3 Circuit schematic of the front-end sensor circuit
Figure 5.4 Setup of the integrated ECG system using the proposed ECG SOC
Chapter 6 Conclusion and Future Work
6.1 Conclusion
In light of the aging population, healthcare systems designed for portable and at-home applications can alleviate the problems of caring for a growing number of elderly patients. Such medical devices can also assist in maintaining a healthy condition of the general population. In this thesis, a design of a low area and low power ECG system-on-chip for applications in portable biomedical devices is proposed. The ECG SOC can acquire three-channel ECG data from external front-end circuits through an ADC controller. A lossless compression engine with compression ratio of 2.5 is employed before data is sent by wireless transmission through a Bluetooth module. An on-board HRV processor is able to perform time-frequency analysis of HRV according to user configurations. The proposed system is well integrated and is configurable through remote commands or a trigger signal. Through the use of a common interface standard, UART, the system is able to easily connect with other modules or ICs increasing the compatibility and robustness of the design. The ECG SOC has been verified on FPGA and implemented using UMC 90nm SPHVT 1.0V 1P9M process technology.
In portable applications, the tradeoff between system complexity and device size is often an important issue. However, VLSI design can help in the implementation of an architecture that has high analysis capability and yet is small in device size. The design and implementation of the ECG SOC proposed in this thesis demonstrates the possibility of an SOC solution for portable medical devices that can benefit doctors, patients, and researchers.
6.2 Future Work
The features of the ECG are also important indicator for the diagnosis of many diseases. For example, the absence of the P wave may indicate cases of atrial fibrillation.
The accurate detection of all points and waves of the ECG is therefore also an important function. To provide more information to the end-user, the study of an area and power efficient automatic method for detection and classification of the ECG waveform is of great benefit.
In terms of architecture design for VLSI implementation, further power and cost efficiency can be achieved by integration of front-end circuits, SOC, and wireless transmission through use of system-in-package (SIP) technology or mixed-signal IC design. The HRV processor can also serve as a processing unit in a multi-biomedical signal system [65] for uses in ICU.
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