Distribution
Due to the complexity, thermal analysis takes high challenges nowadays and hence it is not easy to take account of thermal effects during placement process. The current thermal models, such as finite element method (FEM) [30], finite difference method (FDM) [31] and compact resistive network [32][33], are accurate but they take minutes to analyze a design. As we know, many placement methods are iterative processes. If it takes minutes to analyze a placement for each iteration, the lack of efficiency causes the great amount of runtime. Moreover, as the technology advancing, the number of transistors in a design grows exponentially and hence problem size increases. Therefore, the demands for fast and accurate enough thermal-aware placement methods exist. We find some guidelines from temperature observations with block distribution and take them into consideration during placement process. It is helpful to simplify thermal problems and still fast enough. In this chapter, first the thermal model we used is introduced. Then the temperature observations are shown with different types of block distribution.
3.1 Thermal Model
Figure 7 illustrates a typical single-chip package used by a well-known thermal model named Hotspot [32][33]. Silicon die represents the active silicon device layer and the thermal interface material layer is used to increase the efficiency and
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uniformity of thermal transfer. Heat spreader and heat sink exhaust most of the heat.
Heat generated from the active silicon device layer is delivered from the silicon die to the heat sink, and then removed to the ambient air.
According to design geometries and material physical properties, Hotspot employs thermal-electrical duality to model thermal effects at the functional block level. As shown in Figure 8, current sources (I) represent power sources (P);
resistances (R) represent thermal resistances (Rth); ground represents ambient air;
voltage difference (ΔV) represents temperature difference (ΔT). The formulation of Ohm’s law for temperature is shown in (1). In Hotspot, the chip is divided into grids for analyzing thermal problems, that is, grid-based (as shown in Figure 9). The grids have different magnitude of power due to the characteristics.
ΔV = I × R ΔT = P × Rth (1)
Ambient Air
Heat Sink Heat Spreader Thermal Interface
Material
Silicon Die
Power Sources
Figure 7. A typical single-chip package.
Power source as current source
Thermal resistance as resistance
Ambient air as ground
Figure 8. Thermal-electrical duality.
3D FPGAs has some features which can help building thermal model. First, architectural regularity of 3D FPGAs can match the grid-based characteristic for thermal analysis by dividing into grids based on CLBs. Second, the behavior inside a CLB is unknown and the two situations that can be observed from outside are occupied and unused. Therefore, occupied CLB can be denoted as holding current source and unused CLB can be denoted as open circuit. That is, the power of a CLB only has two types of magnitude. Due to the two features, the thermal problems can be treated as spatial block distributional problem.
3.2 The Influence of Patterns on Temperature
The pattern represents the planar block distribution. In this subsection, the effects of different patterns on temperature are observed. Five patterns are performed in two sizes which are 10 × 10 × 4 and 40 × 40 × 4. The utilization of all patterns is fixed to 50%. The five patterns are described as follows. i) Corner pattern – all blocks are placed on one of the corners on the chip. ii) L-shaped pattern – all blocks are placed on two sides of the chip. iii) Ring pattern – all blocks are placed on the periphery of the chip. iv) Center pattern – all blocks are placed in the center of the chip. v) Chessboard pattern – all blocks are placed evenly on the chip. The maximum temperature and temperature deviation of patterns are shown in Table 1.
Grid-Based
Figure 9. Grid-based model.
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As shown in Table 1, in smaller size, corner and L-shaped patterns have higher maximum temperature and temperature deviation; however, ring, center and chessboard patterns have lower ones. While the size is larger, the maximum temperature and temperature deviation of ring and center pattern are as high as those of corner and L-shaped pattern. However, chessboard pattern still has the lowest maximum temperature and temperature deviation. Therefore, the first guideline is to assign blocks more evenly helps alleviating thermal problems.
3.3 The Influence of Utilization on Temperature
The vertical block distribution is called utilization in different layers. Because the lengths of heat dissipation path for layers are different, the utilization in layers should not be identical for better temperature profile (i.e. maximum temperature, temperature deviation and maximum temperature gradient). Different types of utilization in layers are performed as shown in Figure 10. The dimensions of the architecture are 40 × 40 × 4 and total utilization is fixed to 65%. Chessboard pattern
Table 1
is applied for each layer because of better temperature profile. Figure 10(a) shows that each layer uses the same utilization and L4 is the nearest to heat sink. The curve of maximum temperature declines from L1 to L4, that is, the different lengths of dissipation path for layers lead to uneven temperature distribution. Because of the result of Figure 10(a), 1%~2% blocks are moved to L4 from L1~L3 as shown in Figure 10(b). Temperature distribution in Figure 10(b) is more even. However, placing too many blocks in L4 leads to elevated temperature in L4 as shown in Figure 10(c).
Therefore, the second guideline is to place a little more blocks in the top layer, but not too many.
According to the second guideline, the thermal-aware area constraints are proposed for each layer. It is suggested to move 2% blocks from the bottom layer to the top layer at most and 1% blocks from the middle layers to the top layer at most.
Figure 10. Utilization observations.
(b) (c)
(a)
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Besides the top layer, the number of blocks in each layer is no more than blockavg. Using this area constraints, the temperature distribution becomes more even. The area constraint is shown in (2). lbk isdenoted as the lower bound for area constraints of Lk. ubk isdenoted as the upper bound for area constraints of Lk. The values of lbk andubk
are shown in Table 2. ubnz represents the situation for moving the most blocks from L1~Lnz-1 to Lnz.
blockavg × lbk block(k) blockavg × ubk (2)
3.4 The Influence of Vertical Direction Staggers on
Temperature
Another issue for vertical block distribution is the stagger between layers. We want to figure out that whether a block placed right up or down to another block causes hotspots or not. The dimensions of the architecture are 40 × 40 × 4 and total utilization is fixed to 50%. Chessboard pattern is applied for each layer for better temperature profile. Two types of observations are shown in Figure 11. Figure 11(a) is called Z-non-stagger which a block is placed right up or down to another block.
Figure 11(b) is called Z-stagger opposite to Z-non-stagger. The temperature observations are shown in Table 3.
Table 2
Utilization observations.
L1 L2 ... Lnz – 1 Lnz
Lower Bound(lbk) 0.98 0.99 0.99 0.99 1
Upper Bound(ubk) 1 1 1 1 1+0.01nz
Area Constraint
Lk
The maximum temperature and temperature deviation of Z-non-stagger and Z-stagger are nearly the same. The reason is that heat sink exhausts most of the heats in vertical direction, which makes the heat dissipation in vertical direction much easier than the one in planar direction. Therefore, the third guideline is that stagger placement in vertical direction affects temperature slightly.
Figure 11. Two types of stagger observations in vertical direction.
(a) Z-non-stagger (b) Z-stagger
Table 3
Stagger observations in vertical direction.
Maximum(oC) Deviation
Z-Non-Stagger 47.81 0.66
Z-Stagger 47.58 0.65
Pattern
Temperature
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