4.1 Introduction
In chapter 3, we realize the killer of gate oxide is plasma. But cannot stop it damage gate oxide. In chapter 2, we find out the gate oxide damage location, and it is on source line diffusion. No matter what dies fail, gate oxide damage location is always in the same place. It is an obviously hint, it is the most weak point on gate oxide. The largest F-N tunneling current is in the place. If a new layout is no the place, and new router will be avoid antenna effect damage. The original layout is source line (P+ diffusion) that crosses with poly-si gate. So we need to make a new mask that source line doesn’t cross over poly-Si gate.
In order to reduce or prevent damage to gate oxide from plasma-based process, and to ensure reliability, a circuit layout rule that considers the antenna effect is employed [1].
The conventional antenna rule restricts a maximum antenna ratio allowed for circuit layout. Recent studies show that the damage increases in proportion to both the area and the perimeter of the antenna. Consequently, the damage induced to the gate oxide terminal Ti can be calculated as follow:
antenna perimeter length ratio of Ti, j∈{poly layer, all the via layer, and all the metal layers}, is a set of j-layer wires, A(x) is the area of pattern x which gate terminals connecting , P(x) is the perimeter length of pattern x, is constant is constant. Using the function, it is proposed that the objective function to be minimized during placement and routing the following form:
Pij
Dmax is the maximum allowable gate-damage value [2][3].
4.2 New Layout and Antenna Ratio
The original layout is as Fig.2-3, source lines (P+ diffusion) connect together by P+
diffusion, and they are like fork. So the poly-si gate crosses with P+ diffusion (source line). The new layout (Fig.4.1) is new router in M1 [4]. Every source line is isolation in P+ diffusion, and they are connected by M2. In this way, it can avoid the poly-silicon cross with P+ diffusion, and make the worst point disappear in the new pattern. The weak point is like a capacitor structure, which is including top plane (poly-silicon gate), bottom plane (P+ diffusion) and dielectric (SiO2). And it is easily trap charges in plasma-base process. If the plasma is no uniform, the ions and electrons could be trap in top plane and bottom plane. It will be develop a high electron field in dielectric (SiO2) by the ions and electrons. When the charges discharge to substrate (P+ diffusion), the energy of charge damage the bond of silicone and oxygen (O=Si=O). And Gate oxide thickness of P+
diffusion area is less then cell area (N diffusion=80nm). So it more worst in the place. If we replace the pattern by new layout, the gate oxide damage problem could be
disappeared.
4.3 Results and Discussion Test condition 1:
VG=10V Ig <100nA
New layout pass ratio: 100%
Original layout pass ratio: 31.25% (Table.5.1) Test condition 2:
Ig=100nA to get VG.
New layout has higher breakdown voltage then original layout. The test result is as table.5.1. The result clear display the advantage of new layout, it improves the gate oxide breakdown voltage. It is 100% pass in the testing. The new layout new router is not only disappear the weak point, the antenna ratio also reduce in M1 (Table.5-2). In this way, we can guaranty gate high yield in WAT test. And what is the fail and pass mechanism.
Fig.4-2 is the band diagram of P+ substrate and N well. When bias is input in gate, the greater band bending in A but B is smoother. The electron A will easily produce Fowler-Nordheim tunneling, but B is too high barrier of gate oxide to tunneling. We always find the gate oxide damage position is in A.
4.3 Summary
In the chapter, we do a experiment of modify layout. The original source lines (P+
diffusion) are all together, like a fork. All source lines are isolation, and router is contacts,
M1, via1 and M2 to connect all source line together. The new layout cancels the position A. The original worst place disappears, and there is no parasitism capacitor that will induce worst Fowler Nordheim tunneling between source line and poly-silicone gate.
There is less leakage current in gate oxide, and it gates higher gate oxide breakdown voltage. And it need not change any process recipe. When it is finish all process until M8, the final test also show that is no any fail die. The new layout has completely solved the important problem antenna effect and damage gate oxide in plasma-base process.
4.4 References
[1] Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen;“Multilevel routing with jumper insertion for antenna avoidance” IEEE International12-15 Sept. 2004 Page(s):63 - 66 [2] h. Shin, C. C. King, C.Hu, “Thin Oxide Damage by plasma etching and ashing process,” Proc. Of IrPS, 1992.
[3] Watanabe, H.; Komori, J.; Higashitani, K.; Sekine, M.; “A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure” IEEE Transactions onVolume 10, Issue 2, May 1997 Page(s):228 - 232
[4] K. P. wang, M. Marek-Sadowska, W. maly, “Layout design for yield and reliability,”
5th ACM SIGDA Physical Design Worshop, 1996.
[5] Krishnan, A.T.; Krishnan, S.; Nicollian, P.; “Impact of gate area on plasma charging damage: the "reverse" antenna effect” 2002. IEDM '02. Digest. International
8-11 Dec. 2002 Page(s):525 - 528