The Proposed 11-b Low-Voltage Low-Power SAR A/D converter

Under the low supply voltage environment (V_thp +V_thn >V_DD), there are many design challenges. For the conventional SAR ADC, there are two problems. First, CMOS switches cannot work efficiently. If input voltage is at the middle of the supply voltage, neither NMOS nor PMOS is unable to turn on. Second, input range is limited to half of the full scale voltage. In order to solve the problem, the novel low-voltage SAR ADC is presented.

The conventional successive approximation algorithm uses a DAC to binary search the input voltage. The proposed algorithm is adds or subtracts by the DAC voltage to binary search V^DD2 . It is shown in Figure 3-5. There are two advantages.

First, it achieves rail-to-rail input range without a rail-to-rail comparator. Second, it adopts a grounded-switches technique. It means all switches are only switched to

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

VDD or V . Thus, it is easy to provide adequately low switch on-resistance. _SS

Figure 3-5 Proposed SAR ADC architecture

3C

Figure 3-6 A 11-bit low-power and low-voltage SAR ADC

Because the front-end amplifier has a 70dB dynamic range (DR), a 11-bit SAR ADC is integrated. It is shown in Figure 3-6. The switch S is bootstrapped. It _h provides a rail-to-rail input range. And the others switches are grounded-switches. The switching operations are controlled by the successive approximation register (SAR).

The whole operation is as follows.

Let N=10, i=0

z Sample mode

„ Sh close

„ S10 →V_DD, S0-S9 →V _SS

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

z Hold mode

„ Sh open

„ test b _N

„ Comparator activated and compared V_DAC with V^DD 2 z Redistribution mode ( i conversion cycle)

„ As clk 0->1

‹ If V_DAC>^VDD₂ , b_N−i=1, b_N−i →V _SS

‹ If V_DAC<V^DD2 , b_N−i=0, b_N−i →V_DD

‹ Comparator reset

‹ i=i+1, test b_N−i →V_DD

The comparator plays an important role in SAR ADC. In order to minimize the power consumption, there is only one current branch in this design. The comparator is shown in Figure 3-7. It includes a preamplifier and a latch. The configuration has three advantages. First, a weak-inversion input pair maximize the

D mI

g ratio.

Second, PMOS input pairs have less flicker noise than NMOS. It is good for low-speed applications. Third, the source and the body of the PMOS is tied together to reduce threshold voltage mismatch and avoid body effect. It also enhances the common-mode immunity and input common-mode range.

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

Figure 3-7 Latched comparator

The operation of the comparator is straightforward. There are two phases of operations. During the “reset” phase, M3 and M4 discharge the output nodes. In the phase, the comparator output is not available. The “compare” phase activates the latch and compares the difference. After settling, the comparator output is available. To determine current and transistor size, the analysis is as follows.

„ In “compare” phase. Given a voltage difference ΔV , the ouptut function of time t is represented as

( )

out t V e

V =Δ ⋅ (3.16)

Let t be the conversion period. The output is required to settle before the time ends. _a

( )

out t V e V

V =Δ ⋅ ^aτ ≥ (3.17)

Where the settling time constant

5

„ In “reset” phase. The transistors M3 and M4 are fully turn on. Their resistance is represented as

Considering the overdrive recovery issue. Assume the comparator is saturated and the

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

clock becomes high at t=0. If there is a input signal ΔV = 12⋅LSB. The output function of time t is derived as

( ) (

)

V_out = ⋅Δ + ⋅ ⋅⎜⎝⎛ − ^−tτ⎟⎠⎞− ⋅ (3.20) Where A is the comparator gain during “reset” phase, I represents the comparator tail current and τ stands for the ouput node time constant. The recovery time is defined by

(

) (

)

In order to minimize the recovery time, it needs a high bandwidth and high gain comparator. However, higher bandwidth means more power consumption. Thus, there is a trade-off between speed and power.

Figure 3-8 Given a input sequence {+0.5VDD, +0.25LSB, +0.5VDD, -0.25LSB, -0.5VDD, +0.25LSB, -0.5VDD, -0.25LSB }, the simulated output sequence={1, 1, 1,

0, 0, 1, 0, 0} under five corner cases (FF, FS, TT, SF, SS). Clock rate=32KHz Thermal Noise

Due to the MOS resistance and parasitic resistance, there is a thermal noise at the DAC output during conversion. The resistive thermal noise can be modeled as a noiseless resistor series with a noise source. Thus, the equivalent model is shown in

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

Figure 3-9 for the MSB conversion cycle. Since MSB capacitor is connected to V_DD and the other capacitors are switched to V , the equivalent capacitance is _SS 2⁹⋅C. Thus, the thermal noise is derived as

Δ

Where K is the Boltzmann constant, T is the absolute temperature, and Δ represents a LSB.

Figure 3-9 Thermal noise models as testing MSB

(

)

2 1

vn vn²2

VDAC

Figure 3-10 Thermal noise models during the next conversion after MSB

Δ

⋅C <

KT

384 (3.24)

In next conversion cycle, the thermal noise is modeled as shown in Figure 3-10.

It shows the capacitance requirement is looser than the MSB. Thus, the thermal noise power is largest during MSB conversion. If it satisfies the requirement, the other bit

Chapter 3 Fundamentals of Low-Voltage Low-Power SAR ADC

conversions will satisfy as well. In general, the thermal noise power should be less than the quantization noise power. Therefore, the unit-capacitance is known.

Voltage multiplier

For a low power supply, the conventional CMOS sampling switch is unable to offer adequate low switch-on resistance. In order to achieve the rail-to-rail input range, the bootstrapped technique is adopted. The sampling switch is implemented as NMOS switch. It is driven by the boosted clock driver shown in Figure 3-11. By the source and gate cross-coupled of M1 and M2 configuration, the capacitor C1 and C2 are charged alternatively. In steady state, the voltage drop across the capacitor C1 and C2 is V_DD. When the input clock becomes high, the output voltage is boosted to 2V_DD. As the clock is low, M4 is turned on and the output is pull down to V . Actually, the _SS boosted output voltage cannot reach 2V_DD for the parasitic effect and charge sharing.

In order to reduce the effect, capacitor C1 and C2 must be sufficiently large. Thanks for the light loading of the small sampling switch and the low speed clock rate, the power consumption of the boosted clock driver is as low as ten nano-watt of magnitude.

C1 C2

clock

M1 M2

M3

M4

DD out V

VDD

⋅ 2 VDD

Figure 3-11 Boosted clock driver