Chapter 2 Theory of ISFET
2.2 Theory for the pH sensitivity of Multi-layer ISFET
After discussions of single layer ISFET, we realize the relation between the electrolyte solution and the sensing layer. However, different layers under sensing layer are another factors. According to C. G. Jacobson’s paper [9], the entire theory of Multi-layer ISFETs could be explained.
The standard ISFET includes an intermediate gate formed by one or more
conducting layers, like aluminum, polysilicon, titanium and platinum. Fig. 2-2 [9]
shows the layers considered in the model that correspond to a vertical cut along the sensing area shown in Fig. 2-3 [9].
The model considers two insulators and an intermediate conducting gate. The first insulator is the thin gate oxide of the MOSFET, and the second insulator is the sensing layer of the ISFET.
Considering Gauss surfaces as indicated in Fig. 2-3 and the unit area charges in the interfaces, the following equations are written (from top to bottom):
Qsol+Qads=-ε2E2…(1) QIG=ε2E2-ε1E1…(2) Qs+Qss=ε1E1…(3)
Fig. 3. Gate layers of the intermediate gate ISFET, where QIG is the intermediate gate charge, Qss is the silicon surface states charge, Qs is the silicon charge, Qads is the charge adsorbed in the sensing layer, and Qsol is the solution charge.
E1,E2,ε1,ε2 are the electric fields and dielectric constants in the insulators.
The application of a voltage to the reference electrode yields the voltage balance equation
VR-VRE+φ0(pH)=V1+V2+Φss+ψs…(4)
whereΦss is the work function difference between the solution and the semiconductor, which includes the work function differences introduced by the intermediate gate.
VRE is the constant potential drop between the reference electrode and the electrolyte, andψs is the silicon surface potential. V1 and V2are the potential drops at the insulators.
φ0(pH) is called the potential drop which is derived from above.
The voltage across the insulators is given by
a and b are the thickness of the first and the second insulator (the gate oxide and the sensing layer), respectively.
From (1)–(5)
where CI is the capacitance of the composite insulator given by
CI
The semiconductor charge is approximated by the maximal depletion charge, Vth =VRE-φ0(pH)+Φss
Equation (8) provides the basis for the operation of the ISFET with an intermediate gate. As in a regular ISFET, the potential drop at the interface is directly related to the threshold voltage. The difficulty arises from the additional term in (8), which may introduce a change in the threshold voltage and hence a drift in the readout of the sensor. The main challenge in the intermediate gate ISFET is to assure the operation of the device at constant intermediate gate charge.
Moreover, it must be noticed that classic ISFETs use composite insulators where the interface traps act similarly to a conducting layer. Instabilities in the charge trapped at these sites area possible source of drift. Hence, the intermediate gate model may explain some of the drifts present in classic ISFETs. A first condition for the presence of a constant intermediate gate charge is found when the sensing layer operates as an ideal insulator. In this case the intermediate gate is placed between two good quality insulators and no charging or discharging of the intermediate gate is possible.
An ideal insulating sensing layer cannot be obtained in a practical device.
Considering a typical sensing layer capacitance value of 10 -7F/cm , a leakage current density through the sensing layer lower than 3×10 -14A/cm is required to obtain a drift lower than 1 mV/h. In memories, current densities of the required order of magnitude or lower are achieved at high temperature processes of the order of 1000 C.
If we use low-temperature evaporated sensing layers, these layers will show leakage currents in the range of 10 -8 –10 -4 A/cm [10]. For a leaky sensing layer intermediate-gate ISFET, the steady-state condition is achieved when the sensing layer current is zero and equal to the gate oxide current. Hence, at steady state, E2=0.
Evaluating (1)–(5) the charge-voltage balance equation is VR-VRE+φ0(pH)-(Φss
which corresponds to a MOSFET equation where the terms VA-VRE+
φ0(pH) work as an equivalent gate voltage. The threshold voltage is derived from (9) as follows:
which is only function ofφ0 and constant terms. Hence, threshold voltage changes are directly related to pH changes.
The steady-state condition is achieved controlling the thickness of the sensing layer to avoid large insulation. In any case, even at the lowest leakage current densities observed in low temperature evaporated layers, the transient is no longer than a few seconds.
In addition, the steady operation of the device is achieved with an appropriate design of the electronic readout. From (2) and (3) and considering that
QIG=QS+QSS…(11)
Eq. (11) shows that once the steady state is first achieved after the immersion of the ISFET and first stabilization at E2=0, the intermediate gate unit charge is only
function of the silicon charge. In other words, the variations in the adsorbed charge introduced by pH changes are compensated by the solution charge without affecting the intermediate gate charge.
2.3 References
[1] R.E.G. van Hal, “A general model to describe the electrostatic potential at electrolyte oxide interfaces”. Advances in Colloid and Interface Science 69, pp. 31-62, 1996.
[2] P.Bergveld, “Development of an ion-sensitive solid-state device for neurophysiological measurements”. IEEE Trans. Biomed. Eng, BME-17 () 70, 1970.
[3] J. W. Perram, “The oxide-solution interface”, Aust. J. Chem 27 pp.461-475, 1974 [4] W.M. Siu and R.S.C. Cobbold, Basic properties of the electrolyte-SiO2-Si system:
Physical and theoretical aspects. IEEE Trans. Electron devices ED-26 pp.1805-1815, 1979.
[5] T. Hiemstra, W.H. van Riemsdijk and G.H. Bolt, “Multisite proton adsorption modeling at the solid/solution interface of (hydr) oxides: A new approach”, J.Colloid Interface Sci., 133 pp.91-104, 1989.
[6] J.C. Van Kerkhof, “ISFET responses on a stepwise change in electrolyte concentration at constant pH”, Sensors Actuators B 18, pp56-59, 1994.
[7] D.A. Dzombak and F.M.M. Morel, “Surface Complexation Modelling. Hydrous Ferric Oxide”, John Wiley & Sons, New York, 1990
[8] C. G. Jakobson, U. Dinnar, M. Feinsod, and Y. Nemirovsky, “Ion-Sensitive Field-Effect Transistors in Standard CMOS Fabricated by Post Processing”, IEEE Senosors Journal Vol.2 No.4, August 2002.
[9] V. Mikhelashvili and G. Eisenstein, “Electrical characteristics of Ta 2O5 thin films deposited by electron beam gun evaporation,” Appl. Phys. Lett., vol. 75, pp.
2836–2838, 1999.
Chapter 3
Procedures of the experiment
All processes were done in NDL (National Nano Device Laboratory) and Nano Facility center. A simple list of the experiment is presented and the corresponding graph is shown in Fig. 3-1.
3.1 Fabrication process
1. RCA clean
2. Wet oxide thickness =600nm.
※ temperature=1050℃,time=65min 3. Mask 1 S/D define
4. BOE etch wet oxide
5. Screening dry oxide thickness=300 A°
※ temperature=1050℃, 12min 6.S/D implant
※ Dose=5E15 (1/cm2), Energy=25Kev (n-type) 7. N+ anneal 950℃ 30min
8. PE- oxide thickness=1μm
9. Mask 2 contact hole & gate region define
10. BOE etch PE- oxide 1μm (contact hole region)
PE- oxide 1μm+ wet oxide 6000A°(gate region) 11. Dry oxide thickness=100 A°
※ temperature=850℃, 60min 12. Barrier deposition
13. Sensing layer deposition 14. Mask 3 sensing region define 15. Barrier etching
16. Sensing layer etching 17. Deposit Ti/Pt
18. Mask 4 Ti/Pt region define
19. Thermal coater Al (back side) 5000A