Chapter 2 Backscattering Theory and Parameters Extraction
2.5 Threshold Voltage and DIBL
1
( + − − −
=
η η
Fig. 8 shows the RSD extracted by equation (17) for W/L=0.24um/0.1um and W/L=0.24um/0.065um and we focus on VG>1V to ensure a high electric field condition. Fig. 9 shows the RSD extracted at different VBS conditions. Fig. 10 shows the RSD extracted from different devices at the same scale. We have done many experiments in order to ensure that the RSD extracted from different channel length and bias conditions should be a constant. The RSD value extracted from the constant mobility method at different device dimensions will be used in some parameters extraction in this thesis.
Section 2.5 Threshold Voltage and DIBL
The threshold voltage extraction is an important part in the MOS transistors research and a key parameter in this work. We employ a maximum tran-conductance method in the linear region to assess quasi-equilibrium threshold voltage and the constant subthreshold current method in the saturation region to extract the DIBL.
The maximum tran-conductance is a method establishing a tangent line from the point where the tran-conductance is the maximum to show the threshold voltage in the ID-VG gragh. We set the drain voltage VD = 10mV to ensure the quasi- equilibrium case. Fig. 11 shows drain current versus gate voltage and the maximum tran-conductance method.
The Drain Induced Barrier-Lowering is the decreasing of the threshold voltage when the drain voltage increases, caused by conduction band bends lowering. In other words, the channel control from the gate will weaken at high drain electric field,
especially in the short channel devices. To develop the mismatch model accurately, the DIBL must be considered. We use the constant subthreshold current method to calculate the threshold voltage shift due to the VD increase and measure the DIBL in the saturation region. We set the drain voltage VD = 1V to ensure that the device is operated in the saturation region.
12
Chapter 3
Mismatch Experiment and Results
Section 3.1 Mismatch Model
The mismatch model is a mathematical equation to express the variation of the parameter. The mismatch properties have two features: the total mismatch of the parameter is composed of many single events of the mismatch-generating process and the effects on the parameter are so small that the contributions to the parameter can be summed [6]. The mismatch properties of threshold voltage are the main topic of mismatch since 1970s. In this thesis, our mismatch model is developed based on the research of threshold voltage in the traditional theory and the backscattering theory.
To reach for our goal, we must develop the mismatch model step by step. First of all, we focus on the width of the KBT layer and analyse its mismatch properties. Then we develop the backscattering coefficient mismatch properties in the next step.
One of the fundamental factors limiting the accuracy of MOS circuits is the current mismatch between identically devices. So, based on above considerations and series resistance extraction, the drain current mismatch model will be presented later. The transistors in the circuits usually operate in the saturation region. Thus, the mismatch models in this thesis are all developed and discussed in saturation region.
Section 3.2 Experiment
The measurement procedure is an important part in the mismatch work. Generally, to obtain the statistical variation, we need to measure a lot of devices. In this work, we measure over than 20 different dimensions of n-channel devices, whereas each scale has more than 30 dies on the wafer. All dies are made from the same process and have the same structure. They were fabricated using 65nm CMOS process. We measure our drain current by sweeping gate voltage from 0 to 1.2 V in a step of 25 mV when we fixed the drain voltage at 0.01 V, 0.1 V, and 1 V in order to cover both the equilibrium case and the saturation region case. In the extraction of the series resistance, we set substrate bias VB at = -0.4 V, -0.8 V, and 0 V. The temperature was fixed at 298 K.
The measurement setup includes the HP4156B and a Faraday box for shielding the wafer.
Section 3.3 Mismatch Properties of K
BT Layer’s Width
The mismatch properties can be expressed as the standard deviation: σ. The standard deviation can be calculated from the parameters extracted in the experiment.
In statistics, there should be more than 20 measured devices to ensure that the standard deviation calculated can be considered as the mismatch properties of all dies on the wafer. In this section, the standard deviations are calculated from over than 20 dies. The extreme variance of the parameter would be lead to high standard deviation.
Fig. 12 shows the standard deviation of KBT layer’s width versus the gate voltage from experiments. It can be seen that the variance would decrease when the gate
14
voltage increases. To propose a simple statistical model to explain the phenomenon observed, we pay attentions to the equation of the KBT layer’s width. In Chapter 2, we introduce the parabolic potential barrier model to calculate the width of KBT layer:
(18)
From above equation, we will express the mismatch of A as a function of the variance of threshold voltage. The variance of standard deviation with one random variable x can be expressed as:
(19)
Thus, from equation (18) and equation (19), the standard deviation of KBT layer’s width can be written as:
where . The standard deviation can be expressed as a function of inverse square root of the device area [6]. Thus we obtain a compact model:
where A is a constant depending on channel length and drain voltage and is independent of gate voltage.
Vth
A is the size proportionality constant for the variance
x
xof threshold voltage, as shown in Fig. 13. From the threshold voltage term in above equation, we can observe that the variance of KBT layer’s width would decrease when the gate voltage increases because that the effect of the threshold voltage fluctuation would become smaller. In other words, the variance of KBT layer’s width is sensitive to threshold voltage in the weak inversion region. This is a simple mathematical model to understand the mismatch properties of KBT layer’s width and can calculate it from just three simple parameters: threshold voltage, device size, and drain voltage.
Fig. 14 displays the mismatch calculations compared with the experiments for W/L=0.13um/0.1um, 0.24um/0.1um, and 1um/0.5um at drain voltage VD=1V. We can observe that the differences between the two are small. Fig. 15 shows that the variance of A versus square root of L/W for different devices at fixed gate voltage VG=1V. When the gate voltage is high, the difference of the threshold voltage in equation (21) can be ignored and the standard deviation of KBT layer’s width can be proportional to the square root of channel length divided by device width (L/W). It can be clearly shown in equation (21) by separating the channel length (L) term from constant A and multiplied by the inverse square root of area. Another relation can be observed from dividing each sides of equation (21) by KBT layer’s width, where the channel length term in constant A would be deleted. Then the standard deviation divided by the mean of KBT layer’s width is proportional to the inverse square root of device area when gate voltage is high. Fig. 16 displays this relationship which is a traditional relationship like current factor or mobility [6].
16
Section 3.4 Backscattering Coefficient Mismatch
The backscattering coefficient RC can be expressed as (1), whereas RC is a function of two variables: mean free path and KBT layer’s width. To express the mismatch as these two parts, we applied a differential equation below for analysis:
where σx and σy, are the variance of x and y, respectively. COV (x, y) is the correlation coefficient between (x, y). We assume that the mean-free-path and KBT layer’s width are independent of each other, that is, the correlation coefficient COV (x, y) is zero.
Thus the RC mismatch model can be expressed as:
This is a simple mathematical model to estimate the fluctuation of RC in the saturation region. The σA is already discussed in Section 3.3 and the ratio σλ/mean(λ) can be obtained by the experiment. Both of them have a proportional relationship with the inverse square root of area. From these two different mismatch properties, the standard deviation of RC can also be obtained, so does the standard deviation divided by the mean: σRC/mean(RC). The mismatch properties of the mean-free-path should have the same properties as mobility in [7]. Fig. 17 shows the relationship between the σλ/mean(λ) and the inverse square root of area. Fig. 18 displays the standard deviation RC versus gate voltage VG from equation (23), compared with experiments
( ) , ( 22 )
for W/L=0.13um/0.1um, and W/L=0.24/0.1um, all at VD=1V to ensure the saturation region. We can observe that the model and the experiments are quite close to each other.
Section 3.5 Drain Current Mismatch
Drain current mismatch properties is the last part of this work which directly affects the performance of the circuit. To develop the drain current mismatch model accurately, we considered the extracted series resistance:
( ) ( ( ) )
This is a whole drain current equation based on backscattering theory. We define that the current mismatch is the standard deviation divided by the mean: σID/mean(ID).
The standard deviation σg(x,y,z) with three variables of x, y and z can be expressed as:
)
y), COV(y, z), and COV(x, z) are the correlation coefficients of each variables. In this equation, we assume that these three coefficients are so small, leading to COV(x, y), COV(y, z), and COV(x, z) all being zero. Then the drain current can be expressed as:18
Fig. 19 and Fig. 20 display the relationship between threshold voltage, DIBL and area.
The variance of backscattering RC is discussed in Section 3.4 already. Thus we have:
)
Substituting equation (27) into the drain current mismatch model, we obtain the compact model:
Fig. 21 shows the mismatch of current versus gate voltage for W/L=0.13um/0.1um, and 0.24um/0.1um, at VD=1V to ensure the saturation region. We can observe that the current mismatch decreases when the gate voltage increases because that the
( ) ( )
fluctuation of the threshold voltage, DIBL and backscattering coefficient would have smaller effects at high gate voltages. And we can also observe that the difference between the model and the experiments are small. In this mismatch, the variance of RC is the dominant parameter which affects the drain current mismatch compared with threshold voltage and DIBL.
20
Chapter 4 Conclusion
We have developed a compact mathematical model for mismatch properties of MOS transistors in this thesis. Unlike the traditional research focused on threshold voltage variance only, we have incorporated additional parameters into discussion:
DIBL and backscattering coefficient. We have done many works in detail based on the backscattering theory, covering KBT layer’s width and mean-free-path. Besides, many data have been measured in order to verify our mismatch model. Step by step, several mismatch models have been successfully developed to express the matching properties of each involved parameters, especially the KBT layer’s width and the drain current mismatch.
Reference:
[1] M. J. Chen, and Li-Fang Lu, “A Parabolic Potential Barrier-Oriented Compact Model for the KBT Layer’s Width in Nano-MOSFETs,” IEEE Transactions on Electron Devices, vol. 55, no. 5, pp. 1265-1268, May 2008.
[2] Da-Wen Lin, Ming-Lung Cheng, Shyh-Wei Wang, Chung-Cheng Wu, and Ming-Jer Chen,” A Constant-Mobility Method to Enable MOSFET Series-Resistance Extraction,” IEEE Electron Device Letters, vol. 28, no. 12, pp.
1132-1134, December 2007.
[3] M. J. Chen, Huan-Tsung Huang, Yi-Chin Chou, Rong-Ting Chen, Yin-Ta Tseng, Po-Nien Chen, and Carlos H. Diaz, “Seperation of Channel Backscattering Coefficients in Nanoscale MOSFETs,” IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 39-42,September 2004.
[4] Raphael Clerc, Pierpaolo Palestri, and Luca Selmi, “On the Physical Understanding of the KT-layer Concept in Quasi-Ballistic Regime of Transport in Nanoscale Devices,” IEEE Transactions On Electron Devices, vol. 53, no. 7, pp. 1634-1640, July 2006.
[5] M. S. Lundstrom, “Elementary scattering theory of the si MOSFET,” IEEE Electron Device letters, vol. 18, no. 7, pp. 361-363, Jul. 1997.
[6] Marcel J. M. Pelgrom C. J. Duinmaijer, and Anton P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no.
5, pp 1433-1440, October 1989.
22
[7] Kadaba R. Lakshmikumar, Robert A. Hadaway, and Miles A. Copeland,
“Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,” IEEE Journal of Solid-State Circuits, vol. sc-21, no. 6, pp.
1057-1066 ,December 1986.
) 0 ( V V E
C D=
) 0 ( V V E
C D≠
~
L A
(
C)
S
D
F R
F = ⋅ 1 − F
SC S
R F
n
+n
+) ( th
G V
V >
q T KB
Fig.1
24 Experiment VG=1(V) Parabolic model VG=1(V) Experiment VG=0.7(V) Parabolic model VG=0.7(V) Experiment VG=0.5(V) Paranolic model VG=0.5(V)
W=0.13(um) Experiment VG=1(V) Parabolic model VG=1(V) Experiment VG=0.7(V) Parabolic model VG=0.7(V) Experiment VG=0.5(V) Paranolic modelVG=0.5(V)
W=0.24(um) VD=1(V)
Fig.3
0.0 0.2 0.4 0.6 0.8 1.0
0 50 100 150 200 250 300 350 400
0.0 0.2 0.4 0.6 0.8 1.0
0 50 100 150 200 250 300 350 400
W=0.13(um) W=0.24(um)
L(um)
VG=1(V)
) / )(
( cm2 V S
mean μ ⋅
26
W=0.13(um) L=0.1(um)
) / )(
( cm2 V S
mean μ ⋅
28
0.2 0.4 0.6 0.8 1.0 1.2
10 11 12 13 14 15 16 17 18
mean free path(nm)
VG(V)
L=0.5(um)
W=0.13(um)
Fig.6
ParabolicModel ( long channel MeanFreeMath)
W=0.13(um) VG=1(V)
ParabolicModel ( long channel MeanFreeMath)
W=0.24(um)
VG=1(V)
30
0.4 0.6 0.8 1.0 1.2
0 1000 2000 3000 4000 5000 6000 7000 8000
0.4 0.6 0.8 1.0 1.2
0 1000 2000 3000 4000 5000 6000 7000 8000
L=0.065(um) L=0.1(um)
Rsd(ohm * um)
VG(V)
W=0.24(um)
Rsd=220(ohm*um)
(VB=-0.8V,0V)
Fig.8
0.4 0.6 0.8 1.0 1.2
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0.4 0.6 0.8 1.0 1.2
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
VB=0V ,-0.4V VB=0V ,-0.8V
Rsd(ohm * um)
VG(V)
W=0.24(um) L=0.1(um)
Rsd=220(ohm*um)
Fig.9
32
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
200 400 600 800 1000 1200 1400 1600
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
200 400 600 800 1000 1200 1400 1600
sample1 sample2
Rsd(ohm*um)
VG(V)
W=1(um),L=0.1(um)
Rsd=220(ohm*um)
Fig.10
0.0 0.2 0.4 0.6 0.8 1.0
0.0000000 0.0000005 0.0000010 0.0000015 0.0000020 0.0000025 0.0000030 0.0000035 0.0000040
0.0 0.2 0.4 0.6 0.8 1.0
0.000000 0.000001 0.000002 0.000003 0.000004 0.000005 0.000006 0.000007 0.000008 0.000009 0.000010
VG(V)
W=0.13(um) L=0.1(um)
) (V Gm A
) I
D(A
th0
V
Fig.11
34
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
)
A
(nm σ
Gate Voltage(V)
Experiment
W=0.13(um) L=0.1(um) VD=1(V)
Fig.12
Fig.13
0 2 4 6 8 10 12
0.00 0.01 0.02 0.03 0.04 0.05
0 2 4 6 8 10 12
0.00 0.01 0.02 0.03 0.04 0.05
)
Vth
(V σ
) 1 (
−1WL um
) (
00454 .
0 V um
A
Vth= ⋅
36
Gate Voltage(V)
Mismatchmodel experiment W=1(um) L=0.5(um) VD=1(V)
Gate Voltage(V)
Mismatch Model Experiment
W=0.13(um) L=0.1(um) VD=1(V)
Mismatch model experiment
Gate voltage(V)
W=0.24(um) L=0.1(um) VD=1(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VG=1(V)
Fig.15
W L
)
A
(nm
σ
38
Fig.16
0 2 4 6 8 10 12
0.00 0.02 0.04 0.06 0.08 0.10
0 2 4 6 8 10 12
0.00 0.02 0.04 0.06 0.08 0.10
VG=1(V)
) 1 (
−1WL um
)(%) (A
A
mean σ
W=0.13 (um) W=0.24 (um) W= 1 (um)
VG=1(V)
(1/um)
40
Gate voltage(V)
Experiment model
W=0.13(um) L=0.1(um)
VD=1(V)
experiment model
Gate voltage(V)
W=0.24(um) L=0.1(um)
VD=1(V)
Fig.19
0 2 4 6 8 10 12
0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035
0 2 4 6 8 10 12
0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035
)
Vtho
(V σ
) 1 (
−1WL um
) (
00347 .
0 V um
A
Vtho= ⋅
42
Experiment
The mismatch model
w=0.13(um) L=0.1(um)
VD=1(V)
Experiment
The mismatch model