Chapter 4 Low Power Standard Cell Library
4.4 Cell Design
4.4.4 DFF and SETDFF
The traditional master-slave D type flip-flop (DFF) is shown in Fig. 4.25 The critical path is marked by the dash line. We also use the MVT approach to design this gate and the power and leakage power of this traditional master-slave DFF is shown in the Table 4.11. By examining the Fig. 4.25, we can realize that the master-slave DFF is composed by many inverters and tri-state buffers. From Fig. 4.20(b), we can see that there is only one normal-Vt device without any high-Vt device in the pull up part. Because of the concerning about the timing performance, we don’t use all high-Vt devices to compose the inverter gate and the buffer gate. This will cause that
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there are many paths of the leakage current in the traditional master-slave DFF structure. We propose the single edge trigger flip-flop (SETDFF) in our standard cell library for designers to use it in sequential circuits. The SETDFF is shown in Fig. 4.26.
The transistors on the critical path are mp1、mp4、mp6、mp7、mp8、mn8. We will change these devices into normal-Vt MOSs and other devices are still high-Vt MOSs.
The power and leakage power of this SETDFF is shown in the Table 4.12. We can see that the leakage power of SETDFF is lower than the leakage power of traditional master-slave DFF. So the SETDFF in our standard cell library is effective to diminish the leakage in sequential circuits.
Fig. 4.25 Mixed-Vt DFF schematic
Fig. 4.26 Mixed-Vt SETDFF schematic
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Table 4.11(a) Time and power table of Mixed-Vt DFF with VDD=0.5 v HVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
90.5 247.2 1658.2 1321.3
MVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
62.2 2155.5 995.3 654.8
Table 4.121(b) Time and power table of Mixed-Vt DFF with VDD=1 v HVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
391.9 510.3 267.3 248.2
MVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
308.9 4031.2 234.6 216.7
Table 4.132(a) Time and power table of Mixed-Vt SETDFF with VDD=0.5 v HVT Power (nW) Leakage power (pW) Tplh (ns) Tphl (ns)
72.2 164.7 2.476 1.914
MVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
60.3 789.8 2.072 1.416
Table 4.142(b) Time and power table of Mixed-Vt SETDFF with VDD=1 v HVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
380.4 340.9 306.3 281.3
MVT Power (nW) Leakage power (pW) Tplh (ps) Tphl (ps)
322.4 1368.6 286.7 250.9
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4.5 Summary
We have introduced several low power circuit design methods and present a mixed-Vt method that can gain low dynamic and leakage power consumption. Then we use our mixed-Vt method to design a mixed-Vt low power standard cell library. In above sections, we explain the reasons why we choose the mixed-Vt method and describe the overall design flow and the simulation environment. We also explain the rule that is about the cell selecting criterion and the advantages we will obtain by using mixed-Vt method to establish a standard cell library. After that, we use some kinds of cells in our standard cell library for instance to demonstrate that our mixed-Vt method is very effective in performance.
From many experimental results, we can get around 5% to 30% dynamic power saving and the area is 0% to 30% larger than the standard cells with single high-Vt transistors. We size our standard cell library under 0.5 V supply voltage for the bio- electronics application. Then we characterization our standard cell library for 0.5 V、
0.6 V and 1 V supply voltage. Because the threshold voltage of high-Vt transistor is about 0.3 V~0.4 V, we would use 0.6V instead of 0.5 V supply voltage to synthesize the design examples in Chapter 5.
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Chapter 5
Design Examples by Low Power Standard Cell Library
5.1 C17
C17 is a benchmark of ISCAS85 as shown in Fig. 5.1 C17 Schematic is formed by six NAND gates.
Fig. 5.1 C17 Schematic
We specify the input pin B、C、D to 1、1、1 and give active signals to input A and E to measure the time and power of C17 circuit. We use HVT and MVT NAND gates to establish this benchmark and the simulation result is shown in Table 5.1. We can see that the C17 circuit using the MVT approach can save around 9.4% power consumption and around 35.9% delay-power product less than the HVT one.
Meanwhile, there is no area penalty due to the area of MVT NAND2 is equal to the HVT NAND2.
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Table 5.1 Time and power table of C17 circuit with VDD=0.6 V HVT Tplh (ps) Tphl (ps) Power (nW) Delay-Power
(ns．nW)
In @ A 487.6 448.7
63.9 33.4
In @ E 577.6 578.6
MVT Tplh (ps) Tphl (ps) Power (nW) Delay-Power (ns．nW)
In @ A 350.8 382.4
57.9 21.4
In @ E 370.8 371.8
5.2 32-bit Ripple Adder
In this section, we will analyze the 32 bit ripple adder. We use our mix-Vt standard cell library and the high-Vt standard cell library of UMC to synthesize this circuit. We use the tool, prime power, to exercise 1M input pattern and the cycle time is 6 ns. The synthesis result is shown in the Table 5.2(a). We can see that the adder synthesized by our mix-Vt standard cell library can save around 12% dynamic power around 22% delay-power product less than the HVT one. The leakage power only increases around four times than the high-Vt one under the same clock rate. If we use the normal-Vt standard cell library to synthesize this 32 bit ripple adder, we can see that the leakage power will increase about eleven times than the high-Vt one.
Although someone may think that the dynamic power is lower by using the normal-Vt standard cell library, designers will pay a very high cost for the leakage power in the low power circuit such as the portable products. We can see that the leakage power of the normal-Vt standard cell library case increases around eleven times than the high-Vt one under the same clock rate. We also synthesize this 32 bit ripple adder with 0.6 v supply voltage, and the result is shown in Table 5.2(b)
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Table 5.2(a) Synthesis result of 32bit ripple adder with VDD=1 V
Mixed-Vt@6ns High-Vt@6ns Normal-Vt@6ns
Internal power 48.1 uW 55.1 uW 44.2 uW
Delay-Power 275.1 ns．uW 351.1 ns．uW 155.3 ns．uW
Table 5.2(b) Synthesis result of 32bit ripple adder with VDD=0.6 V
Mixed-Vt@20ns Internal power 4.7 uW
Switching power 749.1 nW Total dynamic
power 5.5 uW
Leakage power 145.4 nW
Total Power 5.6 uW
Total area 827.9
Delay 19.6 ns
Delay-Power 109.8 ns．uW
5.3 32-bit Wallace Tree Multiplier
We take another MVT circuit, the 32-bit wallace tree multiplier, to be the example. We also use the same input pattern with the same clock rate to measure the multipliers synthesized by our mix-Vt standard cell library, the high-Vt standard cell library and the normal-Vt standard cell library of UMC. The synthesis result is shown in the Table 5.3. We can see that the wallace tree multiplier synthesized by our mix-Vt
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standard cell library can save around 9.4% dynamic power and around 29%
delay-power product less than the HVT one. The leakage power increases around three times than the high-Vt one under the same clock rate. The normal-Vt one has the least dynamic power because the driving ability of the transistors in this library is better than that in the high-Vt and our mix-Vt standard cell library. But we can also observe that the leakage power is the major drawback of the normal-Vt standard cell library in this case. The leakage power will increase about nine times than the high-Vt one. We also synthesize this 32 bit wallace tree multiplier with 0.6 v supply voltage, and the result is shown in Table 5.3(b).
Table 5.3(a) Synthesis result of 32 bit wallace tree multiplier with VDD=1 V
Mixed-Vt@6ns High-Vt@6ns Normal-Vt@6ns
Internal power 1.5 mW 1.8 mW 1.5 mW
Total area 25512.1 18975.9 18885.6
Delay 3.94 ns 5.05 ns 2.23 ns
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Table 5.3(b) Synthesis result of 32 bit wallace tree multiplier with VDD=0.6 V
Mixed-Vt@20ns Internal power 55.3 uW
Switching power 35.9 uW Total dynamic
power 91.2 uW
Leakage power 3.7 uW
Total Power 94.9 uW
Total area 25956.7
Delay 12.48 ns
Delay-Power 1184.4 ns．uW
5.4 32-bit Shift Register
We have introduced the circuits that composed of the combination logic in the above sections. In this sections, we take the 32bit shift register for instance to compare the sequential circuit synthesized by our mix-Vt standard cell library with the high-Vt and normal Vt standard cell library. The synthesis result is shown in the Table 5.. The shift register synthesized by our mix-Vt standard cell library can save around 14.2% dynamic power and around 54% delay-power product less than the HVT one. The leakage power increase around 11.29% than the high-Vt one under the same clock rate. We can see that the leakage power of the 32bit shift register with our mix-Vt standard cell library and the high-Vt one are very close. The leakage power of the normal-Vt standard cell library case is still larger than the high-Vt and our mix-Vt standard cell library cases. And we can see the area of our mix-Vt case increases around 22.8% than the high-Vt and the normal-Vt case. We also synthesize this 32 bit shift register with 0.6 v supply voltage, and the result is shown in Table 5.3(b).
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Table 5.4(a) Synthesis result of 32 bit shift register with VDD=1 V
Mixed-Vt@4ns High-Vt@4ns Normal-Vt@4ns
Internal power 98.7 uW 116.4 uW 97.1 uW
Table 5.4(b) Synthesis result of 32 bit shift register with VDD=0.6 V
Mixed-Vt@12ns Internal power 17.3 uW
Switching power 4.6 uW Total dynamic
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Chapter 6 Conclusions
In this thesis, firstly, we have introduced the background of the standard cell library and its format. Then we discuss the timing and power models and their advantages and drawbacks in the present standard cell library. Because of the non-linear and non-ideal effects in the novel nanometer scale process, we can realize that it becomes difficult to model the timing ad power accurately using the conventional method. Therefore, we use the NLDM table to record the input dependent leakage power for all combinations of static input vectors and add the new timing/power model in the characterization tool to let the timing/power model of our standard cell library be more accurate in the 90nm or below process.
After realizing the background of the standard cell library and the flow of characterizing the cells, we would like to establish a low power standard cell library for the hearing aid using the solar battery or the portable electric products. So we have proposed a method using the mixed-Vt technique to reduce the power consumption for the low power circuit at first. This method is to replace the MOSs on the critical path and resizing them to achieve our low power requirements. Then we establish a 90nm low power standard cell library. Design examples are used to compare the performance and we can draw the conclusion that we can have around 5% to 30%
dynamic power saving, 20% to 55% delay-power product saving and the area is 0% to 40% larger than the standard cells with single high-Vt transistors.
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作者簡歷
姓名：林俊誼
出生地：台灣省台中市 出生日期：1983 年 6 月 21 日
學歷： 1989.9 ~ 1995.6 台中市立成功國小 1995.9 ~ 1998.6 台中市立光明國中 1998.9 ~ 2001.6 國立台中一中
2001.9 ~ 2005.6 國立交通大學 電機與控制工程學系 學士 2005.9 ~ 2007.8 國立交通大學 電子研究所 系統組 碩士