Chapter 6 Conclusion and Future Work
A.4 Timing controller module
The main purpose of timing control module is to receive the data from image process module and generate the timing for LCD and LED drivers to display the image on the panel and backlight. This module, consisting of source, gate, and backlight driver controllers, will be described in the following. Fig. A-20 and Fig.
A-21 show the block diagram and the synthesis result of timing control module.
Fig. A-20 The block diagram of timing controller module.
Fig. A-21 The synthesis of timing controller module.
A.4.1 Source driver controller
The source driver controller receives the image data (img) and transfers the data into RSDS mode to meet the requirement of source drivers. Fig. A-22 shows the block diagram of this controller. In order to read and write the data of one line simultaneously, one register (data1) is used as a line buffer for the data read from SDRAMs as shown in the synthesis result(Fig. A-23). The r1 and r2 are the RSDS generators. In addition, start signal (sth), polarity control (pol), and data latch (tp) are also prepared for driver inputs.
Gate Driver Controller
Backlight Driver
Source Driver Controller
Fig. A-22 The block diagram of source driver controller.
Fig. A-23 The synthesis of source driver controller.
A.4.2 Gate driver controller
Based on the frame reset signal (frm_rst) and data enable signal (de), the gate driver controller generates the start signal (stv) and trigger signal (cpv). The cpv enables the internal shift register of the gate driver to turn on the image row by row on LCDs. In addition, the separation enable signal (oe) avoids the crosstalk on adjacent rows. Fig. A-24 and Fig. A-25 show the block diagram and the synthesis result of gate driver controller.
Fig. A-24 The block diagram of gate driver controller.
Fig. A-25 The synthesis of gate driver controller.
A.4.3 Backlight driver controller
This controller generates the input signals of backlight (LED) drivers and determines the color sequence of RGBC or RGBY. The driver signals consist of timing clock (dclk), data latch (le), and serial gray level (sdi). Four sets of these control signals are designed for four groups of LED drivers in the whole backlight.
According to the synchronic field signal (vtt), the backlight colors are switched and synchronized with the image data. Besides, the ycflago as an exchange index sets the fourth field is yellow or cyan. Fig. A-26 and Fig. A-27 show the block diagram and the synthesis result of backlight driver controller.
Fig. A-26 The block diagram of backlight driver controller.
Fig. A-27 The synthesis of backlight driver controller.
A.5 Summary
In FPGA, the clock generation, input buffer, image process, and timing controller module are designed. The clock module is set as a robust and stable time reference for other three modules. In the buffer module, the input clock and system clock are synchronized. The data enable signal is also generated to define the effective image data. An implementation of frame buffer, including the data rearrangement and access of SDRAMs, is the main purpose of image process module following the input module.
Then, the timing control module receives the data from image process module and generates the timing for LCD and LED drivers to the display circuit. According to the synchronic field signal, the backlight colors are switched and synchronized with the field image. An exchange index for yellow or cyan field was also realized in the backlight controller of the timing controller module.
Publication List
Journal Papers
1. Chun-Ho Chen, Yao-Chung Yeh, and Han-Ping D. Shieh, “3-D Mobile Display Based on Moiré-Free Dual Directional Backlight and Driving Scheme for Image Crosstalk Reduction,” IEEE/OSA Journal of Display Technology (JDT), Vol.
4(1), pp. 92-96, 2008.
2. Chun-Ho Chen and Han-Ping D. Shieh, “Effects of Backlight Profiles on Perceived Image Quality for High Dynamic Range LCDs,” IEEE/OSA Journal of Display Technology (JDT), Vol. 4(2), pp. 153-159, 2008.
3. Chun-Ho Chen, Che-Chin Chen, Ke-Horng Chen, and Han-Ping D. Shieh,
“Driving AMOLED Panel by Time-Multiplexing Clamped Inverter Circuits for Reducing Complex Control Signals,” Journal of the Society for Information Display (JSID), Vol. 16(7), pp. 787-791, 2008.
4. Chun-Ho Chen, Fang-Cheng Lin, Ya-Ting Hsu, Yi-Pai Huang, and Han-Ping D.
Shieh, “A Field Sequential Color LCD Based on Color Fields Arrangement for Color Breakup and Flicker Reduction,” accepted by IEEE/OSA Journal of Display Technology (JDT).
5. Yi-Pai Huang, Ke-Horng Chen, Chun-Ho Chen, Fang-Cheng Lin, and Han-Ping D. Shieh, “Adaptive LC/BL Feedback Control in Field Sequential Color LCD Technique for Color Breakup Minimization,” IEEE/OSA Journal of Display Technology (JDT), Vol. 4(3), pp. 290-295, 2008.
International Conference Papers
1. Chun-Ho Chen and Han-Ping D. Shieh, “High Uniformity of Large Size Backlight System with Inclined LED Array,” IDMC2005, pp. 407-409.
2. Chun-Ho Chen and Han-Ping D. Shieh, “Inclined LED Array for Large-Sized Backlight System,” Society for Information Display 2005 (SID’05), pp. 558-561.
3. Chun-Ho Chen, Yao-Chung Yeh, and Han-Ping D. Shieh, “Morie Pattern and Image Crosstalk Reduction in 3D Mobile Display,” Society for Information Display 2006 (SID’06), pp. 1154-1157.
4. Chun-Hung Lai, Chun-Ho Chen, and Han-Ping D. Shieh, “A Novel 3D Double Screens Display,” International Display Workshop 2006 (IDW’06), pp.
1913-1916.
5. Che-Chin Chen, Yi-Fu Chen, Ti-Ti Liu, Chun-Ho Chen, Ming-Tsung Ho, Ke-Horng Chen, and Han-Ping D. Shieh, “Spatial-temporal Division in Field Sequential Color Technique for Color Filterless LCD,” Society for Information Display 2007 (SID’07), pp. 1806-1809.
6. Ya-Ting Hsu, Fang-Cheng Lin, Chun-Ho Chen, Yi-Pai Huang, and Han-Ping D.
Shieh, “Drive and Control Circuitry of OCB Field-Sequential Color LCD with High Data Rate,” IDMC 2007, pp.435-438.
7. Ya-Ting Hsu, Fang-Cheng Lin, Chun-Ho Chen, Yi-Pai Huang, and Han-Ping D.
Shieh, “A Field Sequential Color LCD Based on Color Field Arrangement for Color Breakup and Flicker Reduction,” International Display Workshop 2007 (IDW’07), LCT 3-3.
8. Chun-Ho Chen, Ke-Horng Chen, Yi-Pai Huang, Han-Ping D. Shieh, and Ming-Tsung Ho, “Gray Level Redistribution in Field Sequential Color LCD Technique for Color Breakup Reduction,” Society for Information Display 2008 (SID’08), pp. 1096-1099.
9. Jen-Chieh Hsieh, Yi-Pai Huang, Chun-Ho Chen, Yu-Chun Lo, Jen-Yu Fang, Han-Ping D. Shieh, Gu-Sheng Yu, and Tien Chiang, “Multi-Performance Film (MPF) for Highly Efficient LCD Backlights,” Society for Information Display 2008 (SID’08), pp. 1606-1609.
Domestic Conference Papers
1. Yao-Chung Yeh, Chun-Ho Chen, and Han-Ping D. Shieh, “Moire-free Directional Backlight Syetem For 3D Mobile Display,” Optics and Photonics Taiwan '05 (OPT ’05), G-SA-X-6-2
2. Shiou-Fong Liu, Chun-Ho Chen, and Han-Ping D. Shieh, “Optical Modeling of LED Backlight for Evaluation of Uniformity,” 2006 Taiwan Display Conference Proceedings (TDC’06), pp.396-399
3. Chien-Liang Wu, Chun-Ho Chen, Fang-Cheng Lin, Yi-Pai Huang, and Han-Ping D. Shieh, “A 5.6-inch Field Sequential Color LCD with Less Color Break-up,” Optics and Photonics Taiwan '07 (OPT ’07), GO-004
4. Jen-Chieh Hsieh, Yi-Pai Huang, Chun-Ho Chen, Yu-Chun Lo, Jen-Yu Fang, and Han-Ping D. Shieh, “Multi-Performance Film (MPF) for Highly Efficient LCD Backlights,” 2008 Taiwan Display Conference Proceedings (TDC’08), pp.398-401.
5. Chien-Liang Wu, Chun-Ho Chen, Fang-Cheng Lin, Yi-Pai Huang, and Han-Ping D. Shieh, “Demonstration of a Mobile-Sized Field Sequential Color LCD for Color Break-up Suppression,” 2008 Taiwan Display Conference Proceedings (TDC’08), pp.419-422.
Patents
1. Ke-Horng Chen, Chun-Ho Chen, Hsien-Chun Chiu, Han-Ping D. Shieh, and Ti-Ti Liu,“Spatial-temporal Division Filed Sequential Color LCD display,”
(ROC Taiwan Patent pending)
2. Chun-Ho Chen, Hugo Cornelissen, Pijlman Fetze, and Han-Ping D. Shieh,
“Illumination system for illuminating a display device, and display device,” (US and ROC Taiwan Patent pending)
3. Chun-Ho Chen, Yi-Pai Huang, Ke-Horng Chen, Fang-Cheng Lin, and Han-Ping D. Shieh, “Adaptive Feedback Control in Field Sequential Color Display,” (ROC Taiwan Patent pending)
Awards
2005 1st AUO Award in High Efficiency LCD, sponsored by AU Optronics.
2005 GSSAP scholarship by National Science Council (NSC).
2004 Student fellowship, Institute of Electro-Optical Engineering, NCTU.
Vita
Name: Chun-Ho Chen 陳均合
Day of birth: June 13, 1979
Address: 彰化縣秀水鄉花秀路 122 號 Education:
Sep. ’03 – Present : National Chiao Tung University, Hsinchu, Taiwan.
Ph. D. in Institute of Electro-Optical Engineering.
Sep. ’01 – Jan. ’03 : National Chiao Tung University, Hsinchu, Taiwan.
Master in Institute of Electronics.
Sep. ’97 – Jun. ’01 : National Chiao Tung University, Hsinchu, Taiwan.
Bachelor in Department of Electronics Engineering.
Experience:
Sep, ’06-Mar, ’07 Internship student at Philips Research Lab., Eindhoven, Netherland
Sep. ’05- Oct. ’05 Project members of AUO, FPD05’ Exhibition, Yokohama, Japan.
Feb. ’05- Jun. ’05 TA of Display Technology Experiment, Display Institute, NCTU.
Jul. ’04- Sep. ’04 Short-term internship at Chunghwa Picture Tubes, LTD.