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Timing Diagram

在文檔中 Bit Logic Instructions 1 (頁 162-171)

Pulse timer characteristics:

t t t

t = Programmed time RLO at S input

RLO at R input

Timer running

Scan for "1"

Scan for "0"

Status word

BR CC 1 CC 0 OV OS OR STA RLO /FC

writes: - - - x x x 1

Example

S_PULSE

S Q

BI TV

R BCD

I 0.0

I 0.1 S5TIME#2S

Q 4.0 T 5

If the signal state of input I0.0 changes from "0" to "1" (positive edge in RLO), the timer T5 will be started. The timer will continue to run for the specified time of two seconds (2 s) as long as I0.0 is "1". If the signal state of I0.0 changes from "1" to

"0" before the timer has expired the timer will be stopped. If the signal state of input I0.1 changes from "0" to "1" while the timer is running, the time is reset.

The output Q4.0 is logic "1" as long as the timer is running and "0" if the time has elapsed or was reset.

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13.4 S_PEXT Extended Pulse S5 Timer

Data Type Memory Area Description

T no. T-Nr. TIMER T Timer identification number;

range depends on CPU

S S BOOL I, Q, M, L, D Start input

TV TW S5TIME I, Q, M, L, D Preset time value

R R BOOL I, Q, M, L, D Reset input

BI DUAL WORD I, Q, M, L, D Remaining time value,

integer format

BCD DEZ WORD I, Q, M, L, D Remaining time value, BCD

format

Q Q BOOL I, Q, M, L, D Status of the timer

Description

S_PEXT (Extended Pulse S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. A signal change is always necessary in order to enable a timer. The timer runs for the preset time interval specified at input TV even if the signal state at the S input changes to "0" before the time interval has elapsed. The signal state at output Q is "1" as long as the timer is running. The timer will be restarted ("re-triggered") with the preset time value if the signal state at input S changes from "0" to "1" while the timer is running.

The timer is reset if the reset (R) input changes from "0" to "1" while the timer is running. The current time and the time base are set to zero.

The current time value can be scanned at the outputs BI and BCD. The time value at BI is binary coded, at BCD is BCD coded. The current time value is the initial TV value minus the time elapsed since the timer was started.

See also "Location of a Timer in Memory and Components of a Timer".

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Timing Diagram

Extended pulse timer characteristics:

t t t

t = Programmed time RLO at S input

RLO at R input

Timer running

Scan for "1"

Scan for "0"

t

Status word

BR CC 1 CC 0 OV OS OR STA RLO /FC

writes: - - - x x x 1

Example

S_PEXT

S Q

BI TV

R BCD

I 0.0

I 0.1 S5TIME#2S

Q 4.0 T 5

If the signal state of input I0.0 changes from "0" to "1" (positive edge in RLO), the timer T5 will be started. The timer will continue to run for the specified time of two seconds (2 s) without being affected by a negative edge at input S. If the signal state of I0.0 changes from "0" to "1" before the timer has expired the timer will be re-triggered. The output Q4.0 is logic "1" as long as the timer is running.

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13.5 S_ODT On-Delay S5 Timer

Data Type Memory Area Description

T no. T-Nr. TIMER T Timer identification number;

range depends on CPU

S S BOOL I, Q, M, L, D Start input

TV TW S5TIME I, Q, M, L, D Preset time value

R R BOOL I, Q, M, L, D Reset input

BI DUAL WORD I, Q, M, L, D Remaining time value,

integer format

BCD DEZ WORD I, Q, M, L, D Remaining time value, BCD

format

Q Q BOOL I, Q, M, L, D Status of the timer

Description

S_ODT (On-Delay S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. A signal change is always necessary in order to enable a timer.

The timer runs for the time interval specified at input TV as long as the signal state at input S is positive. The signal state at output Q is "1" when the timer has elapsed without error and the signal state at the S input is still "1". When the signal state at input S changes from "1" to "0" while the timer is running, the timer is stopped. In this case the signal state of output Q is "0".

The timer is reset if the reset (R) input changes from "0" to "1" while the timer is running. The current time and the time base are set to zero. The signal state at output Q is then "0". The timer is also reset if there is a logic "1" at the R input while the timer is not running and the RLO at input S is "1".

The current time value can be scanned at the outputs BI and BCD. The time value at BI is binary coded, at BCD is BCD coded. The current time value is the initial TV value minus the time elapsed since the timer was started.

See also "Location of a Timer in Memory and Components of a Timer".

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Timing Diagram

On-Delay timer characteristics:

t

t = Programmed time RLO at S input

RLO at R input

Timer running

Scan for "1"

Scan for "0"

t t

Status word

BR CC 1 CC 0 OV OS OR STA RLO /FC

writes: - - - x x x 1

Example

S_ODT

S Q

BI TV

R BCD

I 0.0

I 0.1 S5TIME#2S

Q 4.0 T 5

If the signal state of I0.0 changes from "0" to "1" (positive edge in RLO), the timer T5 will be started. If the time of two seconds elapses and the signal state at input I0.0 is still "1", the output Q4.0 will be "1". If the signal state of I0.0 changes from

"1" to "0", the timer is stopped and Q4.0 will be "0" (if the signal state of I0.1 changes from "0" to "1", the time is reset regardless of whether the timer is running or not).

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13.6 S_ODTS Retentive On-Delay S5 Timer

Data Type Memory Area Description

T no. T-Nr. TIMER T Timer identification number;

range depends on CPU

S S BOOL I, Q, M, L, D Start input

TV TW S5TIME I, Q, M, L, D Preset time value

R R BOOL I, Q, M, L, D Reset input

BI DUAL WORD I, Q, M, L, D Remaining time value,

integer format

BCD DEZ WORD I, Q, M, L, D Remaining time value, BCD

format

Q Q BOOL I, Q, M, L, D Status of the timer

Description

S_ODTS (Retentive On-Delay S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. A signal change is always necessary in order to enable a timer. The timer runs for the time interval specified at input TV even if the signal state at input S changes to "0" before the time interval has elapsed. The signal state at output Q is "1" when the timer has elapsed without regard to the signal state at input S. The timer will be restarted (re-triggered) with the specified time if the signal state at input S changes from "0" to "1" while the timer is running.

The timer is reset if the reset (R) input changes from "0" to "1" without regard to the RLO at the S input. The signal state at output Q is then "0".

The current time value can be scanned at the outputs BI and BCD. The time value at BI is binary coded, at BCD it is BCD coded. The current time value is the initial TV value minus the time elapsed since the timer was started.

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Timing Diagram

Retentive On-Delay timer characteristics:

t t t

t = Programmed time

t RLO at S input

RLO at R input

Timer running

Scan for "1"

Scan for "0"

Status word

BR CC 1 CC 0 OV OS OR STA RLO /FC

writes: - - - x x x 1

Example

S_ODTS

S Q

BI TV

R BCD

I 0.0

I 0.1 S5TIME#2S

Q 4.0 T 5

If the signal state of I0.0 changes from "0" to "1" (positive edge in RLO), the timer T5 will be started. The timer runs without regard to a signal change at I0.0 from "1"

to "0". If the signal state at I0.0 changes from "0" to "1" before the timer has expired, the timer will be re-triggered. The output Q4.0 will be "1" if the timer elapsed. (If the signal state of input I0.1 changes from "0" to "1", the time will be reset irrespective of the RLO at S.)

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13.7 S_OFFDT Off-Delay S5 Timer

Data Type Memory Area Description

T no. T-Nr. TIMER T Timer identification number;

range depends on CPU

S S BOOL I, Q, M, L, D Start input

TV TW S5TIME I, Q, M, L, D Preset time value

R R BOOL I, Q, M, L, D Reset input

BI DUAL WORD I, Q, M, L, D Remaining time value,

integer format

BCD DEZ WORD I, Q, M, L, D Remaining time value, BCD

format

Q Q BOOL I, Q, M, L, D Status of the timer

Description

S_OFFDT (Off-Delay S5 Timer) starts the specified timer if there is a negative edge at the start (S) input. A signal change is always necessary in order to enable a timer. The signal state at output Q is "1" if the signal state at the S input is "1" or while the timer is running. The timer is reset when the signal state at input S goes from "0" to "1" while the timer is running. The timer is not restarted until the signal state at input S changes again from "1" to "0".

The timer is reset when the reset (R) input changes from "0" to "1" while the timer is running.

The current time value can be scanned at the outputs BI and BCD. The time value at BI is binary coded, at BCD it is BCD coded. The current time value is the initial TV value minus the time elapsed since the timer was started.

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Timing Diagram

Off-Delay timer characteristics:

t t t

t = Programmed time RLO at S input

RLO at R input

Timer running

Scan for "1"

Scan for "0"

t

Status word

BR CC 1 CC 0 OV OS OR STA RLO /FC

writes: - - - x x x 1

Example

S_OFFDT

S Q

BI TV

R BCD

I 0.0

I 0.1 S5TIME#2S

Q 4.0 T 5

If the signal state of I0.0 changes from "1" to "0", the timer is started.

Q4.0 is "1" when I0.0 is "1" or the timer is running. (if the signal state at I0.1 changes from "0" to "1" while the time is running, the timer is reset).

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在文檔中 Bit Logic Instructions 1 (頁 162-171)

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