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A RCHITECTURE OF S AMPLING C LOCK S YNCHRONIZATION

CHAPTER 4 ARCHITECTURE OF TIMING SYNCHRONIZATION SCHEME

4.2 A RCHITECTURE OF S AMPLING C LOCK S YNCHRONIZATION

Sampling clock synchronization consists of three blocks: resampler, SCO estimation and loop filter. The architecture of resampler is depicted in Fig 2.26. Since the resampler operates all the time, how to reduce its power consumption is very important. As illustrated in Chapter 2, resampler combines interpolator and decimator so that the power consumption reduces nearly half.

The architectures of SCO estimator and loop filter are shown in Fig 4.5 and Fig 2.27 respectively. Note the Arg operation in SCO estimator should exploit the ROM table instead of using divider.

Extract Continual Pilot

Extract Continual Pilot Previous symbol

cont. pilots

RegReg

Arg + table

1/2 (1π +N Ng/ ) ( T )1 T

B A A A= (ROM)

Fig 4.5 Architecture of joint SCO and CFO estimator

In the baseband of DVB-T system, the most important issue in hardware implementation is the efficiency of memory sharing. DVB-T system, in particular, has very large size of OFDM symbols so that the memory requirement is huge. Furthermore, in channel estimation design, the 2-D interpolation method is commonly exploited for resisting Doppler spread. The 2-D interpolation channel estimation acquires the memory of three and 1/3 complete OFDM symbols. If the receiver supports 8K mode transmission, it leads the amazing required memory size. In [20], an embedded DRAM unit performs all memory operations such as buffering three OFDM symbols in order to enable channel time interpolation, extracting scattered pilot for channel estimation and fine symbol synchronization, and extracting TPS pilot for TPS detection. Separated memory should not be applied in DVB-T system due to its inefficiency.

Another thought about hardware implementation of DVB-T system is to exploit a DSP processor. Since the basic operations within the baseband DVB-T system are similar like correlation and accumulation, the DSP processor probably can perform in an efficient way to compute all the operations. Unlike ASIC design, DSP processor based design will lead to a very complicated control of data path. But the advantage of fewer hardware cost is expectable.

Chapter 5

Conclusion and Future Work

The complete DVB-T digital baseband receiver design is accomplished in Matlab. The simulation platform can evaluate the overall system performance in each transmission mode and each channel model. Our system can resist strong multipath channel, large CFO, SCO, AWGN and Doppler frequency spread. The timing synchronization scheme including symbol synchronization and sampling clock synchronization is presented. The proposed low complexity fine symbol synchronization can reduce the computational complexity effectively.

The conventional method of N/2 IFFT has been improved by applying an average window and therefore N/32 IFFT can be adopted in fine symbol synchronization. The symbol timing offset is kept in less than 3 samples so that the ISI can be avoided. On the other hand, a new sampling clock offset estimation algorithm based on linear least square error is proposed in this thesis. The proposed SCO estimation can overcome the problem of unequally distributed continual pilots in conventional designs and hence the steady-state mean square error of estimation results can be improved. The sampling clock synchronization can limit the residual SCO to 1ppm± . With multi-stage synchronization loop, the system achieves high performance due to small parameter Kp of loop filter. The overall timing synchronization achieves a high tolerance to severe channel distortion including Rayleigh channel, Doppler spread 70Hz, CFO 20ppm and SCO 20ppm.

In the future, the channel estimation unit can be improved by applying Wiener interpolation since the system performance is heavily dominated by channel estimation gain.

The resampler design can probably apply the polynomial interpolation to reduce the hardware

cost instead of classical FIR interpolation. There are several other interpolation techniques such as Farrow structure and Lagrange interpolation. We have to find out the best method of interpolation for DVB-T system in the future. In the equalization design, there are some robust techniques like MAP (maximum a posteriori) equalizer and SOVA (soft-output Viterbi algorithm) equalizer. Instead of conventional equalizer without any feedback, these noise prediction equalizers can gain several decibels of system performance especially in strong multipath channel such as Rayleigh channel. In the recent relative materials [22][23], we can discover the required C/N values in ETSI standard have some errors. Therefore, in our future work, we have to consult more other researches for system performance verification. At last, the fixed point simulation should be performed so that the hardware implementation is able to verify our proposed algorithms in silicon-proven.

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[23] Notes of DVB-H Meeting #16 10th and 11th June 2004.