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Unified Hardware Design, Specification, and Verification Language

6. Data types

6.6 Net types

6.6.4 Trireg net

The trireg net stores a value and is used to model charge storage nodes. A trireg net can be in one of two states, as follows:

Driven state When at least one driver of a trireg net has a value of 1, 0, or x, the resolved value propagates into the trireg net and is the driven value of the trireg net.

Capacitive state When all the drivers of a trireg net are at the high-impedance value (z), the trireg net retains its last driven value; the high-impedance value does not prop-agate from the driver to the trireg.

The strength of the value on the trireg net in the capacitive state can be small, medium, or large, depending on the size specified in the declaration of the trireg net. The strength of a trireg net in the driven state can be supply, strong, pull, or weak, depending on the strength of the driver.

For example, Figure 6-1 shows a schematic that includes a trireg net whose size is medium, its driver, and the simulation results.

Table 6-3—Truth table for wand and triand nets wand/triand 0 1 x z

0 0 0 0 0

1 0 1 x 1

x 0 x x x

z 0 1 x z

Table 6-4—Truth table for wor and trior nets wor/trior 0 1 x z

0 0 1 x 0

1 1 1 1 1

x x 1 x x

z 0 1 x z

Figure 6-1—Simulation values of a trireg and its driver

a) At simulation time 0, wire a and wire b have a value of 1. A value of 1 with a strong strength propagates from the and gate through the nmos switches connected to each other by wire c into trireg net d.

b) At simulation time 10, wire a changes value to 0, disconnecting wire c from the and gate. When wire c is no longer connected to the and gate, the value of wire c changes to HiZ. The value of wire b remains 1 so wire c remains connected to trireg net d through the nmos2 switch. The HiZ value does not propagate from wire c into trireg net d. Instead, trireg net d enters the capacitive state, storing its last driven value of 1. It stores the 1 with a medium strength.

6.6.4.1 Capacitive networks

A capacitive network is a connection between two or more trireg nets. In a capacitive network whose trireg nets are in the capacitive state, logic and strength values can propagate between trireg nets.

For example, Figure 6-2 shows a capacitive network in which the logic value of some trireg nets change the logic value of other trireg nets of equal or smaller size.

In Figure 6-2, the capacitive strength of trireg_la net is large, trireg_me1 and trireg_me2 are medium, and trireg_sm is small. Simulation reports the following sequence of events:

a) At simulation time 0, wire a and wire b have a value of 1. The wire c drives a value of 1 into trireg_la and trireg_sm; wire d drives a value of 1 into trireg_me1 and trireg_me2. b) At simulation time 10, the value of wire b changes to 0, disconnecting trireg_sm and

trireg_me2 from their drivers. These trireg nets enter the capacitive state and store the value 1, their last driven value.

c) At simulation time 20, wire c drives a value of 0 into trireg_la. d) At simulation time 30, wire d drives a value of 0 into trireg_me1.

e) At simulation time 40, the value of wire a changes to 0, disconnecting trireg_la and trireg_me1 from their drivers. These trireg nets enter the capacitive state and store the value 0. f) At simulation time 50, the value of wire b changes to 1.

g) This change of value in wire b connects trireg_sm to trireg_la; these trireg nets have different sizes and stored different values. This connection causes the smaller trireg net to store the value of the larger trireg net, and trireg_sm now stores a value of 0.

This change of value in wire b also connects trireg_me1 to trireg_me2; these trireg nets have the same size and stored different values. The connection causes both trireg_me1 and trireg_me2 to change value to x.

nmos1 nmos2

wire c

trireg d

wire a wire b

simulation time wire a wire b wire c trireg d

1 1 strong 1 strong 1

0 1 HiZ medium 1

10 0

VERIFICATION LANGUAGE

Figure 6-2—Simulation results of a capacitive network

In a capacitive network, charge strengths propagate from a larger trireg net to a smaller trireg net. Figure 6-3 shows a capacitive network and its simulation results.

In Figure 6-3, the capacitive strength of trireg_la is large, and the capacitive strength of trireg_sm is small. Simulation reports the following results:

a) At simulation time 0, the values of wire a, wire b, and wire c are 1, and wire a drives a strong 1 into trireg_la and trireg_sm.

b) At simulation time 10, the value of wire b changes to 0, disconnecting trireg_la and trireg_sm from wire a. The trireg_la and trireg_sm nets enter the capacitive state. Both trireg nets share the large charge of trireg_la because they remain connected through tranif1_2.

c) At simulation time 20, the value of wire c changes to 0, disconnecting trireg_sm from trireg_la. The trireg_sm no longer shares large charge of trireg_la and now stores a small charge.

d) At simulation time 30, the value of wire c changes to 1, connecting the two trireg nets. These trireg nets now share the same charge.

e) At simulation time 40, the value of wire c changes again to 0, disconnecting trireg_sm from trireg_la. Once again, trireg_sm no longer shares the large charge of trireg_la and now stores a small charge.

40 0 0 0 0 0 1 0 1

trireg_sm trireg_la

trireg_me2 trireg_me1

wire a

wire b

wire c

wire d

simulation

time wire a wire b wire c wire d trireg_la trireg_sm trireg_me1 trireg_me2

0 1 1 1 1 1 1 1 1

10 1 0 1 1 1 1 1 1

20 1 0 0 1 0 1 1 1

30 1 0 0 0 0 1 0 1

nmos_1

nmos_2 tranif1_2

50 0 1 0 0 0 0 x x

tranif1_1

Figure 6-3—Simulation results of charge sharing

6.6.4.2 Ideal capacitive state and charge decay

A trireg net can retain its value indefinitely, or its charge can decay over time. The simulation time of charge decay is specified in the delay specification of the trireg net. See 28.16.2 for charge decay explanation.