Chapter 3 Basic Power Amplifiers Design
3.2 Conventional RF power amplifier design
3.2.2 Wide-band amplifier design
For wide-band amplifier design, it’s difficult to achieve the impedance matching in wide frequency range and gain flatness in it. Again, we start this topic at the wide-band LNA topology. Figure 3-9 is the LNA circuit schematic. We discuss this circuit step by step from the first stage. First, to make1/gm = 50Ω, the gm value of common gate amplifier is going to be fixed at certain trans-conductance. An additional stage is required to provide sufficient gain over the desired band. A shunt feedback common source amplifier is used in the second stage for this purpose. The
first step is the selection of transistor size and bias condition of the M1 to yield Ω
=
=1/ 50
ReZ11 gm . This ensures input matching condition for wide-band of frequency. But this condition is violated with optimum noise condition. There is a
trade-off between noise and impedance matching in the LNA circuit. One of the major problems in the wide bandwidth amplifier design is the limitation imposed by the gain-bandwidth product of the active device. We know that any active device has a gain roll off at high frequency because of the gate-drain and gate-source capacitance in the transistor. This effect degrades the forward gain as the frequency increases and eventually the transistor stops functioning as an amplifier at the high frequency.
Therefore the second design step is the selection of optimal bias point of second stage of LNA so that it operates at its maximum fT. In addition to this S21 degradation
with frequency other complications that arises in wide-bandwidth amplifier design includes, increase in reverse gain S12 and noise figure at high frequency. Negative feedback configuration is used to reduce these effects and increase the bandwidth. An inductor L is connected in series with Rf such that after certain frequency the negative feedback decreases in proportion to the S21 roll-off. This technique improves gain flatness at high frequency. The load inductance of L1 and L2 replace the resistor load which is used conventionally. The magnitude of the inductor’s impedance increases as frequency increases. This increase inductor impedance compensates the active device gain degradation that occurs at high frequency [13].
Another wide-band LNA design schematic is shown in Figure 3-10. In Figure 3-10, the Rf is added as a shunt feedback element to the conventional cascade narrow
band LNA and Lload is used as shunt peaking inductor at the output. The capacitor Cf
is used for the ac coupling purpose. The source follower, composed of M3 and M4, is added for measurement proposes only, and provides wideband output matching. C1
and C2 are ac coupling capacitor. The small-signal equivalent circuit at he input of the LNA is shown in Figure 3-11. The resistor RfM =Rf /(1−Av) represents the Miller equivalent input resistance of Rf, where Av is the open-loop voltage gain of the LNA.
From equivalent circuit, the value of Rf can be much larger than that of the conventional resistance shunt-feedback. In the conventional resistance shunt-feedback, the size of Rf is limited as RfM determines the input impedance. One of the key roles of the feedback resistor Rf is to reduce the Q-factor of the resonating narrowband LNA input circuit. The Q-factor of the circuit shown in Figure 3-11 can be approximately given by
From (3.8), and considering the inversely linear relation between the -3dB bandwidth and the Q-factor, the narrowband LNA in Figure 3-9 can be converted into a wideband amplifier by the proper selection of Rf. To design a wideband amplifier that covers a certain frequency band, the narrowband amplifier will be optimized at
flattening the gain over a wider bandwidth of frequency with much smaller noise
Figure 3-9: A wide-band LNA circuit schematic.
Lg
Figure 3-10: Another wide-band LNA schematic.
s T
L ω
Figure 3-11: Small-signal equivalent circuit at the input.
Chapter4
UWB CMOS Power Amplifier design
4.1 The PA Issues of UWB Transmitter
In UWB systems, the power level from the UWB transmitter should be low enough not to interfere with the already existing communication systems, for example 802.11a. As shown in Figure 4.1[33], the low output levels that specified by the Federal Communications Commission (FCC) is less than -41.3 dBm/MHz. Therefore, for a 7 GHz bandwidth, the peak output power is approximately-3 dBm or 500μW.
UWB systems need not require large transistors, and greatly lighten the difficult of CMOS technology. The main challenging task becomes to achieve a high gain and good impedance match over the entire frequency band.
Figure 4-1: The power level of UWB.
Linearity is another issue in UWB systems. For constant envelope modulation schemes like GMSK, FSK, the amplitude remains constant and non-linear high
efficiency power amplifier is used. However, non-constant envelope modulation schemes like CDMA, the amplitude of the signal also carries some data information and hence it is important to maintain the exact shape of the signal without introducing any distortion through the power amplifier. It is noted that because the bandwidth of MB-OFDM is less than DS-CDMA, the linearity requirements is more relaxed.
4.2 UWB Design for CMOS Power Amplifier
In this chapter, we introduce a two stage power amplifier for UWB application. To design a UWB PA, the first consideration is to achieve wide bandwidth matching network. At the same time, gain flatness is another important goal of the wide-band amplifier design. There are many methods for wide bandwidth matching network, such as distributed amplifier (DA) and balance amplifier etc., but we’ll provide our solution using CMOS PA design for these key points.
4.2.1 Input Matching: Cascode with Resistor Feedback
As we mentioned in Chapter 3.2, the cascade topology of resistor feedback is considered to starting my design at wide-band matching. Figure 4-2 shows the first stage of our design. The Rf is added as a shunt feedback element to the conventional cascade narrow band amplifier and Lload is used as shunt peaking inductor at the output. Figure 4-3 shows the small-signal equivalent circuit, in which the RS means
the impedance of the signal source. The resistor RfM =Rf /(1−Av) represents the Miller equivalent input resistance of Rf, where Av is the open-loop voltage gain of the cascode amplifier. From its equivalent circuit, the value of Rf can be much larger than that of the conventional resistance shunt-feedback. In the conventional resistance shunt-feedback, the size of Rf is limited as RfM determines the input impedance. One of the key roles of the feedback resistor Rf is to reduce the Q-factor of the resonating narrow-band amplifier input circuit. Recalling (3.7), the impedance of the amplifier with source degeneration can be derived as
s
The Q-factor of the circuit shown in Figure 4-3 can be approximately given by
gs
From (4.2), and considering the inversely linear relation between the -3dB bandwidth and the Q-factor, the amplifier can be converted into a wideband amplifier by the proper selection of Rf. To design a wideband amplifier that covers a certain frequency band, the amplifier will be optimized at the center frequency. The feedback resistor Rf also provides its conventional roles of flattening the gain over a wider bandwidth of frequency with much smaller noise figure degradation [14].
Figure 4-2: The input stage of our PA.
R
S LgRfM
Cgs
s TL
ω
L
sFigure 4-3: The small-signal equivalent circuit at the input.
4.2.2 Output Matching with Inductor-resistor Feedback
Output matching networks are also a problem to UWB PA. Since, antenna connect to the output of PA, the matching networks of PA must transfer to 50Ω for wideband application. As the components of matching network are increasing, the parasitic effects are also increasing. There come some bothering interferences such as power
loss, efficiency increase, and output noise increase.
In this work, we simplify output matching network by load-line theorem. The basic concept is selecting an optimum device it has optimum output load at 50Ω. By simulation of I-V curve, the inductor-resistor feedback topology not only benefits the goal of gain flatness but also has good performance for wideband design, as shown in Figure 4-4.
R
biasL
fR
fL
loadL
SDC blocking
R
loadM3
Figure 4-4: The output stage of our design.
Now we discuss the load-line result about this PA, as shown in Figure 4-5. In this case, the NMOS transistor of TSMC 0.18um process, has the width of160-um and the length of 0.18-um length. Lf is 2.25nH, Rbias is 350Ω, Rf is 150Ω, and Lload is 3.47nH.
When Rload is 50Ω, we set the operation point of the bias to be 1.2V of VDS and 0.8V of VGS.
Figure 4-5: The I-V curve of the load-line study of the PA.
4.2.3 Gain flatness of amplifier with inductor-resistor feedback
This is the measurement of uniformity of the gain across the wide frequency range of interest. This parameter commonly used for wideband systems can impact pulse distortion in impulse-based UWB. It is desired that the gain be flat over the frequency band, typically a tolerance of ±0.5 dB.
It’s worth discussing further for the feedback of our input stage. The feedback resistor, Rf1, plays a key role for the gain as known in circuit theorems, and so do the Lf2 and Rf2 in the output stage. The resistor feedback can be design in such a way that it can provide the require match at both the input and output ends. Figure 4-4 show the characteristic of resistor feedback. Clearly, the low frequency gain drops due to small feedback resistor, and large feedback resistor provide good gain but have large gain variation, as shown in Figure 4-6. Since input impedance is usually on 50Ω,
m1
small resistor can get better matching. Therefore, we might trade off between better matching and larger low frequency gain.
0.0 3.0G 6.0G 9.0G 12.0G 15.0G
0.0
Figure 4-6: The comparison with the value of the feedback resistor.
We use inductor-resistor feedback to improve the gain at matching consideration.
Inductor-resistor feedback impedance can be written as:
f Analyzing with circuit theorem, the gain of the shunt-shunt feedback
( ) ( ) ( ) ( ) ( )
(4.4), it is clear that Zf is small at low frequency and increase with the frequency raise.Therefore, the high frequency gain can slight increase. By cascading two stages, it should get flatness over the wide bandwidth. The concept is shown at Figure 4-7.
0.0 3.0G 6.0G 9.0G 12.0G 15.0G
CS with RL feedback sum in large-R case sum in small-R case S21(dB)
Figure 4-7: The |S21| of “common-source with RL feedback” and “two stages overall”.
4.2.4 Detail of the Power Amplifier for UWB application
We start to design a two stage power amplifier and apply Advance Design System (ADS) for simulation tools, which can supports load-pull and large signal simulation.
TSMC 0.18µm process is used in this work, and small signal model and large signal model are supported by TSMC. At first, we decide the transistor parameters. We choose the width per finger is 2.5um and the finger number of each NMOS is 64; so the width of each NMOS is 160um. Besides, we add two capacitors C1 and C2 in order to connect with the two stages: not only for inter-stage matching but also for the DC blocking purpose. After simulating, the total topology is decided as Figure 4-8 and the detail of the passive devices is listed on Table 4-1.
Device Value Device Value
Rf1 400Ω Lf2 2.25nH
Lg1 0.908nH Rf2 150Ω
Lload1 2.45nH Lload2 3.47nH
LS1 0.1nH C2 2.85pF
C1 0.951pF LS2 0.15nH
Rbias 350Ω
Table 4-1: Passive devices of the PA.
Figure 4-8: The overall schema of our UWB PA.
4.2.5 Simulation Results
To simulate the result, we apply 0.7V to VG1, 1.8V to VDD1, and 1.2V to VDD2
respectively. Figure 4-9 shows the simulated S-parameter. |S11| and |S22|are lower than -10dB between 3.1 and 10.6GHz. And |S21| is higher than 13.5dB at the same range in our simulation results. The -3dB bandwidth is 2.5~11.7GHz for the simulation. The noise figure (NF) of this UWB LNA is shown in Figure 4-10. The noise figure varies between 3.8 to 4.1 at 3.1~10.6GHz. Figure 4-11 shows one of the index representing the stability. This amplifier is unconditionally stable at any frequency. The two-tone test results for third-order inter-modulation distortion are shown in Figure 4-12. The test is performed at 8GHz. IIP3 is to 16.7dBm, and the input referred 1-dB compression point (ICP) is 3.98dBm. The proposed UWB PA dissipate 38.9mW with two power supplies; one is 1.8V, and the other is 1.2V. Table 4-2 represents the performance between 3.1G to 10.6GHz.
B.W.
Table 4-2: The specification of the PA. In the brackets are the indexes at 8GHz.
0.0 3.0G 6.0G 9.0G 12.0G 15.0G
Figure 4-9: The S-parameter of the PA.
0.0 3.0G 6.0G 9.0G 12.0G 15.0G
0
Figure 4-10: The Noise Figure.
0.0 5.0G 10.0G 15.0G 20.0G 1
2 3 4 5 6 7
Frequency(Hz) Mu
Figure 4-11: The stability index: Mu.
4.2.6 Layout
The layout is shown in Figure 4.13, the total size occupied by the PA is 0.98x0.83 mm2, The capacitor is used metal-insulator-metal (MIM) capacitance supported by TSMC, the models of the resistor and inductor are supplied by TSMC. The metal width is decided according to the capacity of current flow and AC signal power. Input and output pads use GSG with 50Ω, and bias-tee is used for the input end.
Figure 4-13: The layout of the PA.
4.3 Further Design for Better Efficiency and Linearity
Review Figure 4-5 again, and we will find the I-V curve inclined. Because it is asymmetric to the operation point, the output signal swings in a smaller range.
Besides, the large signal linearity is limited. To improve these characteristics, we make a further design, as shown in Figure 4-14.
L
g1Figure 4-14: The further design of PA.
To take the advantages of previous PA, we choose the similar topology except for the DC-block capacitors on the feedback path. One capacitor is added on the input stage and the other is added for output stage. These capacitors play an important role to avoid the current leakage through the feedback path. In this work, the amplifier efficiency increases because of the better use for the DC power allocation.
4.3.1 Further Design by Load-line Curve
Beginning the topic to design a class A power amplifier, we need to take a look at Figure 4-15 and Figure 4-16. The size of the transistor and the DC bias condition must be synthesized. When we simulate the I-V curve for load-line decision, by the DC-block capacitor Cf2 the impedance of Zf is neglect and we obtain the vertical plot.
Thus, we can decide the transistor size and locate the load-line easier. In Figure 4-16, the point m1 means the operation point (VDS=1.8V ,and VGS=1.1V) and m2 is represented as knee point as (VGS=1.8V, Imax). The line connected with m1 and m2 is surely the desired load-line instead of the other line, called the optimum line, which passes to the punch-off region. Choosing the width as 100um, the Ropt is almost well-designed to 50Ω.
Figure 4-15: The output stage of the PA.
(a)
(b)
4.3.2 Simulation for Further Design
The circuit has shown in Figure 4-14. By changing the transistor size and the circuit topology, we obtain a UWB PA for 3-8GHz applications. It is decided that the width of the transistor M3 is 100um (2um per finger and 50 fingers.) To transfer signal from M1 and M2 to M3, M1 and M2 must not be wider than M3. Thus we design them as the same width. Table 4-3 figures out the value of each passive device. From Figure 4-17 to Figure 4-20 there are simulation results, and Table 4-2 represents the performance between 3GHz to 8GHz.
Device Value Device Value
Rf1 850Ω Lf2 3.27nH
Lg1 1.2nH Rf2 250Ω
Rbias1 450Ω Rbias2 1000Ω
Lload1 3.47nH Lload2 3.47nH
LS1 0.1nH C2 2.85pF
C1 0.951pF LS2 0.1nH
Cf1 0.951pF Cf2 0.951pF
C0 DC block
Table 4-3: The passive devices of the PA.
B.W.(GHz) Power Gain(dB) P-1db(dBm) OIP3(dBm) PAEmax(%)
Power consumption
(mW)
3~8Ghz >16.67 8.532 23.110 15.914 70 @max PAE
Table 4-4: The specification of the PA.
0.0 2.0G 4.0G 6.0G 8.0G 10.0G 12.0G 14.0G 16.0G -30
Figure 4-17: The S-parameter of the PA.
0.0 2.0G 4.0G 6.0G 8.0G 10.0G 12.0G 14.0G 16.0G 0
Figure 4-18: The Noise Figure.
0.0 2.0G 4.0G 6.0G 8.0G 10.0G 12.0G 14.0G 16.0G 1
2 3 4 5 6 7
Frequency(Hz) Mu
Figure 4-19: The stability index: Mu.
Figure 4-20: The performance of PA in the aspect of linearity.
4.3.3 Layout of the Further Design
The layout is shown in Figure 4.21, the total size occupied by the PA is 1.073x0.927mm2, The capacitor is used metal-insulator-metal (MIM) capacitance supported by TSMC, the models of the resistor and inductor are supplied by TSMC.
The metal width is decided according to the capacity of current flow and AC signal power. Input and output pads use GSG with 50Ω.
Figure 4-21: The layout of the PA.
Chapter5 Summary
Modern wireless standards need good power efficiency or wideband for applications. However, as CMOS technology is getting scaling down, breakdown voltage is also getting lower. This trend takes challenges to the CMOS power amplifier design. In this thesis, we have presented the two designs of RF CMOS power amplifier.
One is 3.1~10.6GHz two stages power amplifier for ultra wide-band applications, by using cascode configuration with feedback and the common source with feedback.
According to the simulation result, the PA allows the maximum output power 16.7dBm, power gain 15.18dB, P1dB as 4dBm, and total current consumption 38.9mA at DC supply 1.2V and 1.8V. Since cascode configuration with feedback can increase the power gain, provide the stable wideband matching, and flatten the power gain with the 2nd stage. But the resistor-inductor feedback path does take some DC power loss; the limited and asymmetric output signal range does not succeed in suitable PAE.
Based on the previous design, we follow up studying to design a 3~8GHz power amplifier suitable for group A, group B, and group C of MB-OFDM. By using feedback configuration including inductor, resistor, and capacitor, we obtain better performance at efficiency and linearity: PAEmax is about 15.9%, P1dB is 8.5dBm, and
OIP3 is 23.11dBm. Total power consumption is 70mW with the power supply 1.8V condition. The UWB power amplifier can be used for MB-OFDM. As the 130nm and 90nm CMOS technologies using in recent days, the gain will increase and should be able to cover the entire spectrum from 3.1 GHz to 10.6 GHz. The inductor-resistor feedback configuration provides a process to design a wideband matching network, with good performance of noise and gain flatness.
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