DFT for Low-V Write-Assist Enable Method

In order to lower the write-assist enable signal to 90% VDD voltage level, we add an extra transmission gate between the External_WAEN signal and the gate terminal of M1-NMOS, WAEN. Figure 3-5 illustrates half of the WA8T cell and the corresponding DFT. The control signal of the transmission gate is both connected the TX_EN signal. The TX_EN signal would be at logic-1 level only for the test mode and logic-0 level for the normal mode. Specially, the voltage of the TX_EN is connected to the VSUPPLY, which is the overall external supply voltage (1.05V) instead of the VDD as before (0.75V). When in the test mode, only the NMOS in the transmission gate is turned on. As NMOS is not suitable for passing a logic-1 value, the voltage level of the gate terminal of M1 would be reduced by one threshold voltage (about 400mV) so that we can achieve our ideal suppressed voltage level. On the contrary, the voltage level of the gate terminal of M1 would be perfect logic-1 in the normal node because the PMOS in the transmission gate is suitable for passing logic-1 value. We can attain our target voltage level by this way.

As shown in figure 3-5, we need one transmission gate for all a-port and one transmission gate for all b-port. It means we need four transistors for overall

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Fig. 3-5 Illustration of the DFT for Low-V WAEN

Table 3-VII

Operations of Low-V Write-Assist

Operation Behavior Voltage of WAEN

TX_EN = 1 NMOS turn on and pass a

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Chapter 4 Conclusion

In this thesis, testing of Dual-Port SRAMs with the write-assist circuit is discussed. We set the experiment on 28nm technology node and simulate the disturb issues as well. We use the newest write-assist circuit as the solution to fix the disturb issue. The open defects in DP-SRAM may cause DP-SRAMs fail to operate correctly and open defects in the write-assist circuitry let DP-SRAMs fail to perform the simultaneous access operation correctly because write-assist circuit fails to suppress the write-disturb issue. Hence, it is important to develop useful methodologies to detect them for further diagnosis and information feedback. Besides, two different targets can be concluded. For DP-SRAM cells, once we detect the open defects beforehand, we can decide whether we should use dummy row or column to repair them or not depending on the cost issue and so on. For the write-assist circuitry, it is even more important. We decide whether we should fix these defects afterward or not. If the write-disturb issue is very severe in one product, it is essential to equip with the write-assist circuitry to suppress the disturbance.

We proposed several test methodologies for the hard-to-detect faults.

Half-VDD attacking method is a promising solution for the open defect on the source/drain terminal in DP-SRAM cells. Low-V write-assist method and severe read method are new test method for the write-assist circuitry. Our experiment

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results show that we can detect these open defects in a smaller resistance representing better efficiency. DFTs for each proposed method are also discussed in the last and they turn out to be an applicable structure. To sum up, the detectable resistance of open defects can be further lowered by one order to two orders in average comparing to the conventional test algorithm.

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