In modern bonding machines the actual wire bonding operation is triggered according to the coordinate values of the starting point (pad side) and ending point (lead side) of the bonding program. That is, when the coordinate values of the bonding program are set in the correct positions, the actual position of each wire will be bonded correctly (the bonding accuracy is about ±2.5 μm).
The proposed WWBP system utilizes this advantage to simulate the actual wire bonding operations for wire bonding position verification. This approach can prevent incorrect bonding before the physical wire bonding process is executed.
The proposed WWBP system first captures the image of a single leadframe unit without IC chip or any bonding wire on it. The WWBP system then labels each lead on the image with a unique pseudo code for the later simulation process. The bonding program is obtained from the bonding machine through the SEMI SECS/GEM communication protocol. Each of the [X, Y]
coordinate values for the wire bonding positions is obtained by decoding the bonding program.
Based on the captured leadframe image and the coordinate values of the wire bonding positions, the WWBP system simulates a wire bonding operation for the waiting verification machine (WVM) to calculate the end point location of each wire and obtains a numbered pseudo code for each corresponding lead. The pseudo code of each lead is compared with the CAD drawing to verify whether the wires were bonded correctly.
The entire WWBP system is composed of four parts, as illustrated in Figure 9, and is described in below.
Figure 9. Flow chart of the proposed wrong wire bonding prevention system based on CAD drawing.
3-1 Image capture, process and data pre-process
Part 1: Image capture and process.
When IC packaging foundries receive an order for a new product, different bonding or different IC chip, the R&D department will generate a CAD drawing and issue an order to the base material factory to fabricate the base material (Step 1 of Figure 4). After receiving the base material, the engineer must capture the images and process them using the following three substeps.
Part 1.1: Capture leadframe image of real leadframe and leadframe layout image from CAD drawing. The leadframe image is captured asLI(l) using a back light (see Figure 10(a)). Only the bonding area needs to be included in the image (see Figure 10(b)). Then, the leadframe layout image is captured from the CAD drawing and is filled up into every block of the leadframe. A full set of CAD drawings for the wire-bonded IC includes the leadframe layout and bonding wires in different drawing layers (Figure 10(c)). With the tool of AutoCAD, it is easy to keep the targeted drawing layer of leadframe only (Figure 10(d)). Every block of the leadframe is then captured and filled up into a solid as DI(l) (Figure 10(e)).
Part 1.2: Extract the lead information for bonding position checking.
Part 1.2.1: Because the gray-level histogram of LI(l) and DI(l) has a near-bimodal distribution, as shown in Figure 11, a valley-emphasis auto-threshold selection method [26] can be used to binary LI(l) and DI(l) into LIb(l) and
) (l DIb .
Figure 10. Capture leadframe image of real leadframe and leadframe layout image from CAD drawing.
Figure 11. Threshold selection for a leadframe IC image binarization.
Part 1.2.2: Define the calibration marks in the image. The calibration mark is used as a reference when a leadframe is moved to the bonding area that may usually shift and rotate. Ordinarily, there are four calibration marks are used in bonding position setup, two on the lead side (leadframe) and two on the pad side (IC chip). Here we only need to define the lead side calibration marks in the image. The coordinates for the two calibration marks in LIb(l) can then be determined accordingly, say IL1(XIL1,YIL1), IL2(XIL2,YIL2) from left to right, as shown in Figure 12. The coordinates for the two calibration marks in the image DIb(l) can then be determined accordingly, say IL1’(X'IL1,Y'IL1)
and IL2’( X'IL2,Y'IL2 ). In the later procedure, the coordinates of these calibration marks are used as the basis to convert the coordinates of the actual bonding positions into corresponding image coordinates.
Figure 12. Illustration of the calibration marks in the binarized leadframe image LIb(l).
Part 1.2.3: Label each solid line (lead) on the two binary images LIb(l) and DIb(l), respectively, with a separate set of pseudo codes. The pseudo code for each lead was given starting from the top-leftmost lead, clockwise, as shown in Figure 13(a). All of the pixels of the same lead (solid line) are given the same pseudo code. The labeled images LIl(l) and DIl(l) , respectively, corresponds to the binary imageLIb(l) and DIb(l). The set of pseudo codes are stored in two 2D arrays LIl(l)[x, y] and DIl(l)[x, y], where [x, y] is the coordinate value of each pixel, as shown in Figure 13(b).
Figure 13. Labeled the binary image LIb(l) as image LIl(l) from the top-leftmost lead clockwise.
Part 1.3: Stored the CAD drawing in the host computer. The engineer stored the CAD drawing into the host computer for the later bonding position verification.
3-2 Event monitor and remote control
Part 2: The wire bonding positions be adjusted.
Once the wire bonding position was changed (Step 2, Step 3, or Step 5 of Figure 9) in a modern bonding machine, an event will be sent to the host computer via the SEMI SECS/GEM communication protocol. Part 3 will be executed automatically when the host computer receives this event.
Part 3: Upload the bonding program of waiting verification machine (WVM) into the host computer.
The WWBP system will automatically upload the bonding program from the WVM via the SEMI SECS/GEM communication protocol.
3-3 Bonding process simulation and wire bonding position verification
Part 4: Correctness checking for all wire bonding positions.
Part 4.1: Simulate the actual wire bonding operation and generate the wire bonding position information for each wire with pseudo code.
The bonding position of each wire is checked using the CAD drawing, WVM bonding program and the leadframe image. A CAD drawing/bonding program contains the bonding sequence of each wire, the coordinates of the starting point and the ending point for each wire, and the calibration mark coordinates on both the leadframe and the IC chip. The following three steps will simulate the physical/actual WVM wire bonding operation to obtain the coordinate values and pseudo codes that will be bonded onto a lead.
(a) Decode the CAD drawing/bonding program into the corresponding bonding coordinates. The CAD drawing and each type of bonding machine has its own coordinate-encoding rule. Here it is decoded by using the original encoding rule and recorded it. (b) Convert the coordinates of the actual wire bonding positions into the corresponding image coordinates. (c) Obtain the pseudo code for each wire from the labeled image.
In the case of WVMs, the XY coordinates of the end point of each wire (j) are decoded and recorded as P (l XWVM−l( j) , YWVM−l( j) ) on the lead side and
P (p XWVM−p( j),YWVM−p( j)) on the pad side. The XY coordinates of the calibration marks are recorded as L1 (XWVM(L1),YWVM( L1)), L2 (XWVM( L2),YWVM( L2)) on the lead side from left to right. The end point of each wire (j) on the lead side of WVM will be mapped into the image LI (l) with the coordinate (X ,Y ) as show in Figure
14. The end point P (l XWVM−l( j),YWVM−l( j)) of a wire (j) on the lead side of the WVM will be converted into new coordinates as follows:
Figure 14. Mapping the end point coordinates of WVM wires onto the imageLIl(l).
[X ,j Y ]= [(j XIL1 + (XWVM−l( j)–XL1) × ℓx), (YIL1 + (YWVM−l( j)–YL1) × ℓy)]
Then the pseudo code in the labeled image LIl(l) can be obtained from the 2D array LIl(l)[X ,j Y ] as j LIl(l)[(XIL1 + ( XWVM−l( j)– XL1) × ℓx), (YIL1 + (YWVM−l( j)–YL1) × ℓy)].
Similarly, for CAD drawing, the XY coordinates of the end point of each wire (j) are decoded and recorded as 'P (l XCAD−l( j),YCAD−l( j)) on the lead side and
p'
P (XCAD−p( j),YCAD−p( j)) on the pad side. And the ending point pseudo code of wire (j) will be obtained from the 2D array DIl(l)[X ,j Y ]. j
To provide a better bonding capability, the R&D department might design the base material in a way for the chip to be attached with a special rotation angle (see Figure 5(a)). But the actual rotation angle of the WVM is hard to keep in high accuracy with the original design. It is necessary to calibrate the rotation bias before the bonding position comparison. The algorithms are described in the Appendix C.
Part 4.2: Compare the pseudo codes and coordinates of the pad side for each corresponding pair of wires in the CAD drawing and WVMs.
One IC packaging foundry needs several bonding machines (WVMs) to work at the same time. These WVMs must be checked one by one. This part is to follow the bonding sequence to check the corresponding pair of wires of CAD and WVM.
Theoretically, the starting point (pad side) and ending point (lead side) coordinates for a pair of corresponding CAD drawing and WVM wires should be equal.
However, there are great variations in lead positions in the leadframe-based material.
On the lead side, it is to compare the pseudo codes for a corresponding pair of CAD drawing and WVMs wires to verify whether the wire bonding positions bonded using the WVMs are correct or not. On the pad side, each point on the IC chip is practically bonded with high accuracy and low variation. The distance (D) between the CAD drawing and WVMs coordinates is then calculated. For good wire bonding it is to have the wire bonding position be controlled within a shift distance (D) which should be less than a pre-defined shift tolerance range (R). When the distance is greater than the pre-designed allowable range (R), this wire is marked as an
incorrect bond (see Figure 15). Here, R is set equal to (pad width – diameter of gold wire)/2. Then, the corresponding bonding positions of the CAD drawing and WVMs on the same pad can be guaranteed. The algorithm for the wire bonding position comparison is given below:
Figure 15. Illustration of the shiftment of a bonding point at pad side.
Algorithm: Wire bonding position comparison based on CAD drawing
Input: The pseudo code of each wire on the lead side and the XY coordinate value of every wire on the pad side
Output: The verified wire with incorrect bonding
Procedure:
For j = 1 to N do /* N is the total number of to be bonded wires */
Case lead side: /* Check the bonding positions in the lead side */
If (the pseudo code for P (l' XCAD−l( j),YCAD−l( j))–the pseudo code for P (l XWVM−l( j),YWVM−l( j)) = 0)
/* Check whether the pseudo code of P (l' XCAD−l( j),YCAD−l( j)) in
CAD is equal to the pseudo code of P (l XWVM−l( j),YWVM−l( j)) in the waiting verification machine.
All pixels of the same lead have the same pseudo code. The pixel of different lead owns different pseudo code. If the pseudo codes for the end points of a pair of wires in the corresponding CAD drawing and WVM are equal, then the corresponding wires in the same numbered lead can be located. */
Then the wire bonding has passed
Else the wire bonding has failed
End if
End case
Case pad side: /* Check the bonding positions in the pad side */
If (D < = R) then the wire bonding has passed
/* D = (XCAD−p(j) −XWVM−p(j))2 +(YCAD−p(j) −YWVM−p(j))2 ;
R = Shift tolerance range */
Else the wire bonding has failed
End if
End case
End for
End procedure
After the check, the host computer will display the comparison result and go back to Part 2 waiting for the next event.
4. Wrong wire bonding prevention system based on standard bonding program