Zero Temperature Coefficient

+ ∂

∂

∂

T V T

V α

α ^. ……… (4-4)

Among various device parameters in semiconductor technologies, the characteristics of bipolar transistors have proven the most reproducible and well-defined quantities that can provide positive and negative TC. Fig. 4-28 [4-15] shows a conceptual block diagram of bandgap ifα1 is set to one. Since the bias sources referenced to VBE(ON) and V^T have opposite temperature coefficient, output voltage Vref with almost zero TCs. In order to determine the required valueα2, the temperature coefficient of negative-TC voltage and positive-TC voltage [4-16] are analyzed in the following.

Fig. 4-28 Conceptual block diagram of bandgap

4.5.2.1 Zero Temperature Coefficient

Firstly, it was recognized that if two bipolar transistors have the different size, then the difference between their base-emitter voltages is directly proportional to the absolute temperature. For example as shown in Fig.4-29, where base currents are assumed negligible, transistor Q2 consists of n unit transistors in parallel, and Q1 is a unit transistor.

Fig. 4-29 Generation of PTAT voltage

Thus, the V_BE difference exhibits a positive temperature coefficient

For a bipolar device, we can write I_C =I_S exp(V_BE /V_T), whereV_T =kT/q. The saturation current IS is proportional toµkTn_i², where µ denotes the mobility of minority carriers and n_i is the intrinsic minority carrier concentration of silicon. The temperature dependence of these quantities is represented as µ αµ₀T^m, where m ≈ -3/2, and of the base-emitter voltage. In taking the derivative of VBE with respect to T, we must know the behavior of IC is held constant .Thus,

Equation (4-11) gives the temperature coefficient of the base-emitter voltage at a given temperature T , revealing dependence on the magnitude of V_BE itself.

with V_BE≈750mV and T =300°K, T V_BE

∂

∂ ≈−1.5 mV/°K.

We obtain the base-emitter voltage of bipolar transistors exhibits a negative TC.

With the negative-and positive-TC voltages obtained above, we can now develop a reference having a nominally zero temperature coefficient. We rewrite Vref =α₁V_BE +α₂(V_T lnn),Where V_T lnn is the difference between the base-emitter voltages of the two bipolar transistors operating at different current densities. How do we choose α 1 and α ? Since at room temperature 2 ∂V_BE/∂T ≈−1.5 mV/°K whereas ∂V_T/∂T ≈+0.087 mV/°K, we may set α =1 and choose 1 α2 lnn such that (α2 lnn)(0.087 mV/°K)=1.5 mV/°K. That is, α2lnn≈17.2, indicating that for zero TC:

Vref ≈V_BE+17.2V_T≈1.25V ........…….… (4-12)

As shown in Fig. 4-33 is a curve which is the actually variation of Vref. The difference between actually value and ideal value result from process parameter is slightly different.

4.5.2.2 Architecture

Fig 4-30, shows a bandgap structure base on the configuration, using PMOS devices to isolate the amplifier. The gates and sources of M1 / M2 are at the same potential, so the same current is forced through each side. For the amplifier to be stable, the amount of signal fed back and subtracted from the input is larger than the amount of signal fed back and added to the input. Because M1 and M2 are inverting common-source amplifiers, we want the signal fed back to the +input of the amplifier to be larger than the signal fed back to the – input of the amplifier. Since the AC currents flowing in M1 and M2 are equal and the branch containing Q2 is a higher resistance than the branch containing Q1, the Q2 branch is always connected to the +amplifier input. In the following, Vref is analyzed.

Fig. 4-30 Bandgap structure

According to Fig. 4-30 , we write down the below equations.

)

From the above equation (4-13), we can set those value which include R1, R2 and n to decide the Vref. In general, n is set to eight for layout concern. The choice of ratio of R1 to R2 will result in Vref with zero temperature coefficient.

Another important issue is the existence of degenerate bias points. As shown in Fig. 4-30, if the transistors carry zero current when the supply is turned on, they may remain off indefinitely. Called the “start-up” problem, the above issue is resolved by adding a mechanism that drives the circuit out of the degenerate bias point when the supply is turned on.

Comparing Fig.4-30, a start-up circuit has added to Fig. 4-31, where the device M9 provides a voltage path to ground upon start-up. Through M6 and M7, M9 is turned on and force M1~M4 cannot remain off. When the start-up is finished, M8 by ID5 force M9 turned off. Thus, M1~M4 is still turn on because the current for branch X and Y are built up. After start-up period, Vref will output a voltage with zero temperature coefficient. The simulation result is shown Fig. 4-32.

Fig. 4-31 Bandgap with start-up circuit

4.5.2.3 Simulation Result and Summary

The problem of start-up generally requires careful analysis and simulation. The supply voltage is ramped from zero in a dc sweep simulation. As shown in Fig. 4-32, we sweep the supply voltage for bandgap circuit from zero to Vin, and the start-up circuit is able to auto-on and auto off. As shown in Fig. 4-33, the actually variation for bandgap output is from 1.23V to 1.235V.

(a) Vin=12V (b) Vin=16V Fig. 4-32 Simulation for start-up circuit in bandgap

(a) Vin=12V (b) Vin=16V Fig. 4-33 Variation of the zero-TC

4.5.3 Pass Devices Concern

The option of pass devices of the linear regulators is typically dependent on what process (bipolar, BiCMOS, or CMOS) is to be adopted, what application is used. The specifications of the regulators in the application linear regulators can be classified based on pass device structures: NPN-Darlington, NPN, PNP, PMOS, and NMOS. Fig. 4-34 shows five topologies of serial pass devices. The primary distinctions in performances between these topologies of the pass devices are in the parameters of dropout voltage and quiescent current. Bipolar-based pass devices can typically deliver largest output currents for a given supply voltage, but require more quiescent current because they belong to current-driven devices. The driving performance of MOS-based pass devices is greatly influenced by aspect ratio and gate drive voltage. However, MOS transistors require little quiescent current because they are voltage-driven devices. The NPN Darlington pass transistor with a PNP buffer used in an NPN Darlington regulator typically requires at least 1.6 V of input-to-output voltage differential for proper work, but linear regulators usually work under the operational environment with less than 0.5 V of input-to-output voltage differential. The advantage of the NPN Darlington regulator is less drive current required compared to other BJT-based pass devices because of its high current gain. The dropout voltage of NPN Darlington regulators is described as follows:

V_drop =2V_BE +V_CE(SAT) ≅1.6~2.5V ……… (4-14)

The NPN pass device is made of a single NPN transistor driven by a PNP transistor. The dropout voltage of the NPN regulator is described as follows:

V_drop =V_BE +V_CE(SAT) ≥0.9V ……… (4-15)

The PNP pass device is a single PNP transistor, and the major advantage of PNP regulator is that PNP pass transistor can maintain output regulation with very little voltage drop across it.

The dropout voltage of the PNP regulator is described as follows:

V_drop =V_CE(SAT) ≈0.1~0.4V ……… (4-16)

(a)NPN Darlington (b)NPN (c)PNP

(d)NMOS (e)PMOS Fig. 4-34 Pass devices topologies

Fig. 4-34(d) and 4-34(e) show the MOS-based pass devices. The major advantage of NMOS regulators is its low output resistance, and hence variations of the output current will only slightly change the output voltage. The major drawback of NMOS regulators is the dropout voltage required at least larger than one gate-source voltage. The dropout voltage of NMOS regulators can be improved by using a charge pump circuit. The PMOS regulators exhibit low dropout voltages, depending on on-resistance of PMOS pass transistor and the current through the pass transistor, which is expressed as follows:

V_drop =I_out ⋅R_on ……… (4-17)

where Ron is the on-resistance of the PMOS pass transistor, Iout is the current through the pass transistor.

Table 4-4 [4-2] lists the comparison of these pass devices.

Parameter DARLINTON NPN PNP NMOS PMOS

Output Current High High High Medium Medium

Quiescent current Medium Medium Large Low Low

Dropout Vce(sat)+2Vbe V_ce(sat) +V_be V_ce(sat) V_ds(sat) +V_gs V_SD(sat)

Speed Fast Fast Slow Medium Medium

Table 4-4 Comparison of pass element devices

4.5.4

Frequency Response of Voltage Regulator

Fig. 4-35 shows a block diagram of linear regulators using conventional frequency compensation by inserting a large output capacitor with equivalent linear resistance. The error amplifier acts a gain stage in the feedback loop to provide a regulated output voltage. The buffer provides low output impedance at the gate of the output pass transistor. The output voltage of this circuit is sensed by feedback resistors Rf1 and Rf2, and fed back into one of the inputs of the error amplifier. The error amplifier compares Vref with the feedback signal Vfb

and amplifies the voltage difference of two signals. This linear regulator can control output voltage by controlling the voltage drop across the output pass transistor, which is connected in linear between the unregulated input and the load. The output pass transistor is a common-source PMOS transistor to provide output current. There are three poles and one zero in the feedback loop, which are expressed as follows:

fp1≈

Where Cout is an output capacitor, Cp1 and Cp2 are the parasitic capacitances at output nodes of the error amplifier and buffer, RO1 and RO2 are the output resistances at output node of the error amplifier and buffer, R is the output resistance of the pass transistor, R is the

equivalent linear resistance of the output capacitor, λ is the channel length modulation parameter, IL is the current through output pass transistor MOP. To achieve optimum stability, fz1 should be equal to fp2 for pole-zero cancellation, and fp3 should be placed after the unity-gain frequency of feedback loop.

From the above equations, we find the fact that the variations of the load current will change the position of fp1. As depiction in Fig. 4-36, the first pole fp1 is shifted to a higher frequency fp1＇for a higher load current, but other poles are almost fixed. Therefore, phase margin of the linear regulators will decrease with load current increasing, and linear regulators will tend to be un-stable. Moreover, the matching of fp2 and fz1 is very important for the stability of the linear regulators. Unfortunately, ESR of nowadays is too small to compensate fp2. The result makes the linear regulators tend to be unstable.

Fig. 4-35 Block diagram of linear regulator

Fig. 4-36 Frequency response of linear regulator under two different loads

4.5.5 Voltage Regulator with OTA Structure

From the previous analysis, the main problems of conventional linear voltage regulators are that the position of the pole at the output node is pushed to high frequencies with the load current increasing, and ESR is too small. Therefore, many techniquesare discussed whereby the compensating capacitor of internally compensated linear regulator. A technique for linear regulator without compensating capacitor is presented by operational transconductance amplifier (OTA) [4-14] and a buffer. Without compensating capacitor, the circuit allows to occupy less silicon area.

Fig. 4-37 shows the complete schematic of the control loop, including an error amplifier, buffer, PMOS pass transistors. Transistors included Mn1-Mn4, Mp2-Mp6 construct the error amplifier. The error amplifier with a OTA op amp is utilized to provide enough loop gain.

Fig. 4-37 Linear regulator with OTA structure

The OTA can be defined as an amplifier where all nodes are low impedance except the input and output nodes, and the design can stabilize this linear regulator under the variations of the load current. For an OTA without buffer can only drive capacitive loads. The buffer is normally presented only when resistive loads need to be driven. If the load is purely capacitive, then it is seldom included. From equation (4-18), (4-19) and (4-20) equation, we get a information which pole form. The buffer is added to acquire a fine frequency response.

The buffer provides low output impedance at the gate of the output pass transistor. By this arrangement, dominator pole must be located in output node due to output capacitor is huger than internal parasitic capacitances.

4.5.6 Simulation Result and Summary

ESR is set to 0.005Ω, output capacitor is set to 4.7µF. Output transient variation under the simulated conditions that supply voltage (Vin) changes from 12V to 16V. Fig. 4-38 shows the simulated bode plot of this linear regulator with the load current of 0µA and 100mA. From the simulation result, the phase margins are almost above 70° for min. and max. load current levels.

As shown in Fig. 4-39, the result shows the maximum output variation under a full load current change is below 50 mV for target Vout = 5V and 1.5V. According to these results, the regulator can provide the Vhalf-luminance and Vdigital-core.

(a) Vin=16V and min. load (b) Vin=16V and max. load

(c) Vin=12V and min. load (d) Vin=12V and max. load

Fig. 4-38 Simulated bode plot for loop response

(a) Vin=16V and Vout =5V (b) Vin=12V and Vout =5V

(c) Vin=16V and Vout =1.5V (d) Vin=12V and Vout =1.5V Fig. 4-39 Output variation under a full load current change

Chapter5

Conclusions and Future Work

5.1 Conclusions

The pixel of 2T1C owns the least number of TFT in all pixel structure, and has a max.

aperture-ratio comparing other pixel structure. TFT is always made from both amorphous and ploy-silicon. Poly-silicon has much higher mobility, reducing the size of the drive TFT.

Poly-silicon is always required. For poly-silicon TFT, both mobility and threshold-voltage vary randomly across the plate. Unfortunately, this structure of pixel does not compensate the variation of Vt and mobility (Up), the former two variables would lead to variation in illumination strength. Thus the driving by time ratio grayscale is adopted. Since the large voltage step is forced to pixel, it results in the reduction influence of variation of the characteristics of the driving transistor.

In this thesis, we have enhanced the luminance efficiency of conventional time ratio grayscale by increased lighting time and decreased addressing time. For decreased addressing time, shift register of sampling adopt double rate serial-in. For increased lighting time, amplitude modulation coding will reduce the number of sub-frame, and increase the lighting time. The combined method could enhance 24%. luminance. The higher luminance allows a small pixel. Small pixel will allow high resolution displays to be created. The method eliminates any unnecessary digital to analog conversions, making the OLED technology ideal for the all-digital age. Without analog circuits, driver circuits by poly-silicon TFT can be integrated to the display panel. For scan signal, the another proposed scan signal gating is developed. It also prevent from error programming issue when adjacent scan line are toggling.

5.2 Future Work

A prototype of this AMOLED driver is simulated by 0.6 um 18V CMOS technology.

Because lighting time is limited, it is suitable for the QVGA (Quarter Video Graphic Array) or below the resolution. The future work is driving an AMOLED panel by the driver chip, and find out the image performance. From the engineering evaluation, we will get much more experience for the next generation driver development. The final goals are that driver structure are integrated on the display panel and drive a bigger dimension panel. There is no analog design in driver by this method. Thus it is possible that the driving circuit is fully implemented to SOP. Without extra-chip for driver, the panel price will be reduced. The price is a key factor for competition with many kinds of displays. Besides, multi-channel data driving shift register must be used for larger panel. VGA or bigger dimension panel is also lighting.

Reference

In Chapter1

[1-1] Lawrence E. Tannas, “The Ultimate Avionics Display”, SID ’00 DIGEST, pp.

1145-1147, 2000.

[1-2] Sixto Ortiz Jr, “New monitor technologies are on display”, Computer, vol:36, pp. 13-16, 2003.

[1-3] Collins. L, “Roll-up displays: fact or fiction? “, IEE Review, Volume: 49, pp. 42–45, 2003.

[1-4] C. W. Tang, S.A. Van Slyke., “Organic electroluminescent diodes”, Appl. Phys. Lett.

Vol. 51, pp. 913-915, 1987.

[1-5] J.H. Burroughes, D.D.C. Bradley, A.R. Brown, R.N. Marks, K. Mackay, R.H. Friend, P.L. Burn, A.B. Holmes, “ Light-emitting organic electroluminescent devices based on conjugated polymers”, Nature, vol. 347, pp. 539-541,1990.

[1-6] M.T.Johnson, I.M.Hunter, N.D.Young, I.G.J.Camps, “Active matrix polyLED displays”, IDW ’00, pp. 235-238, 2000.

[1-7] Tatsuya Shimode, Mutsumi Kimura, Satoru Miyashita, “Current status and future of light emitting polymer display driven by poly-Si TFT”, SID ’99 DIGEST, pp. 372-375, 1999.

[1-8] G.Rajeswaran, M. Itoh, M. Boroson, “Active matrix low temperature poly-Si TFT/OLED full color displays: development status”, SID ’00 DIGEST, pp. 974-977, 2000.

[1-9] Y. Sakaguchi, H. Tada, T. Tanaka, E. Kitazume, K. Mori, S. Kawashima, J. Suzuki,

“Color Passive-Matrix Organic LED Display using Three Emitters”, SID ’02, pp. 1182-1185,

[1-10] S. Xiong, B. Guo, C. Wu, Y. Chen, Y. Hao, Z. Zhou, H. Yang, “A Novel Design of Sub-frame and Current Driving Method for PM-OLED”, SID ’02, pp. 1174-1176, 2002.

[1-11] A. Hunze, M. Scheffel, J. Birnstock, J. Blässing, A. Kanitz, W. Rogler, G. Wittmann, A. Winnacker, S. Rajoelson, H. Hartmann, “Passive Matrix Displays Based on the New Red Emitting Dopant RedATDBstors”, SID ’02, pp. 1186-1189, 2002.

[1-12] James L. Sanford, Frank R. Libsch, “TFT AMOLED Pixel Circuits and Driving Methods”, SID ‘03 DIGEST, pp. 10-13, 2003.

[1-13] Masuyuki Ohta, Hiroshi Tsutsu, Hiroshi Takahara, Ikunori Kobayashi, Tsuyoshi Uemura, Yoneharu Takubo, “A Novel Current Programmed Pixel for Active Matrix OLED Displays”, SID ‘03 DIGEST, pp. 108-111, 2003.

In Chapter2

[2-1] Byeong-Gyu Rohr, Tae-Joon Ahn, Jae-Young Cho, Hwan-Sool Oh, “The fabrication of green organic light-emitting-diode by evaporation process”, TENCON ’99. Proceedings of the IEEE Region 10 Conference , vol. 2 , pp. 1103-1105,1999.

[2-2] Takahisa Shimizu, Akio Nakamura, Hatsumi Komaki, Takao Minato ,Hubert Spreitzer, Jonas Kroeber “Fabrication Technique of PELD by Printing Methods” SID ’03 DIGEST, pp.

1290-1293, 2003.

[2-3] Tatsuya Shimoda , “Ink-jet Technology for Fabrication Processes of Flat Panel Displays”, SID ’03 DIGEST, pp. 1178-1181, 2003.

[2-4] G.Rajeswaran, M. Itoh, M. Boroson, “Active matrix low temperature poly-Si TFT/OLED full color displays: development status”, SID ’00 DIGEST, pp. 974-977, 2000.

[2-5] Shoustikov. A., Yujian You, Thompson, M.E. “Electroluminescence color tuning by dye doping in organic light-emitting diodes”, IEEE Journal vol.4 , pp. 3 - 13, 1998.

[2-6] G. GU, Stephen R. Forrest, “Design of flat-panel displays based on organic

light-emitting devices”, IEEE Journal of selected topics in quantum electronics, pp. 83-99, 1998.

[2-7] C. C. Wu, J. C .Sturm, R.A. Register, M. E. Thompson, “Integrated three-color organic light-emitting devices”, Appl. Phys. Lett., vol. 69, pp. 3117-3119, 1996.

[2-8] C. W. Tang, D. J. Williams, J. C. Chang, “Organic electroluminescent multicolor image display device”, U.S. Patent 5294870, 1994.

[2-9] J. Kido, M. Kimura, K. Nagai, “ Multilayer white light-emitting organic electroluminescent device”, Science, vol. 267, pp. 1332-1334, 1995.

[2-10] J. E. Littman and S. A. Vanslyke, “White light-emitting internal junction organic

[2-11] J. Kalinowski, P.Di Marco, M. Cocchi, V. Fattori, N. Camaioni, J. Duff,

“Voltage-tunable-color multilayer organic light emitting diode”, Appl. Phys. Lett., vol. 68, pp.

2317-2319, 1996.

[2-12] P.E. Bruuows, G. Gu, V. Bulovic, Z. Shen, S. R. Forrrest, M.E. Thompson, “Achieving Full-Color Organic Light-Emitting Devices for Lightweight, Flat-Panel Displays”, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 44, NO.8, pp. 1188-1202, 1997.

[2-13] J.R. Sheats, “Stacked Organic Light-Emitting Diodes in Full Color”, Science 1997 277, pp. 191-192, 1997.

[2-14] L E. Tannas, Jr., “ Flat Panel Displays and CRTs”, New York: Van Nostrand Reinhold, 1985.

[2-15] Jin Kim, J. H. Back, Giljae Lee, J. D. Noh, T. J. Kim, H. R. Ann, “A Development of Driving Chip-set and System for 1.94” Full Color PM OLED”, SID ’03 DIGEST, pp.

1127-1129, 2003.

[2-16] M.T.Johnson, I.M.Hunter, N.D.Young, I.G.J.Camps, “Active matrix polyLED displays”, IDW ’00, pp. 235-238, 2000.

[2-17] T. P. Brody et al, IEEE Trans Elec Dev, Vol ED-22, No 9, pp. 739-748, 1975.

[2-18] R.M.A Dawson, Z.Shen,D.A.Furst, S. Connor, J. Hsu, M.G. Kane, R.G. Stewart, A.Ipri,C.N.King, P.J. Green, R.T. Flegal, S.Pearson, W.A. Barrow, E. Dickey, K. Ping, C.W.Tang, S. Van Slyke, F. Chen, J. Shi, J.C. Sturm, M.H. Lu, “Design of an improved pixel for a polysilicon active-matrix organic LED display”, SID ’98 DIGEST, pp. 11-14, 1998.

[2-19] M. J. Powell, “Bias-stress-induced creation and removal of dangling-bond states in amorphous silicon thin-film transistors”, Appl. Phy. Lett. 60,2, pp. 207-209, 1992.

[2-20] Reiji HATTORI, Tsutomu TSUKAMIZU, Ryusuke TSUCHIYA, Kazunori MIYAKE, Yi HE, Jerzy KANICKI, “Current-Writing Active-Matrix Circuit for Organic Light-Emitting Diode Display Using a-Si:H Thin-Film-Transitors”, IEICE TRAN. ELECTRON., VOL.E83-C, NO.5, pp. 779-782, 2000.

[2-21] R.M.A.Dawson, Z. Shen, D.A. Futst, S. Connor, J. Hsu, M.G. Kane, R.G. Stewart, A.

Ipri, C.N. King, P.J. Green, R.T. Flegal, S. Pearson, W.A. Barrow, E. Dickey, K. Ping, S.

Robinson, C.W. Tang, S. Van Slyke, C.H. Chen, J. Shi, M.G. Lu, M. Moskewicz, J.C. Sturm,

“A polysilicon active matrix organic light emitting diode display with integrated drivers”, SID ’99 DIGEST, pp. 438-441, 1999.

“A polysilicon active matrix organic light emitting diode display with integrated drivers”, SID ’99 DIGEST, pp. 438-441, 1999.

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