Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits

7

for Yield Enhancement of Switched-Capacitor Circuits

CHIN-LONG WEY, National Chiao Tung University

JWU-E CHEN, National Central University

PEI-WEN LUO, Industrial Technology Research Institute

Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower vari-ation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimizvari-ation criterion that quickly determines if the placement is optimal. The optimization criterion leads to the devel-opment of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.

Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids—Placement and routing General Terms: Design, Algorithms, Performance

Additional Key Words and Phrases: Mismatch, common centroid, spatial correlation, process variation, variance of ratio, placement optimization, yield enhancement

ACM Reference Format:

Huang, C.-C., Wey, C.-L., Chen, J.-E., and Luo, P.-W. 2013. Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits. ACM Trans. Des. Autom. Electron. Syst. 19, 1, Article 7 (December 2013), 13 pages.

DOI: http://dx.doi.org/10.1145/2534394 1. INTRODUCTION

As semiconductor technology continues to shrink, process variation problems become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation becomes an important design issue. In order to bring the process variation to the early design stage, the process variation information must be injected to the circuit simulator.

Process corners are generally considered in circuit simulation. It uses the device pro-cess boundary to simulate the yield loss phenomenon. However, the device boundaries are usually not the performance boundary. The performance space may be within or overstep the corner space [Luo et al. 2008], which results in either overkill or overpass. To improve the accuracy of yield analysis, the time-consuming Monte-Carlo analysis is commonly employed.

Devices mismatch can be attributed to two sources of errors: random mismatch and systematic mismatch [Liu et al. 2008]. Random mismatch is usually caused by process

Authors’ addresses: C.-C. Huang (corresponding author) and J.-E. Chen, Department of Electrical ing, National Central University, Jhongli, Taoyuan, Taiwan; C.-L. Wey, Department of Electrical Engineer-ing, National Chiao Tung University, Hsinchu, Taiwan; P.-W. Luo, Industrial Technology Research Institute, Hsinchu, Taiwan; corresponding author’s email: lynden.huang@gmail.com.

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variation; on the other hand, systematic mismatch is mainly due to asymmetrical layout and processing gradients. The key performance of many analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold, is directly related to accurate capacitance ratios [McNutt et al. 1994]. The capacitance ratio mismatch problem can be alleviated by using parallel unit capacitances [Khalil et al. 2005], and the precision of the unit capacitance array can be further improved by common centroid structures [Khalil et al. 2005; Khalil and Dessouky 2002; Ma et al. 2007; Hastings 2000]. These structures significantly reduce the effects of gradients and random errors in fabrication.

Perfectly matched devices in the common centroid structure must satisfy the fol-lowing four conditions [Hastings 2000]: coincidence, symmetry, dispersion, and com-pactness. A number of layout rules were developed for guiding designers to develop an appropriate layout that meets these conditions [Khalil et al. 2005; Khalil and Dessouky 2002; Ma et al. 2007; Hastings 2000]. However, the layout shape must be rectangular to meet these four conditions. Moreover, which condition achieves better matching is gen-erally difficult to determine without performing the time-consuming yield evaluation process [Chen et al. 2009, 2010; Luo et al. 2011].

In reality, there exist some correlations among devices which highly depend on their spatial locations [Xiong et al. 2007; Doh et al. 2005]. The closer devices generally have the similar parameter variation. It has been shown that placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, and thus higher yield performance [Luo et al. 2008]. The optimization criterion was proposed in Chen et al. [2010] to quickly generate optimal/near-optimal placements with the highest/near-highest correlation coefficients for the ratio of two capacitors or a continuous capacitor ratio (multiple capacitors). The algorithm has been successfully implemented to a charge-redistribution (CR) successive-approximation register (SAR) analog-to-digital converter (ADC) design for yield enhancement [Lin et al. 2011]. The optimal/near-optimal placements were generated without the need of the Monte-Carlo simulations.

However, the optimization criteria in Chen et al. [2010] and Lin et al. [2011] were oversimplified. It may not be always true that the higher correlation coefficients result in lower variance of ratio. The use of Pearson’s correlation coefficient [Chen et al. 2010] to define the optimization criterion is too optimistic. Counterexamples will be presented shortly to illustrate the contradiction. On the other hand, the optimization criterion in Lin et al. [2011] only considers the maximization of R, the sum of cross-correlation coefficients between any pair of unit capacitance. Counterexamples will also be provided to show that placement with larger values of R may not always result in smaller standard deviation or smaller variance. This leads to the development of a new optimization criterion which can quickly and effectively identify the better placement. The resultant placement is confirmed by Monte-Carlo simulations. Based on the optimization criterion, a simple yet effective placement generation process is developed.

In the next section, the impact of spatial correlation in yield analysis and the spa-tial correction model are briefly reviewed. In addition, the optimization criterion pro-posed [Chen et al. 2010; Lin et al. 2011] is also discussed. Section 3 presents the proposed optimization criterion. Based on the optimization criterion, capacitor place-ment generation is discussed in Section 4. Finally, a brief concluding remark is given in Section 5.

2. PRELIMINARY

LetμCsandμCtbe the nominal values of two capacitors Csand Ct, respectively. Var(Cs) and Var(Ct) are respectively their variances, and Cov(Cs, Ct) is the covariance. The

variation of capacitance ratio, Var(Cs/Ct), can be expressed as follows [Luo et al. 2008]. Var  Cs Ct  = _μ Cs μCt 2 Var Cs μ2 Cs +Var Ct μ2 Ct −2Cov(Cs, Ct) μCsμCt  . (1)

Let Csand Ctbe implemented with p and q unit capacitors (UC), respectively, that is, Cs = {Cs1, Cs2, . . . , Csp} and Ct = {Ct1, Ct2, . . . , Ctq}. The ratio is Cs : Ct = p : q. Without loss of generality, the ( p+ q) UCs are placed on an m-by-n array structure. The self-correlationρ_{s(i, j)} andρ_{t(i, j)} denote as the correlation coefficients between Csi and Csj, between Cti and Ctj, respectively, while the cross-correlation ρst(i, j) is the correlation coefficients between Csiand Ctj[Luo et al. 2008]. Let Scsand Sctbe the sum of total self-correlation coefficients of Csand Ct, respectively, and Scstbe the sum of the cross-correlation coefficients, that is,

Scs= p−1  i=1 p  j=i+1 ρs(i, j); Sct= q−1  i=1 q  j=i+1 ρt(i, j); Scst= p  i=1 q  j=1 ρst(i, j). (2) Let μCu and σCu denote the nominal value and standard deviation of a UC, re-spectively. With the assumption that all UC’s have the same means and variances, Var(Cs/Ct) can be expressed as follows [Luo et al. 2008]:

Var  Cs Ct  =  p q 2_σ cu μcu 2 p+ 2Scs p2 + q+ 2Sct q2 − 2Scst pq  . (3)

Consider the Pearson’s correlation coefficient [Luo et al. 2008],

ρcst =

Cov (Cs, Ct) 

Var (Cs)Var (Ct)

. (4)

By substituting Eq. (1) to Eq. (3), we obtain

ρcst=

Scst 

( p+ 2Scs)(q+ 2Sct)

. (5)

Based on Eq. (5), the following property was concluded in Luo et al. [2008] that the higher correlation coefficientρcst results in a smaller Var(Cs/Ct). Since the smaller variance of the capacitor ratio generally results in higher yield performance, hence, the higher correlation coefficient will result in higher yield performance. Thus, the correlation coefficient ρcst was employed in Chen et al. [2010] to quickly determine which placement may achieve higher yield performance without executing the time-consuming Monte-Carlo simulations.

To deal with the continuous ratio C1:C2:. . .:CN, the ratio of multiple capacitors, sev-eral evaluation functions have been recently proposed [McNutt et al. 1994; Khalil et al. 2005; Khalil and Dessouky 2002; Ma et al. 2007]; an effective capacitor placement methodology based on spatial correlation has been proposed [Chen et al. 2010] and implemented to the design of SAR ADCs [Lin et al. 2011]. More specifically, letρi j be the correlation coefficient of a pair of capacitors, Ciand Cj. The placement optimization problem was formulated to maximize the value of R [Chen et al. 2010], where

R=ρ_ij | i, j = 1, 2, . . . , n, and i < j

. (6)

Fig. 1. A common N-bit charge redistribution SAR ADC. 3. OPTIMIZATION CRITERIA

We first present the variance analysis used to examine the optimization criteria in Chen et al. [2010] and Lin et al. [2011] for a pair of capacitance ratio and a continuous capacitance ratio. Then, the counterexamples for both criteria proposed in [Chen et al. 2010; Lin et al. 2011] are illustrated. Finally, a new optimization criterion is presented with the confirmation of Monte-Carlo simulation results.

3.1. Variance Analysis

Eq. (1) can also be written as

Var  Cs Ct  =  1 μ4 Ct  μ2 CtVar Cs+ μ 2 CsVar Ct− 2μCsμCtCov (Cs, Ct)  . (7)

Similarly, we can also obtain

Var  Ct Cs  =  1 μ4 Cs   μ2 CtVar Cs+ μ 2 CsVar Ct− 2μCsμCtCov (Cs, Ct) . (8) By Eqs. (7) and (8), one can derive

Var  Cs Ct  =  μ4 Cs μ4 Ct  Var  Ct Cs  , (9) and Var  Cs+ Ct Cs  = Var  Ct Cs + 1  = Var  Ct Cs  . (10)

Thus, the following property holds. PROPERTY1.

(a) Minimizing Var(Cs/Ct) is equivalent to the minimization of Var(Ct/Cs). (b) Minimizing Var(Cs/(Cs+ Ct)) is equivalent to the minimization of Var(Cs/Ct).

3.2. Examining Optimization CriterionR

Figure 1 shows a CR-SAR-ADC [Lin et al. 2011] which is comprised of a capacitor array, a comparator, and control units.

Consider an N-bit SAR ADC that includes the capacitors Ci, i = 0, 1, . . . , N. The capacitance ratios are

CN: CN−1:. . . : C2: C1: C0= 2N−1: 2N−2:. . . :2:1:1 (11)

Let C_i∗denote the sum of all capacitances excluding Ci, i = 1, 2, . . . , N.

Ci/(Ci+ Ci∗)= 2

Fig. 2. Placements of four-bit SAR ADC: (a) and (b) placements in Lin et al. [2011]; and (c) proposed. Table I. Standard Deviation and R

Std(Cj/Ctotal)

Placement j_{= 1} j_{= 2} j_{= 3} j_{= 4} R

Fig. 2(a) 0.0021 0.0027 0.0034 0.0049 9.3015 Fig. 2(b) 0.0021 0.0027 0.0028 0.0045 9.3199 Fig. 2(c) 0.0021 0.0027 0.0036 0.0029 9.2572

Table II. MC Simulation withμCu= 100 fF, σCu= 10 fF,

andρ0= 0.9 Std(Cj/Ctotal) Placements j= 1 j= 2 j= 3 j= 4 Fig. 2(a) 0.0022 0.0028 0.0035 0.0050 Fig. 2(b) 0.0022 0.0028 0.0028 0.0046 Fig. 2(c) 0.0022 0.0027 0.0037 0.0029

By Property 1(b), minimizing Var(Ci/(Ci+Ci∗)) is equivalent to the minimization of Var(Ci/Ci∗).

Example 1. Consider the placements [Lin et al. 2011] in Figures 2(a) and 2(b) with

continuous ratio C4:C3:C2:C1:C0= 8:4:2:1:1. The unit capacitor Cuis 100 fF, the stan-dard deviation of unit capacitor is 10 fF, and the unit correlation coefficientρ0is 0.9.

One can generate a 16-by-16 correlation coefficient matrix [Luo et al. 2008] and calculate the variance and covariance of the capacitances. For the placement in Fig-ure 2(c), C₄∗ = C0 + C1 + C2 + C3 and CTotal = C4 + C4∗. By Eq. (2), we obtain

Var(C4) = Var(C₄∗) = 5228.5, and Cov(C4, C₄∗) = 5186.6. By Eq. (3), the variance of

ratio Var(C4/CTotal) = 8.1913e-6. Thus, the standard deviation is Std(C4/CTotal) is 0.0029. Similarly, one can compute the standard deviations of C1/CTotal, C2/CTotal, and C3/CTotal, and the R values for the placements, as shown in Table I. The mean values of C1/CTotal, C2/CTotal, C3/CTotal, and C4/CTotalare 0.0625, 0.125, 0.25, and 0.5, respectively. Note that, for simplicity, the systematic mismatch was ignored because the array size is small and the capacitors, (C2, C3, C4), with even numbers of unit

capacitors, have the common center point.

Similarly, one can derive the standard deviations of the other placements, as shown in Table I. Results show that both placements in Figures 2(a) and 2(b) have higher values of R than that in Figure 2(c), so is the standard deviation of the most significant bit (MSB), that is, C4/CTotal. The situation becomes significant when the bit number increases.

In order to confirm the correctness of the computed values in Table I, the Monte-Carlo (MC) simulation was conducted to compute the variance. With 10,000 samples, the simulation results are tabulated in Table II.

Fig. 3. Common-centroid-based placements. Table III. Calculated Values withρ0= 0.5

Placements p+ 2Scs q+ 2Sct 2Scst ρcst Var(Cs/Ct)

Fig. 3(a) 4.4224 160.7778 28.4144 0.5328 5.7042E-5 Fig. 3(b) 5.8288 142.1754 45.6104 0.7922 3.2203E-5 Fig. 3(c) 8.9254 138.2296 46.4596 0.6613 7.4696E-5 3.3. Examining Optimization Criterionρcst

Let Csand Ctbe implemented with 4 and 26 unit capacitors which are placed on a 6-by-5 array structure, that is, p= 4 and q = 26, Figure 3 shows three different placements and the associated values are computed and tabulated in Table III, whereμCu= 100 fF,σCu= 10 fF and the ρ0 = 0.5 were assumed. Results show that the placement in

Figure 3(b) results in the highest correlation coefficientρcst and the lowest variance of ratio, Var(Cs/Ct). This endorses that the placement with higher correlation coefficient results in lower variance of ratio [Luo et al. 2008].

However, for the placements in Figures 3(a) and 3(c), the former has lowerρcstthan the latter, by the conclusion [Luo et al. 2008], the former should have higher variance of ratio than the latter. By Table III, the former one has lower Var(Cs/Ct). This contradicts the conclusion in Luo et al. [2008]. In fact, to obtain higherρcst, by Eq. (5), the terms ( p+ 2Scs)∗(q+ 2Sct) must be reduced, and the term Scstshould be increased. Moreover, to obtain lower Var(Cs/Ct), by Eq. (3), both ( p+ 2Scs) and (q+ 2Sct) must be decreased and Scstshould be increased. Both conditions may not be linearly dependent. Therefore, the criterion may not be always true. To further verify the simulation results of the example, the MC simulation with 10,000 samples is adopted for variousρ0, as shown

in Figure 4.

As shown in Figure 4, the placement in Figure 3(a) has lower Var(Cs/Ct) than Figure 3(c). In addition, Figure 4 also confirms the accuracy of the estimated vari-ance that is calculated by Eq. (3).

3.4. New Optimization Criterion

This sub section presents the proposed optimization criterion.

PROPERTY2. Let Csand Ctbe implemented with p and q unit capacitors, respectively,

and let the (p+ q) unit capacitors be completely placed on an n-by-m array. The sum κ = (p + 2Scs)+ (q + 2Sct)+ 2Scst (13)

is a constant for any placements of the (p+ q) units on this array.

Example 2. Consider the two different placements in Figures 5(a) and 5(b), where p= q= 4 on a 2-by-4 array structure. Their correlation matrices are shown in Figures 5(c)

Fig. 4. MC simulation results of the placements in Figure 3.

Fig. 5. Common-centroid placements.

Based on the correlation matrices in Figure 5, the correlation coefficients of both cases can be expressed as follows.

Scs(a)= Sct(a)= 2ρ2+ 3ρ √ 2_{+ ρ}√10_, Scst(a)= 10ρ + 2ρ3+ 4ρ √ 5_, Scs(b)= Sct(b)= ρ + ρ3+ 2ρ √ 2_{+ 2ρ}√5_, Scst(b)= 8ρ + 4ρ2+ 2ρ √ 2_{+ 2ρ}√10_.

Let k(a) be the coefficient sum of all entries of the matrix in Figure 5(c), then

κ(a) = (p + 2Scs(a))+ (q + 2Sct(a))+ 2Scst(a)

= 8 + 20ρ + 8ρ2_{+ 4ρ}3_{+ 12ρ}√2_{+ 8ρ}√5_{+ 4ρ}√10_.

Similarly, letκ(b) be the coefficient sum of all entries of the matrix in Figure 5(d), and

κ(b) = 8 + 20ρ + 8ρ2_{+ 4ρ}3_{+ 12ρ}√2_{+ 8ρ}√5_{+ 4ρ}√10_,

that is,κ(b) = κ(a). For ρ = 0.5, κ(a) = κ(b) = 25.3686. The matrix in Figure 5(d) is a matrix permutation of that in Figure 5(c). Thus, the total sums of the correlation coefficients for both cases are the same.

PROOF(PROPERTY2). If two placements have the same number of ( p+ q) unit

capaci-tors which are placed on the same array, their corresponding correlation matrices have the permutation relationship, that is, one matrix can be obtained from a permutation of the other. Thus, the total sums of the correlation coefficients at all entries in both matrices are the same.

Based on Property 2, a new optimization criterion can be summarized as the following property.

PROPERTY 3. Given an n-by-m array, both capacitors Cs and Ct contain p and q unit capacitors, respectively. Among the placements on the same array, the one with the lowerω-value will result in the lower variation of ratio,

ω = Scs

p + Sct

q . (14)

PROOF. Eqn. (3) can be rewritten as

Var (Cs/Ct)= G1∗ (G2+ 2G3), where G1=  p q 2_σ cu μcu 2 , G2=  1 p+ 1 q  , G3= Scs p2 + Sct q2 − Scst pq,

Note that p, q, σCu, and μCu are constants as are G1 and G2. Thus, minimizing

Var(Cs/Ct) is equivalent to the minimization of G3. By Eq. (13), we can derive

κ − p − q 2 = Scs+ Sct+ Scst, or Scst= κ − p − q 2 − (Scs+ Sct). Thus, G3= Scs p  1 p+ 1 q  + Sct q  1 p+ 1 q  −(κ − p − q)/2 pq , that is, Scs p + Sct q =  G3+ (κ − p − q)/2 pq    1 p+ 1 q  .

Since p, q, andκ are constants, minimizing G3 is equivalent to the minimization of

By Eq. (13), we have Scs p + Sct q = p(κ − p − q)/2 + (q − p)Scs− pScst pq = p(κ − p − q)/2 + (p + q)Scs− p(p + 2Scs+ Scst)+ p2 pq = κ − q + p 2q +  1 p+ 1 q  Scs− 1 q  _p  i=1 f (ri, si)  = κ − q + p 2q + 1 q  q p+ 1  Scs− p  i=1 f (ri, si)  ,

where (ri, si), i= 1, 2, . . . , p, are the locations of the p unit capacitors of Cs. Let (r, s) be any entry of the n-by-m array,

f (r, s) = n  i=1 m  j=1 ρ√(r−i)2_{+(s− j)}2 . (15)

The function f (r, s) is referred to as the weight of the entry (r, s) on the n-by-m array [Chen et al. 2009, 2010; Luo et al. 2011]. This concludes that minimizingω in Eq. (14) is equivalent to the minimization ofωp, where

ωp=  q p+ 1  Scs− p  i=1 f (ri, si), or ωp= n× m p Scs− p  i=1 f (ri, si), (16) that is, minimizing the variance of ratio is equivalent to the minimization ofωp.

4. OPTIMAL COMMON-CENTROID PLACEMENTS

Consider an array size of 2R_{by 2}C_{, without loss of generality, let C  R. Both} capaci-tances Csand Ctcontain p and q unit capacitances, respectively, where p+ q = 2R+C.

Let (ri, si), i = 1, 2, . . . , p, be the locations of the p unit capacitors of Cs on the array. By Eq. (16), ωp= 2R+C p Scs− p  i=1 f (ri, si). (17) Thus, for p= 1, we have Scs = 0 and, by Eq. (17), ω1 = − f (r1, s1). Minimizingω1is

equivalent to the maximization of f (r1, s1).

The entry weights of the 8-by-8 array are illustrated in Figure 6(a), where there are ten distinct entry weights, w1–w10, which can be calculated by Eq. (15), and the computed values for ρ0 = 0.5 are listed in Figure 6(b), where the maximum entry

weight w1= 10.7038.

We denote the entry/entries located at the center of the array as central entry/entries, or C-entry or C-entries. Figure 6 shows that array containing four C-entries, labeled by w1 and colored in yellow. Figure 6(b) shows that the C-entries have the highest entry

Fig. 6. Computed entry weights.

weight. (The maximum entry weight was defined in Chen et al. [2009, 2010] and Luo et al. [2011] in a similar way.) Thus, the following property holds.

PROPERTY4. Let p= 1, a placement is generated in such a way that the only one-unit

capacitor of Cs is placed on the C-entry/C-entries of the array, and the q unit capacitors of Ct are placed on the remaining entries of the array. Then, the placement results in the lowest variation of ratio among the placements on the same array.

PROOF. For p = 1, S_cs = 0. Thus, by Eq. (17), w₁ = − f (r, s). Since f (r, s) is the

highest entry weight of the array, the maximum of f (r, s) results in the lowest w1and

corresponding variation of ratio.

For p= 2, let (r1, s1) and (r2, s2) be the locations of the two unit capacitors of Cs on the 2R_-by-2C_{array. By Eq. (17), we obtain}

ω2= 2R+C−1Scs− [ f (r1, s1)+ f (r2, s2)]. (18)

Consider the 8-by-8 array of p= 2. We partition array into two 8-by-4 subarrays, as shown in Figure 7(a). The two unit capacitors for Cswill be respectively placed on the C-entries, marked in yellow, of both subarrays. Similarly, for p= 4, let (ri, si), i= 1,2,3,4 be the locations of the two unit capacitors of Cson the 2R-by-2Carray. By Eq. (17), we obtain

ω4= 2R+C−2Scs− [ f (r1, s1)+ f (r2, s2)+ f (r3, s3)+ f (r4, s4)]. (19)

Figure 7(b) shows that an 8-by-8 array is partitioned into four 4-by-4 subarrays. The

C-entries are colored in yellow.

Note that the partitioned subarrays are either the square or rectangular shapes. With the C-entries, the placements meet the rules of compactness, symmetry, and

dispersion. If the C-entries near the center are chosen, the placements will meet the

rule of coincidence.

Placing two unit capacitors on two subarrays, each having four entries, will result in 16 combinations, referred to as candidate placements. This has demonstrated that the searching space for optimal placements is significantly reduced from the number of 2-out-of-64, C(64,2)= 2016, to C(4,1)∗2= 16, for the 8-by-8 array. In fact, due to the symmetry of the array, the 16 candidate placements can be categorized into only six distinct placements, as shown in Figure 8, where the p= 2 unit capacitors are placed

Fig. 7. 8-by-8 array.

Fig. 8. 8-by-8 array with p= 2.

on the locations marked in green. By the rules of common centroid, symmetry, and dispersion, the placements in Figures 8(a)–8(c) will never be the optimal placements.

By Eq. (18), we can easily find that the placements in Figures 8(a) and 8(d) have the same value of [ f (r1, s1)+ f (r2, s2)]. However, the placement in Figure 8(d) has lower

Scs than that in Figure 8(a) thus resulting in lowerω2. Similarly, for the pairs of the

placements in Figures 8(b) and 8(e) and those in Figures 8(c) and 8(f), the placement in Figure 8(e) (Figure 8(f)) has lower ω2 than that in Figure 8(b) (Figure 8(c)). In

addition, lower Scs is also caused by placing the two unit capacitors on the locations with larger distance. The placements in Figures 8(d)–8(f) meet the rules of dispersion and symmetry of common centroid.

Figure 9(a) shows the curve family for all possible placements. The optimal placement is the one in Figure 8(f). Figure 9(b) compares the variances of ratio for the placements with the patterns in Figures 8(d)–8(f). Results show that the one in Figure 8(d) is the optimal solution forρ0= 0 to 0.5, while the one in Figure 8(e) is the optimal solutions for

ρ0> 0.8. Thus, the candidate placements in Figures 8(d)–8(f) are optimal/near-optimal

solutions depending upon the values ofρ0.

Similarly, Figure 10(a) shows a 4-by-4 array which is partitioned into four subarrays. Figure 10(b) illustrates a candidate placement. Figure 10(c) plots the variances of ratio with ρ0 = 0 to 1 for all possible placements for placing p = 4 to this 4-by-4 array.

Fig. 9. 8-by-8 array with p= 2.

Fig. 10. 4-by-4 array with p= 4. 5. CONCLUSION

The yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. In practice, however, a circuit generally includes several design variables which are treated as random variables when taking the process variation into consideration. Thus, the variance of the random variables may affect the circuit yield.

The placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion which can significantly reduce the searching space for finding the optimal/near-optimal solutions for a sufficiently large array size. It should be mentioned that routability of the resulting array is also an important issue to be addressed. A simple routing scheme has been proposed in Huang et al. [2011]; however, systematically considering both placement and routing of the capacitor array is being developed for further yield enhancement.

The concept of C-entries of the partitioned subarrays plays an important role for au-tomatically generating the optimal/near-optimal common-centroid capacitor placement on a reasonably large array. The concept of the C-entries and partitioned subarrays significantly reduces the searching space for the optimal solutions. Even though the

preceding discussions place the emphasis on the 2R_-by-2C_{array, the concept of C-entries} can be applied for any array size. A simple yet effective automatic placement gener-ation process is being developed [Huang to appear], where partitioning and merging schemes are being implemented to meet the rules of coincidence, dispersion, symmetry, and compactness.

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