DOI 10.1007/s00339-013-7900-3
Improved performances in low-voltage-driven InGaZnO thin film
transistors using a SiO
2
buffer layer insertion
Z.W. Zheng· Y.C. Chen
Received: 6 June 2013 / Accepted: 30 July 2013 / Published online: 28 August 2013 © Springer-Verlag Berlin Heidelberg 2013
Abstract In this paper, we report the device characteris-tics of indium gallium zinc oxide (IGZO) thin film tran-sistors (TFTs) with high-κ lanthanum aluminate (LaAlO3) based gate insulators. The IGZO TFT with single LaAlO3 gate insulator has an operation voltage as low as 1.5 V but suffers a low on-off-state drive current ratio (Ion/Ioff) of 1× 103, a large subthreshold swing (SS) of 0.405 V/dec and a small field effect mobility (μFE) of 0.84 cm2/V sec. Inserting a SiO2buffer layer between IGZO active channel layer and LaAlO3gate insulator results in a reduced effec-tive dielectric constant but with significant improved char-acteristics including a high Ion/Ioffof 6.2× 104, a small SS of 0.113 V/dec and a large μFEof 5.2 cm2/V sec. Such good performances can be attributed to the lowered gate leakage and reduced interface trap issue owing to the smooth SiO2 buffer layer insertion.
1 Introduction
At the rapid growth of flat panel display market, oxide thin film transistors (TFTs) [1–14] have attracted much attention as emerging devices that exhibit higher mobility compared to the conventional amorphous or polycrystalline silicon TFTs [15–17] and organic TFTs [18–21]. Among various oxide TFTs, ZnO-based TFTs [1–14], especially indium gal-lium zinc oxide (IGZO) TFTs [4–14], have been considered
Z.W. Zheng (
B
)Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
e-mail:[email protected]
Y.C. Chen
Institute of Photonic System, National Chiao Tung University, Hsinchu 300, Taiwan
as potential candidates for flexible display applications, due to their advantages of low production cost, high mobility, excellent uniformity, good optical transparency, etc. How-ever, the currently developing IGZO TFTs still suffer large operation voltage and low device mobility. In addition, low threshold voltage (Vt) and small subthreshold swing (SS) are also needed for high-speed operation. To solve these issues, improving the properties of active channel material in the fabrication process [7–9], such as IGZO thickness, channel composition, provides an alternative solution. Apart from the active channel layer material, the insulating material is also of great significance for high-performance TFTs. It is well known that gate dielectrics with high dielectric constant and small surface roughness allow the TFTs to have low op-eration voltages, because the high carrier density in the ac-tive channel layer could be induced at a relaac-tively low volt-age bias compared to traditional dielectrics and polymer in-sulators. Therefore, incorporating high-κ gate materials into TFTs has been widely applied to improve the device perfor-mances [17–19].
In this paper, we report the device performances of IGZO TFTs with high-κ lanthanum aluminate (LaAlO3) [17–19, 22] based gate dielectrics. Due to the high dielectric con-stant, large energy bandgap and high thermal stability of LaAlO3 dielectric, low threshold voltage (Vt) and low op-eration voltage can be achieved in the LaAlO3-based TFTs. However, LaAlO3 dielectric still suffers interfacial issue that degrades the electron mobility as reported in the liter-ature [22]. To solve this problem, using a SiO2buffer layer inserted between the IGZO active channel layer and LaAlO3 gate insulator, improved device performances are achieved as compared to the TFTs with single LaAlO3 gate dielec-tric, including a higher Ion/Ioffof 6.2× 104, a smaller SS of 0.113 V/dec and a larger μFEof 5.2 cm2/V sec. Such good characteristics can be attributed to lowered gate leakage
cur-rent and reduced interfacial issue with a SiO2buffer layer in-sertion [10–12,20,21,23]. The present results demonstrate that IGZO TFTs with stacked LaAlO3/SiO2gate dielectrics show high potential for future high-speed and low-power ap-plications.
2 Experimental details
Figure1(a) and (b) shows the schematic structure and photo-graph of the IGZO TFT with device microphoto-graph in the inset, respectively. The top-contact bottom-gate type IGZO TFTs
Fig. 1 (a) Schematic structure and (b) photograph of the IGZO TFT with device micrograph in the inset
were prepared on the 300-nm thick insulating SiO2grown on 4-inch silicon substrates with a shadow mask process. A 50-nm thick TaN bottom gate (G) electrode was formed by physical vapor deposition (PVD) and patterned. Then, a 30-nm thick LaAlO3and 10-nm thick SiO2were deposited by e-beam evaporation at room temperature, followed by an-nealing in O2ambient at 400◦C to improve the gate oxide properties. Subsequently, a 40-nm thick IGZO active layer was deposited using dc reactive sputtering from an IGZO target under Ar ambient mixed with O2gas. Finally, 300-nm thick Al was thermally coated to form source (S) and drain (D) electrodes, followed by N2sintering at 300◦C to reduce contact resistance. The devices have a channel width (W ) of 500μm and a channel length (L) of 50μm. The metal– insulator–metal (MIM) capacitors of gate dielectrics were also fabricated side-by-side to characterize the gate capaci-tance and leakage current. For comparison, the TFT devices without SiO2 buffer layer were also fabricated as control samples. The gate insulators were characterized by atomic force microscopy (AFM) analysis. The electrical character-istics of TFT devices were measured at room temperature using HP4156C semiconductor parameter analyzer.
3 Results and discussion
Figure2shows the capacitance–voltage (C–V ) characteris-tics of the Al/[with and without SiO2buffer layer]/LaAlO3/ TaN gate capacitors on the same substrate, with the current density–voltage (J –V ) characteristics in the inset. A high capacitance density for gate dielectrics is needed to induce a large carrier density at a relatively low operation voltage. The high capacitance density of 62 and 23 fF/μm2 mea-sured at 100 kHz is obtained for the MIM capacitors without and with SiO2buffer layer, respectively, as shown in Fig.2.
Fig. 2 C–V characteristics of Al/[with and without SiO2 buffer
layer]/LaAlO3/TaN gate capacitors on the same substrate, with J –V
2
It indicates the equivalent oxide thickness (EOT) of ∼5.5 and∼15 nm for single LaAlO3 and stacked SiO2/LaAlO3 gate dielectrics, respectively. The high dielectric constant of ∼21 can be extracted for LaAlO3 dielectric, while the reduced effective dielectric constant of ∼10.4 is obtained for SiO2/LaAlO3gate stack. Although the insertion of SiO2 buffer layer decreases effective gate capacitance and effec-tive dielectric constant, the structure reduces the gate leak-age current density (1.1× 10−7A/cm2@−1.5 V) further by more than one order of magnitude as compared to the sin-gle LaAlO3structure (2.7× 10−6A/cm2@−1.5 V) in the inset of Fig. 2. This smaller gate leakage by introducing a SiO2buffer layer could reduce the off-current level in TFT devices and improve the Ion/Ioff, indicating that the inser-tion of SiO2buffer layer is a powerful solution for lowering off-state power [10–12,20,21,23], in contrast to single in-sulator.
Since the surface morphology of the gate dielectrics is very critical to device performances [12–14,21], the surface roughness of the LaAlO3gate insulators on bottom TaN gate without and with SiO2buffer layer was examined by AFM analysis, as shown in Fig.3(a) and (b), respectively. Smooth surfaces of single LaAlO3 and stacked SiO2/LaAlO3 di-electrics with root mean square (RMS) roughness of 0.572 and 0.590 nm are obtained, respectively. The difference in RMS roughness between single LaAlO3and SiO2/LaAlO3 stack is just 0.018 nm, which is much smaller than atomic scale. It indicates that there is no degraded roughness af-ter the deposition of SiO2buffer layer. Moreover, the SiO2 buffer layer prevents the carriers moving into the gate di-electric, due to the lager conduction band offset (Ec) of
4.3 eV between SiO2 and IGZO channel as compared to that of 2.1 eV between LaAlO3 and IGZO channel [24– 26], as shown in the energy band diagram in Fig. 4. This smooth surface with proper Ec as a barrier between the
gate dielectric and channel is preferred and favorable to be flat gate stack to prevent gate leakage, especially for bottom-gate TFT structures.
Figures5(a) and (b) displays the output Id–Vdand trans-fer Id–Vg characteristics of the IGZO TFT without SiO2 buffer layer, respectively. This TFT device behaves as in enhancement mode with good saturation characteristics and can be operated under the voltage bias as low as 1.5 V in Fig.5(a), indicating that incorporating high-κ LaAlO3 di-electric can give an advantage of lowering the operation voltage. From the measured results, the IGZO TFT with sin-gle LaAlO3 insulator shows a low Vt of 0.36 V extracted from the linear Id1/2–Vg curve in Fig. 5(b) but suffers a low Ion/Ioff of 1× 103, a large SS of 0.405 V/dec, which can be calculated from Id–Vg curve in Fig. 5(b). Besides, a small μFE of 0.84 cm2/V sec is obtained according to the extraction from a gradual channel approximation in the lin-ear region using the equation of μFE= (∂Id/∂Vg)·(L/W)/
Fig. 3 AFM images of (a) single LaAlO3 and (b) stacked
LaAlO3/SiO2gate insulators on bottom TaN gate
(Vd·Cg), where Id, Vd, Vgand Cgare the drain current, drain voltage, gate voltage and gate insulator capacitance per unit area, respectively [27].
To further improve the performances of the IGZO TFTs, a SiO2 was inserted as buffer layer at the interface of IGZO/LaAlO3. The output Id–Vd and transfer Id–Vg char-acteristics of the IGZO TFT with inserted SiO2buffer layer are shown in Fig.6(a) and (b), respectively. Using a SiO2 buffer layer, the IGZO TFT device exhibits improved per-formances including a high Ion/Ioff of 6.2× 104, a small
SS of 0.113 V/dec and a large μFE of 5.2 cm2/V sec with a low Vtof 0.27 V. The comparison of the TFT parameters is provided in Table1, indicating that SiO2buffer layer inser-tion is necessary for stable operainser-tion of the TFT. Although the effective dielectric constant of gate stack decreased with
Table 1 Important transistor parameters for the IGZO TFTs without and with SiO2buffer
layer Insulator Operation voltage (V) Vt(V) Ion/Ioff SS (V/dec) μFE (cm2/V sec) Nmax (cm−2) LaAlO3 1.5 0.36 1× 103 0.405 0.84 2.2× 1013 LaAlO3/SiO2 1.5 0.27 6.2× 104 0.113 5.2 1.3× 1012
Fig. 4 Energy band diagram of gate stack for the IGZO TFT
addition of the SiO2buffer layer, the device performances have been greatly improved. It can be attributed to the low-ered gate leakage and reduced interfacial issue caused by SiO2 insertion [10–12,20,21,23]. The off-current of the TFT device decreases after the SiO2 buffer layer deposi-tion and thus improves the Ion/Ioff, which agrees with the small gate leakage for SiO2/LaAlO3gate stack. On the other hand, the performances of TFTs are strongly influenced by the interface trap states at the interface between the active channel and gate insulator, since the field-induced carriers are confined to a very thin region close to the interface. The interface defects can produce trapping or scattering ef-fects, leading to the degradation of μFE and SS. From SS, we can infer the maximum density of surface states at the gate dielectric/IGZO channel interface, according to the SS equation [12]: Nmax= [SS · log(e)/(kT /q) − 1] · (Cg/q). Here, k is the Boltzmann constant, T is absolute tempera-ture, q is charge quantity of an electron. The Nmax is cal-culated to be∼2.2 × 1013 cm−2for the TFT device with-out SiO2 buffer layer insertion, while much lower Nmaxof ∼1.3 × 1012 cm−2for the TFT device after inserting SiO2 buffer layer. It is well known that the TFT performances are greatly governed by the surface states at the interface. Due to the interfacial issue caused by LaAlO3 [22], inserting a smooth SiO2 buffer layer evaporated at room temperature without sputtering plasma damage can effectively passivate
Fig. 5 (a) Output Id–Vdcharacteristics and (b) transfer Id–Vg
charac-teristics of the IGZO TFT without SiO2buffer layer
high-κ surface and reduce interface states near the IGZO ac-tive channel layer [10–12], resulting in the improvement of
μFEand SS. A very small SS of 0.113 V/dec was achieved, close to the theoretical minimum value of 0.060 V/dec at room temperature, which indicates low interface trap den-sity using a SiO2buffer layer insertion.
4 Conclusions
We demonstrate improved performances in IGZO TFTs us-ing a SiO2 buffer layer inserted between the IGZO active channel layer and high-κ LaAlO3gate insulator. Good TFT device characteristics are achieved simultaneously, includ-ing a low Vtof 0.27 V, a good Ion/Ioffof 6.2× 104, a small
2
Fig. 6 (a) Output Id–Vdcharacteristics and (b) transfer Id–Vg
charac-teristics of the IGZO TFT with SiO2buffer layer
SS of 0.113 V/dec and a large μFE of 5.2 cm2/V sec at op-eration voltage as low as 1.5 V. Such good performances were attributed to the lowered gate leakage and reduced in-terfacial issue caused by SiO2buffer layer insertion. These present results show that low-voltage-driven IGZO TFTs with stacked LaAlO3/SiO2 as gate insulators have a great promise for future high-speed and low-power applications.
Acknowledgements The authors would like to thank Prof. A. Chin from National Chiao Tung University and Dr. C.H. Cheng from Na-tional Taiwan Normal University for their support and technical help in experiments.
References
1. R.L. Hoffman, B.J. Norris, J.F. Wager, Appl. Phys. Lett. 82, 733 (2003)
2. B. Yaglioglu, H.Y. Yeom, R. Beresford, D.C. Paine, Appl. Phys. Lett. 89, 062103 (2006)
3. N.L. Dehuff, E.S. Kettenring, D. Hong, H.Q. Chiang, J.F. Wager, R.L. Hoffman, C.H. Park, D.A. Keszler, J. Appl. Phys. 97, 064505 (2005)
4. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Nature 432, 488 (2004)
5. E. Fortunato, P. Barquinha, R. Martins, Adv. Mater. 24, 2945 (2012)
6. J.C. Park, H.N. Lee, IEEE Electron Device Lett. 33, 818 (2012) 7. H. Yabuta, M. Sano, K. Abe, T. Aiba, T. Den, H. Kumomi, K.
No-mura, T. Kamiya, H. Hosono, Appl. Phys. Lett. 89, 112123 (2006) 8. S.Y. Huang, T.C. Chang, M.C. Chen, S.W. Tsao, S.C. Chen,
C.T. Tsai, H.P. Lo, Solid-State Electron. 61, 96 (2011)
9. S.Y. Lee, D.H. Kim, E. Chong, Y.W. Jeon, D.H. Kim, Appl. Phys. Lett. 98, 122105 (2011)
10. J.H. Na, M. Kitamura, Y. Arakawa, Appl. Phys. Lett. 93, 063501 (2008)
11. H.H. Hsu, C.Y. Chang, C.H. Cheng, IEEE Electron Device Lett. 34, 768 (2013)
12. F. Zhou, H.P. Lin, L. Zhang, J. Li, X.W. Zhang, D.B. Yu, X.Y. Jiang, Z.L. Zhang, Curr. Appl. Phys. 12, 228 (2012) 13. Y.J. Cho, J.H. Shin, S.M. Bobade, Y.B. Kim, D.K. Choi, Thin
Solid Films 517, 4115 (2009)
14. H.H. Hsu, C.Y. Chang, C.H. Cheng, Appl. Phys. A 112, 817 (2013)
15. C.W. Chen, T.C. Chang, P.T. Liu, H.Y. Lu, K.C. Wang, C.S. Huang, C.C. Ling, T.Y. Tseng, IEEE Electron Device Lett. 26, 731 (2005)
16. K.M. Chang, W.C. Yang, C.P. Tsai, IEEE Electron Device Lett. 24, 512 (2003)
17. B.F. Hung, K.C. Chiang, C.C. Huang, A. Chin, S.P. McAlister, IEEE Electron Device Lett. 26, 384 (2005)
18. M.F. Chang, P.T. Lee, S.P. McAlister, A. Chin, IEEE Electron De-vice Lett. 29, 215 (2008)
19. M.F. Chang, P.T. Lee, S.P. McAlister, A. Chin, IEEE Electron De-vice Lett. 30, 133 (2009)
20. M. Kitamura, Y. Arakawa, Appl. Phys. Lett. 89, 223525 (2006) 21. J.H. Na, M. Kitamura, D. Lee, Y. Arakawa, Appl. Phys. Lett. 90,
163514 (2007)
22. I.Y.K. Chang, S.W. You, P.C. Juan, M.T. Wang, J.Y.M. Lee, IEEE Electron Device Lett. 30, 161 (2009)
23. G. Wang, D. Moses, A.J. Heeger, H.M. Zhang, M. Narasimhan, R.E. Demaray, J. Appl. Phys. 95, 316 (2004)
24. H. Cho, E.A. Douglas, B.P. Gila, V. Craciun, E.S. Lambers, F. Ren, S.J. Pearton, Appl. Phys. Lett. 100, 012105 (2012)
25. L.F. Edge, D.G. Schlom, S.A. Chambers, E. Cicerrella, J.L. Freeouf, B. Hollander, J. Schubert, Appl. Phys. Lett. 84, 726 (2004)
26. J. Robertson, Rep. Prog. Phys. 69, 327 (2006)
27. S.M. Sze, K.K. Ng, Physics of Semiconductor Devices, 3rd edn. (Wiley, New Jersey, 2007), p. 308
