High density and low leakage current in TiO(2) MIM capacitors processed at 300 degrees C

IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST 2008 845

High Density and Low Leakage Current in

TiO

₂

MIM Capacitors Processed at 300

◦

C

C. H. Cheng, S. H. Lin, K. Y. Jhou, W. J. Chen, C. P. Chou, F. S. Yeh, J. Hu, M. Hwang, T. Arikado,

S. P. McAlister, Senior Member, IEEE, and Albert Chin, Senior Member, IEEE

Abstract—We report Ir/TiO

2

/TaN metal–insulator–metal

ca-pacitors processed at only 300

◦

C, which show a capacitance

density of 28 fF/µm

2

_{and a leakage current of 3}

_{× 10}

−8

₍₂₅

◦

_C)

or 6

× 10

−7

(125

◦

C) A/cm

2

at

−1 V. This performance is due

to the combined effects of 300

◦

C nanocrystallized high-κ TiO

2

,

a high conduction band offset, and high work-function upper

electrode. These devices show potential for integration in future

very-large-scale-integration technologies.

Index Terms—High κ, Ir, metal–insulator–metal (MIM), TiO

2

.

I. I

NTRODUCTION

T

HERE is a strong desire to decrease the processing

temperature of metal–insulator–metal (MIM) capacitors

[1]–[16] while maintaining a high capacitance density (ε

0

κ/t

κ

)

and low leakage current. This requirement is due to the

low-temperature processing associated with low-κ isolation

di-electrics, such as poly-arylene. For very-large-scale-integration

(VLSI) backend integration, temperatures down to 300

◦

C may

be desirable [17]. Low-temperature-processed MIM capacitors

would be useful in the integration of future-generation

Ge-on-Insulator (GOI) [18], [19] and IIIV-on-Ge-on-Insulator (IIIVOI) [20]

technologies, where the device performance can crucially be

dependent on the thermal processing budget. Unfortunately,

most high-κ dielectrics, as used for high-density MIM

capaci-tors, require a high process temperature to improve their quality

and increase the κ value by crystallization.

Here, we describe the performance of MIM capacitors

processed at only 300

◦

C. A capacitance density of 28 fF/µm

2

Manuscript received February 23, 2008. The review of this letter was arranged by Editor A. Z. Wang.

C. H. Cheng and C. P. Chou are with the Department of Mechanical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: feldcheng@hotmail.com; cpchou@cc.nctu.edu.tw).

S. H. Lin and F. S. Yeh are with the Department of Electrical Engineer-ing, National Tsing Hua University, Hsinchu 30013, Taiwan, R.O.C. (e-mail: d9563815@oz.nthu.edu.tw; fsyeh@ee.nthu.edu.tw).

K. Y. Jhou is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: a9368b.ee95g@ nctu.edu.tw).

W. J. Chen is with the Department of Mechanical Materials Engineering, National Yun-Lin Polytechnic Institute, Huwei 632, Taiwan, R.O.C. (e-mail: wjchen@npust.edu.tw).

J. Hu, M. Hwang, and T. Arikado are with Tokyo Electron Ltd., Tokyo 107-8481, Japan (e-mail: jim.hu@tel.com; ming.hwang@tel.com; tsunetoshi. arikado@tel.com).

S. P. McAlister is with the National Research Council of Canada, Ottawa, ON K1A 0R6, Canada (e-mail: Sean.McAlister@nrc-cnrc.gc.ca).

A. Chin is with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C., and also with the Nano-Electronics Consortium of Taiwan, Hsinchu 30013, Taiwan, R.O.C. (e-mail: albert_achin@hotmail.com).

Digital Object Identifier 10.1109/LED.2008.2000833

was obtained with a leakage current of just 3

× 10

−8

A/cm

2

.

Such capacitor performance compares well with that for

de-vices incorporating 450

◦

C processed SrTiO

3

(STO) [14], [15]

and is better than that for 400

◦

C processed TiTaO [11], [12],

TiLaO [13], and STO [16] capacitors. This was achieved by

using a high-κ TiO

2

dielectric that had a high κ value of 65 due

to nanocrystal formation. This occurs at processing

tempera-tures as low as 300

◦

C. These MIM capacitors have potential in

analog, RF, and dynamic random access memory applications,

and are vital for GOI [18], [19] and IIIVOI [20] technologies.

II. E

XPERIMENTAL

P

ROCEDURE

The high-κ TiO

2

MIM capacitors were fabricated on

stan-dard Si wafers having a 2-µm-thick SiO

2

isolation layer on

the Si substrates. Then, TaN (50 nm thick) was deposited on a

200-nm Ta layer and used as the lower capacitor electrode. The

TaN surface was first given an NH

3

plasma treatment [13]–[16]

and then exposed to an O

2

plasma—this being done to increase

the oxidation resistance before the high-κ dielectric deposition

and postdeposition anneal (PDA). Then, a 20-nm-thick TiO

2

dielectric was deposited at room temperature by electron-beam

evaporation at a pressure of 2

× 10

−6

torr followed by a 300

◦

C

PDA for 10 min in an oxygen ambient of 1-atm pressure.

Finally, a 20-nm Ir layer was deposited and patterned to form

the top electrode. The capacitors were 180 µm

× 180 µm in

size, thus minimizing any complications from variations in

dimensions arising from lithography. The fabricated devices

were characterized by standard C–V and J –V measurements.

III. R

ESULTS AND

D

ISCUSSION

In Fig. 1(a) and (b), we show the C–V and J –V

characteris-tics of Ir/TiO

2

/TaN capacitors, respectively. A high capacitance

density of 28 fF/µm

2

_{was measured along with a low leakage}

current of 3

× 10

−8

A/cm

2

at

−1 V. These results are compared

with other MIM data in Table I. Our results are an improvement

over those for a Ni/STO/TaN device, which had a slightly lower

density of 25 fF/µm

2

_{and were processed at 400}

◦

_{C [16]. Since}

the work function of the Ni electrode is only slightly lower

than Ir, the better leakage in the Ir/TiO

2

/TaN device, when

compared with Ni/STO/TaN, is due to the larger conduction

band offset (∆E

C

) of TiO

2

with respect to the STO [21], [22].

This is because the larger ∆E

C

and the higher work-function

electrode will form a higher Schottky barrier height to lower

the leakage current by Schottky emission mechanism [15], [16].

A larger ∆E

C

to the metal electrode is also important for the

high-temperature leakage current at 125

◦

C. We found a 125

◦

C

0741-3106/$25.00 © 2008 IEEE

846 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST 2008

Fig. 1. (a) C–V and (b) J –V (measured at 25◦C and 125◦C) characteristics for Ir/TiO2/TaN capacitors.

leakage current of 6

× 10

−7

A/cm

2

measured at

−1 V. This

is, to the best of our knowledge, better than previous data

and is at a high capacitance density of 28 fF/µm

2

[1]–[16].

In addition, a small loss tangent of 0.013 is obtained at such

large 28 fF/µm

2

_{density using the advanced four-element}

model and two-frequency calculation [23], which can be

de-creased with decreasing capacitance density [24]. A quadratic

voltage coefficient of capacitance (α) of 5010 ppm/V

2

was

obtained at 500 kHz, which can also rapidly be improved with a

decreased capacitance density [14] used for analog/RF

applica-tion. A temperature coefficient of capacitance of 353 ppm/

◦

C

was measured even at a high 28 fF/µm

2

_density.

To understand the performance improvements, we examined

the 300

◦

C processed TiO

2

structure by cross-sectional TEM.

As shown in Fig. 2, the nanocrystallization of TiO

2

is

observ-able even at 300

◦

C. This nanocrystallization effect yields a

high κ value of

∼65 for the TiO

2

dielectric and explains why

the leakage current is better than that for previous TiTaO [11],

[12] and TiLaO [13] MIM capacitors, shown in Table I, which

have a κ value of 45. The high κ value, in combination with

∆E

C

and the high work-function Ir electrode, helps explain the

Fig. 2. Cross-sectional TEM image of a TiO2sample after 300◦C processing.

TABLE I

COMPARISON OFMIM CAPACITORSTHATHAVEVARIOUS DIELECTRICS ANDMETALELECTRODES

good 125

◦

C leakage current. This is because the larger ∆E

C

value lowers the Schottky emission current, and the high κ

value decreases the conducting electric field for both Schottky

emission and Frenkel–Pool mechanism [15].

To study the thermal stability, we annealed an Ir/TiO

2

/TaN

capacitor at 350

◦

C for 20 min under an N

2

ambient. In

Fig. 3(a) and (b), we display the C–V and J –V characteristics

before and after this thermal treatment. Only a small

degrada-tion of the capacitance density and leakage current occurred,

indicating the good thermal stability of both the top Ir electrode

and the metal-electrodes-capped TiO

2

. We also note that good

thermal stability has been reported for Ir/HfAlON pMOS even

at rapid thermal annealing temperatures of up to 900

◦

C [25].

IV. C

ONCLUSION

We have demonstrated Ir/TiO

2

/TaN MIM capacitors with a

capacitance density of 28 fF/µm

2

along with a leakage current

of 3

× 10

−8

A/cm

2

at

−1 V. Since the device processing was

performed at 300

◦

C, this would permit these capacitors to be

integrated into a VLSI backend, along with advanced low-κ

isolation dielectrics, or with future front-end GOI and IIIVOI

technologies.

CHENG et al.: HIGH DENSITY AND LOW LEAKAGE CURRENT IN TiO2MIM CAPACITORS 847

Fig. 3. Thermal stability behavior of a 300◦C formed Ir/TiO2/TaN capacitor

after a 350◦C N2anneal for 20 min.

A

CKNOWLEDGMENT

The National Chiao Tung University (NCTU) team would

like to thank the support from Tokyo Electron Ltd. and NSC

(95-2221-E-009-298-MY3).

R

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