Proceedings of the 2000 IEEE lntemational Conference on Robotics & Automation
San Francisco, CA Apnl2000
Petri-Net and GA Based Approach to Modeling, Schedulin
Performance Evaluation for Wafer Fabrication
Jyh-Horng Chen, Li-Chen
Fu
&
Ming-Hung Lin
Department of Computer Science and Information EngineeringNational Taiwan University, Taipei, Taiwan, R.O.C. Abstract--Wafer fabrication is one of the most capital-
intensive manufacturing processes in the world, which requires an huge investment in plant and equipment. Also,
wafer fabrication is the most complicated one found today. The complexity is as the result of equipment uncertainty, product diversity, process intricacy, ever improving technologies, and variable yields. A significant amount of risk is involved in the wafer fabrication due to huge investment costs, long production cycle time, and short production life cycle. How to survive from such competitive and risky environment has become a major task of effective job-shop scheduling, which has benefits of higher machine utilization, shorter cycle time, higher throughput rate, lower WIP inventory, and greater customer satisfaction In this paper, a genetic algorithm (GA)
embedded search strategy over a hybird color-timed Petri- Net (HCTPN) for wafer fabrication is proposed. Through the HCTPN model, all possible behaviors of the wafer manufacturing systems such as WIP status and machine status can be completely tracked down by the reachability graph of the net. The chromosome representation of the search nodes in GA is constructed directly from the HCTPN model, recording the information about the appropriate scheduling policy for each workstation in the fab. A better chromosome found by GA is received by the HCTPN based schedule builder, and then a near-optimal schedule is generated.
1. Introduction
Wafer fabrication is the most costly phase of semiconductor manufacturing [3]. A significant amount of risk is involved i n the wafer fabrication because it requires huge investment costs and complex manufacturing process. To survive from such competitive and risky environment, the company must not only reduce production cycle time and increase throughput rate but also meet customers’ due dates.
Recent papers by Uzsoy et al. [3,5] and Johri [4] highlight the difficulties in planning and scheduling of wafer fabrication facilities. These papers also survey the literature on releated topics. Effective shop-floor scheduling can be a major component of reduction i n cycle time. The benefits of effective scheduling include higher machine utilization. shorter cycle time, higher throughput rate, and greater customer satisfaction. This is particularly true of semiconductor manu-facturing, with its rapidly changing markets and complex manufacturing processes [1,6,7,81. Yet i n
many wafer fabrications the product spends much more waiting time than actually being processed, so there is a large potential for reducing waiting time and a great benefit for doing so. It is well known in the scheduling literature that the general job shop problem is NP-hard, which lead to no efficient algorithm exists for solving the scheduling problems optimally in polynomial time for wafer fabrication, and therefore it is the reason why we apply the genetic algorithm (CA) to approach the problem. CA is a search procedure that uses random choices as a guide tool through a coding in the parameter space [9-131. While randomized, however, GAS are by no means a simple random-walk approach. They efficiently exploit historical information to speculate on new search nodes with expected improved performance. That is, GA samples large search space randomly and efficiently to find a good solution in polynomial time, which however does not require enormous memory space as other traditional search algorithms such as A*. Many researchers have used GA to deal with job shop scheduling problem in traditional industries. Lee et al. [ 121 focused on solving the scheduling problem in a flow line with variable lot sizes. Lee et al. [ I I]
combined the machine learning and genetic algorithm in the job shop scheduling. Ulusoy et al. [13] have
addressed on simulateneous scheduling of machines and automated guided vehicles (AGVs) using genetic alogrithm. In addition, Cheng et al. [IO] have
surveyed relational topics on solving the job shop problem using GA. They also discussed chromosome representation in details. Unlike the previous research, we use CA methodology to solve the more complex scheduling problem in wafer fabrication. However, since wafer fabrication is a complex discrete event system, schedulers cannot be easily realized on this kind of system, and thus how to model a complex wafer fab manufacturing system is a imperative task. In the modeling field, Petri Net (PN) has played an important role; it has been developed into a powerful tool for discrete event systems, particularly i n manufacturing systems. PNs have gained more and more attentions i n semiconductor manufacturing due to their graphical and mathematical advantages over traditional tools to deal with discrete event dynamics and characteristics of complex systems [ 14- 171. ZIiou e/ d. [15] reviewed applications of PNs in semiconductor manufacturing automation. I t can also serve as a tutorial paper. The colored timed Petri net
(CTPN) is used to model the furnace in tlie IC wafer fabrication [ 171 and i n the entire wafer fabrication manu-facturing system [ 141. Jeng e/ d. [ I61 applied Petri net methodologies to detailed modeling, qualitative analysis. and performance evaluation of the etching area in an IC wafer fabrication system located in the Science Based Industrial Park i n
Hsinchu, Taiwan.
In this paper, we propose a systematic hybrid color- timed Petri-Net (HCIPN) model embedded with a genetic algorithm (CA) scheduler. The HCTPN can be used to model the complex process flows i n wafer fah efficiently and the detailed manufacturing characteristics. Also, new transitions are introduced in this paper, which significantly reduce the complexity of Petri-Net model. The CA scheduler can be used to dynamically search for an appropriate dispatching rule for each workstation or processing unit family through the HCTPN model.
The organization of this paper is described as follows. In Section 2 . the definitions of the proposed hybrid color-timed Petri net (HCTPN) are revealed here. And, the systematic inethod of HCTPN model is discussed. In Section 3, a GA embedded search method over the HCTPN model is employed. In Section 4, we demonstrate two example of using the proposed mechanism and analyze the performance. Finally, conclusions are provided i n Section 5.
The ordinary PN do not include any concept of time and color. With this class of nets, it is possible only to describe the logical structure and behavior of the modeled system, but not its evolution over time and color. Responding to the need to model the manufacturing system i n wafer fab, we add time and color attributes to the ordinary PN. I n the proposed hybrid colored-timed Petri-Net (HCTPN) model, we introduced three kinds of places. namely immediate (ordinary) places, timed places, and communication places, and five kinds of transitions, i.e., immediate (ordinary) transitions, colored transitions, mapping transitions, comparable transitions, and macro transitions. Also, we have introduced colored tokens in the HCTPN model. For clarity, tlie tokens' color and transitions are described as follows.
Tokens' color
In the HCTPN model, the color of the tokens is defined as a 5-digits number. The first two digits are defined as the product type, i.e., the route ID. and the last three digits are defined as the operation step that the product is performed now.
Immediate transitions
Immediate transitions are the same as the ordinary transitions. They can be used to model behaviors or events of resources in manufacturing systems. Colored transitions
There are a set of colored transitions T and a set of color C in HCTPN model. For all t E 7', which
2.
Wafer Processing Model3404
contains a color set C ( t ) . We define that t E be enabled with respect to the color c if
can m ( p , c ) 2 I ( P , l . C ) , v p € P . c € C ( t ) :
where
P is the set of places in HCTPN model.
m( p , c ) is the number of tokens in p with respect to the color c.
I ( p , i , c ) is the multiplicity of input arcs fromp to t
with respect to the color c.
After the colored transition t is fired, the new marking
m' becomes
In the HCTPN model, the colored transition is drawn as K X X .
Mapping transitions
The function of the mapping transitions is to transfer the token's color c , to a predefined color c7, i.e., after firing the mapping transitions, the color of the tokens that enable this type of transition is transferred to the predefined color of other kind. The other enabling and firing rules of the mapping transitions are the same as the ordinary transitions. In the HCTPN model, the mapping transitions are drawn as IZZ.
Comparable transitions
A comparable transition has two input arcs and two output arcs, which was drawn as
-.
One of the comparable transition's output arcs is a regular arc; tlie other one is an inhibitor arc. Only one of the comparable transition's output arcs can be enabled. The mechanism of the comparable transitions is that, tlie comparable transition compare the two token's color in the two input places, if the colors are the same. the regular output arc is active; otherwise, the inhibitor arc is active.Macro transitions
Each macro transition contains a module of the model, and the module contains a set of subnets. In the HCTPN model, the macro transitions are drawn as
LII.
In this paper, we used the proposed HCTPN to model the whole wafer manufacturing systems which include the deposition, photolithography, etching, and diffusion areas. The wafer processing model we proposed is a general model, which does not focus on some special cases. In other words, when the equipment information is given, the wafer processing model is automatically generated by the model generator. Different process flows of different products can be performed based on this model by changing the tokens' color, as long as these process flows were performed in the fab using the proposed HCTPN model. The implementation of the model generator was discussed in Section 4, and the details of the proposed Wafer Processing Model including Routing Module and Elementary Module (see Figure 3 ) are described i n the following sections.
The purpose of the Routing Module is to model the logical process flow of the manufacturing systems. The basic concept of this module is described as follows. First, we divide all the machines in the fab into n workstations (niachiiie groups or processing unit family), each of which contains one or more ideiitical machines (or processing iiriits). At the beginning, a token (lot) with the color xyOOO enters the model, where xy is the route ID, and 000 is current operation step. Lots then checkin aiid the lots’ color are changed to xyOO1, preparing to do the first operation. Each operation has its associated workstation to be performed, thus lots travel to and take operations in the proper workstation i n the fab according to the predefined process flow. After the lot finishes the current operation, the lot’s color number will be increased by one, and ready to do the next operation. Step by step, after the lot finishes all its operations, it enters the end place and finishes the work. The Routing Module which is shown in Figure 3 implements the idea above-mentioned. For clarity, we explain the notations used in Figure 3 as follows:
The purpose of Operating Module is to model the detailed manufacturing system in a wafer fab, such as processing, setup, rework, scheduled machine maintenance as well as unscheduled machine breakdown, and time-critical operation. We divide the Elementary Module into two subnets, which will be explained in details as follows.
?
Wafer Processing Model
Elementary Module 1
Elementmy Module 2
Routing Module
Figure 2 Wafer processing model Time-Critical Subnet
Time-Critical Subnet is shown in Figure 4. This subnet is used to avoid the rework in some time- critical operations. The idea of the Time-Critical Subnet is that if a lot is waiting for a time-critical operation, after waiting for some specific time period, the lot can get the higher priority and can be performed first. The notation used in Figiire 4 is described below.
Figure 3 Routing module.
Figure 4 Time-Critical Subnet.
8 k < <*LA
111,.,1.’1
-7
Figure 5 Operating Subnet Operating Subnet
Operating Subnet is shown in Figure 5. The purpose of this subnet is to model processing, machine setup, machine failure, aiid to check whether the lot needs to be reworked. Similarly. we explained the notation used in Figure 5 as follows. ’
3.
Wafer Fab SchedulerIn this paper, we allow our computation model to
support the search algorithm over a hybrid color- timed place Petri-Net (HCTPN) model, i.e., search can be performed in both axes of multiple resources and different time segments. Here. we propose a new 3405
scheme to represent a schedule for the problcm o f production scheduling in wafer fah using CA
embedded search over a HCTPN model. The algoritlim starts with an initial set of random configurations called a population. which i s a collection of chromosomes. The clirotnosoiiie here denotes a total scheduling solution for wafer fabrication. The size of the population i s always tixed (N,,). Following this, a iiiating pool is established in
which pairs of individuals from the population are chosen. The probability of choosing a particular individual for mating is proportional to its fitness value. Chroniosomes with higher fitness values have a greater chance of being selected for mating. Applying crossover (R?) to generate new offsprings. Mutation atid inversion are also applied with a low probability. Next the offsprings generated are evaluated on the basis of fitness. and selecting some of the parents and some of the offsprings forins a new generation. The above procedure is executed
N,
times. wherey,
is the number of generations. After a fixed number of generations ( N K ) , the fittest chromosome. i.e., the one with the highest fitness value is returned as the desired solution.Chromosome Representation
In this paper, we use priority rule-based representation of chromosomes in the CA. This representation belongs to indirect approaches as described above, which brings us the advantages such as the simplicity of the chromosome structure, simple GA operators, and shorter computation time. First. we define a gene place as follows:
P, : A gene place set is a subset of the place set. i.e., p, c P . A gene place p E PK is used to control the scheduling i n GA over HCTPN model. The gene place in our HCTPN model is denoted as the input buffer place of each machine group. that is. each machine group (identical machines) has a gene associated with it. A gene g = (d,s,h) is a three tuple where
0 d one type of dispatching rules.
R
s: one type of setup rules.0
b: one type of batching rules.The rules we selected for gene codes are listed i n
Table 1.
Table 1 Gene codes
For each rule, it is described as follows:
0
FCFS: First Come First Serve.R
MINS: Minimum Inventory at the Nest Station first. In this rule. a lot has a higher priority if itsnext operation workstation has a lower inventory.
SRPT: Shortest Remaining Processing Time first
EDD: Earliest Due Date first SSU: Same Set-Up first
WxT: Waiting for the arrival lot to cotnplete the batch within x unit of lot inter-arrival time. When the batch is completed within this specific time period. the batch is started immediately. Otherwise, the partial batch is started right after one unit of lot inter-arrival time.
After genes are defined. the chromosome can be created. I n this paper, the length of a chromosome is tixed, and is equivalent to the number of machine groups. The structure of the chromosome is depicted in Figure 6 .
Figure 6 Chromosome representation Fitness Function
In this paper. we use three objective functions in our implementation. The fitness function is defined as follows:
. f ( c ) =
wheref; is the score for mean cycle time,
' . f ; ( c ) + *v2 . .fz(c) + w; ' f;(c)
A
is the score for throughput rate,fi
is the score for number of lots which meet due date.Scheduler Builder
A schedule builder is dedicated to transforming a chromosome to a feasible schedule, such that we can evaluate the aforementioned indirect cliromosome representation. Based on the HCTPN model, the evolution of the system can be addressed by the change of marking i n the net. Consequently, all possible kinds of behavior of the system can be completely tracked by the reachability graph of the net. In other words, we can track the WIP status from the HCTPN model while the schedule was performed. Thus, given a HCTPN model and a chromosome, the schedule builder can generate a feasible schedule in
terms of the firing sequence of transitions in the HCTPN model according to the chromosome. The firing sequence of transitions provides the order of the initiation of operations. The architecture of the scheduler was shown in Figure 7, i n which, we first select a lot release policy to control the tiinins for 3406
release of a lot (token) to the HCTPN model. Second, apply the GA over the HCTPN to find a good chromosome. Finally, use the schedule builder to transform the chromosome to a feasible schedule.
Genetic Algonthm
Rclcn\c I'olicy
Figure 7 The
architectureof
t h e scheduler4.
Experiment Results
The simulation model we used in this paper is based on Wein's model [I]. It describes a fictitious wafer fab, but most of the parameters of the model are derived from data gathered at the Hewlett-Packard Technology Research Center Silicon fab (the TRC fab), which is a large R&D facility in Palo Alto, California. Unlike the model studied by Wein [I], we enlarge the capacity of the fab to increase the complexity of the simulation. Moreover, we add the rework probability to the inspection machines, and define the reworked step in each route. Batch processing machines are also included in our simulation model, so that the simulation model can be closed in real fab. We assume both of the workstations of TMNOX and PLM6 are batch- processing machines, and their batch size are 4 and 2, respectively. The entire fab contains 24 workstations (total 74 machines) in our simulation model, and three different process flows are defined. Route 1 has 172 steps, and its total processing time is 494.6 hours. Route 2 has 139 steps, and its total processing time is 412.7 hours. Route 3 has 110 steps, and its total porcessing time is 346.7 hours.
Case 1:
Three Orders for Total
100Lots
The problem description is listed in Table 2 Table 2 Three orders Order 1D Route Quantity (lots) Due Date
Order 01 Route 1 30 1999/12/180800 Order 02 Route 2 20 2000/0 1/03 08 00
Order 03 Route 3 50 2000/0 1/13 08 00
- - -
-____
- - -__-_-
Current System Date: 199911 0/30
We evaluated the scheduling policies, wh EDD, and GA. I n
dispathcing rules plus SSU are also evaluated. For each scheduling policy, we run
LO
times of simulation and calculate mean value and standard deviation. The the compared results are listed in Table 3, where the three criteria are mean queueing time (MQT), throughput rate (TPR), and the rate of meeting due date (MDD).Table 3 The compared result for case 1
Case
2:
Four Orders for Total 80 Lots
Unlike the case 1, we have four orders
in
the case 2. Also, the route sequence we used as the input pattern in the case 2 is different from the case 1. Here we listed the four orders, and one compared result in Table 4, and Table 5, respectively.Table 4 Four orders to be released into the fab Order ID Route Quant'ty (lots) Due Date Order 0 I Route 2 20 1999/12/12 08:OO
Order 02 Route 3 20 1999/12/17 08:OO
Order 03 Route I I O 1999/12/24 08:OO
Order 04 Route 3 30 2000/01/04 08:OO
Current System Date: 1999/10/30
Table 5 The compared result for case 2
From Table 3 and Table 5, we found that the proposed GA scheduler performs much better than other conventional dispatching rules. It has a lower queueing time for lots spent in the fab, a higher throughput rate for a fab, and a higher rate for meeting the customers' due date. In addition, the experimental results show that the proposed GA scheduler has a lower variability on the total queueing time, throughput rate, and the rate of meeting due date, which increases the accuracy of the simulation based 3407
prediction. As a result. tlie proposed GA scheduler has a significant impact on wafer fab scheduling. by providing obvious iinprovements over the other conventional dispatching rules. even tliougli the fab has a mixed production.
5. Conclusion
In this paper. we consider the wafer fab scheduling problem. We first proposed a systematic hybrid colored-timed Petri-Net (HCTPN) model for a wafer fab. The entire HCTPN model is composed of two modules. one is Routing Module, and the other is Elementary Module. The objective of the Routing Module is to model the logical process tlow of the wafer fab manufacturing system. And, the Elementary Module is used to model the detailed manufacturing characteristics in wafer fab. I n this paper. we also introduced many new transitions. which are useful to model some special issue and to significantly reduce the complexity of Petri-Net inodel i n our study. I n order to make better scheduling policies on wafer fab, we proposed a genetic algorithm scheduler, which dynamically searches for the appropriate dispatching rules for each machine group or processing unit family. Through the experiments, we found that tlie CA scheduler provides more superior performance than the conventional dispatching rules do. By using GA scheduler. we have a higher throughput rate for fabs. a shorter queueing time for lots spent i n tlie fab, and a higher promising rate for meeting the custoiners’ due date.
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