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計算機系統

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國立臺中教育大學 96 學年度研究所碩士班招生考試

計算機系統 科試題

一、(a) Why can’t use the top-down parsing method to process the grammar listed as below?(4%) (b) Please modify this grammar to avoid above problem. (4%)

<id-list> ::= id | <id-list> id

<exp> ::= <term> | <exp> + <term> | <exp> - <term>

<term> ::= <factor> | <term> * <factor> | <term> DIV <factor> 二、Please answer following questions briefly.(12%)

(a) What is a critical section?

(b) What three requirements must a solution to the critical-section problem satisfy? (c) What is multiprogramming?

(d) What is swapping? (e) What is a context switch? (f) Define deadlock

三、Peterson’s solution is a classic software-based solution to the critical-section problem.(10%) (a)In regard to the Peterson's solution (described in the following picture) for process i and

process j, please fill some code in the following blank-blocks (Block-A ~ Block-E). (b)Please prove Peterson's solution satisfies the three requirements of critical-section.

Block C

Block D Block B

The structure of process Pi in Peterson’s solution

Block A

;

)

;

( )Block E

;

Block C Block D Block B

The structure of process Pi in Peterson’s solution

Block A

;

)

;

( )Block E

;

資訊科學學系碩士班 用

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四、Consider the following segment table: (1st ~ 12st bit for segment base address, 13st ~ 22st bit for segment length)(9%)

Content

Segment No.

0

1

2.

3.

4

0000110110111001011000

1000111111000000001110

0000010110100001100100

0101001011111001000100

0111101000000001100000

Content

Segment No.

Content

Segment No.

0

1

2.

3.

4

0000110110111001011000

1000111111000000001110

0000010110100001100100

0101001011111001000100

0111101000000001100000

0000110110111001011000

1000111111000000001110

0000010110100001100100

0101001011111001000100

0111101000000001100000

What are the physical addresses for the following logical addresses (1st ~ 3st bit for segment number, 4st ~ 12st bit for offset)?

000110101110 011110010000 010111110100 a. b. c. 000110101110 011110010000 010111110100 a. b. c.

五、Assume that we have a demand-paged memory. The page table is held in registers. It takes 8 milliseconds to service a page fault if an empty frame is available or if the replaced page is not modified and 20 milliseconds if the replaced page is modified. Memory-access time is 100 nanoseconds. Assume that the page to be replaced is modified 70 percent of the time. What is the maximum acceptable page-fault rate for an effective access time of no more than 300 nanoseconds?(5%)

六、Consider the following set of processes, with the length of the CPU-burst time given in milliseconds:(16%)

Process Burst Time Priority

A 10 3 B 1 1 C 2 3 D 1 4 E 5 2

The processes are assumed to have arrived in the order A, B, C, D, and E, all at time 0.

(a) What is the average turnaround time of each process for each of the scheduling algorithms including FCFS, SJF, a non-preemptive priority (a smaller priority number implies a higher priority), and RR (quantum = 1) scheduling?

(b) Which of the schedules in part a results in the minimal average waiting time (over all processes)?

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七、For minimizing the number of page faults of a page replacement algorithm, we can associate with each page frame a counter of the number of pages that are associated with that frame. Then, to replace a page, we search for the page frame with the smallest counter. Use FIFO for breaking ties. Where, the initial value of the counters is 0. Counters are increased whenever a new page is associated with that frame. Counters are decreased whenever one of the pages associated with that frame is no longer required.(10%)

(a) How many page faults occur for the algorithm described above for the following reference string, for four page frames?

1, 2, 3, 4, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4, 2

(b) What is the minimum number of page faults for an optimal page replacement strategy for the reference string in part (a) with four page frames?

八、Consider the following structure of the instruction register. Op code address-1 address-2

8 bits 16 bits 16 bits

(a) What is the maximum number of distinct operation codes that can be recognized and executed by the CPU? (5%)

(b) What is the maximum memory size on this machine? (5%)

九、Please explain the Hamming Code. If the original 8-bit data is 00111011, please write out the 12-bit Hamming code include 4 parity bits. (10%)

十、Derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit. (10%)

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