Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs

Abstract—This paper examines the edge direct tunneling (EDT)

of holes from p

polysilicon to underlying p-type drain extensions

in off-state p-channel MOSFETs having ultrathin gate oxides that

are 1.2 nm–2.2 nm thick. It is for the first time found that for

thinner oxides, hole EDT is more pronounced than both

conven-tional gate-induced drain leakage (GIDL) and gate-to-channel

tunneling. As a result, the induced gate and drain leakage is

more accurately measured per unit gate width. Terminal currents

versus input voltage are measured from a CMOS inverter with

gate oxide thickness

= 1 23 nm, exhibiting the impact of

EDT in two standby modes. For the first time, a physical model is

derived for the oxide field

at the gate edge by accounting for

the heavy and light holes’ subbands in the quantized accumulation

polysilicon surface. This model relates

to the gate-to-drain

voltage, oxide thickness, and doping concentration of the drain

extension. Once

is known, an existing direct tunneling (DT)

model consistently reproduces EDT current–voltage

( – ),

and the tunneling path size extracted falls adequately within the

gate-to-drain overlap region. The ultimate oxide thickness limit

due to hole EDT is projected.

Index Terms—Direct tunneling (DT), edge direct tunneling

(EDT), gate-induced drain leakage (GIDL), MOSFETs, oxide,

surface quantization, valence-band electron tunneling (VBET).

I. I

T

HE gate oxide thickness in scaled MOSFETs is now

ap-proaching the direct tunneling (DT) regime [1]. The gate

leakage due to DT [2] is usually measured per unit oxide area

[3], [4], and a certain criterion of 1 A/cm was thought to be the

ultimate limit of scalable oxide thickness [3], [4]. For n-channel

devices in off-state or in standby mode during the normal circuit

operating conditions, the edge direct tunneling (EDT) [5]–[7] of

electrons from n polysilicon to the underlying drain extensions

not only dominates over the gate leakage, but also can prevail

over the conventional gate-induced drain leakage (GIDL) [8],

[9]. This paper explores the EDT of holes from p

polysilicon

to the drain extensions in p-channel devices. The treatment is

Manuscript received April 2, 2001; revised July 19, 2001. This work was supported by the National Science Council under Contract NSC89-2215-E-009-049. The review of this paper was arranged by Editor G. Groeseneken.

K.-N. Yang and H.-T. Huang were with the Department of Electronics Engi-neering, National Chiao-Tung University, Hsinchu 300, Taiwan. They are now with the R&D Department, Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.

M.-J. Chen is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. ([email protected]).

Y.-M. Lin, M.-C. Yu, S.-M. Jang, D. C. H. Yu, and M.-S. Liang are with the R&D Department, Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(01)10094-8.

similar to the one for nMOSFET EDT version [6], [7], which

facilitates direct comparisons between the two. Here, we report

for the first time that for thinner oxides, hole EDT becomes more

significant than the GIDL and gate-to-channel tunneling. This

indicates that the induced gate and drain leakage originate from

the oxide edge rather than the whole gate oxide, and thus it is

best measured or evaluated per unit gate width. To get an

under-standing of the impact of EDT, we measured current–voltage

–

from a CMOS inverter on the same wafer. The ability to

model hole EDT –

is essential. An existing DT –

model

cited in [10], [11] is utilized. Unlike the whole area

counter-part where the so-called capacitance–voltage

–

integration

technique [12] is valid, however, it is very difficult to measure

the oxide field at the gate edge—which is the input parameter

to the model—since the overlap capacitance is too small to

de-tect using present

–

equipment. To alleviate this problem,

we present a physical model for the oxide field

at the gate

edge by accounting for heavy and light holes’ subbands in the

quantized accumulation polysilicon surface. This model is quite

vital in enabling the consistent reproduction of EDT – , the

extraction of EDT path size and dopant concentration of drain

extension, and even the projection of ultimate oxide thickness.

II. E

C

Test patterns including p

poly-gate p-channel MOSFETs

and CMOS inverters were fabricated in an 0.18- m process

technology [13]. The gate oxides were grown in dilute wet

oxygen ambient to three different physical thicknesses: 1.23,

1.85, and 2.16 nm. These oxide thicknesses for p-channel

devices were adequately extracted by using an electron DT

–

model [10] and were all confirmed by high-resolution

transmission electron microscope (TEM) and a

–

method

accounting for polysilicon depletion and quantum mechanical

effects, as detailed elsewhere [14]. Other process parameters

like poly reoxidation, extension source/drain implant dose, and

spacer thermal budget were unchanged.

Fig. 1 illustrates three plausible tunneling leakage paths for

off-state p-channel MOSFETs and related band diagrams. With

the source open to prevent subthreshold conduction and

, where

is drain voltage and

is gate voltage, the

mea-sured drain current

, gate current

, and bulk current

are

plotted in Fig. 2 versus

for three different

oxide thicknesses. Fig. 2(a) and (b) reveals that the drain

cur-rent is primarily due to the GIDL and the gate curcur-rent, with

EDT being the origin of the latter component. It is seen that

a certain range of

exists where the EDT dominates over

the GIDL, and this range is extended for decreased gate oxide

(a)

(b)

(c)

Fig. 1. (a) Band diagram located at channel region far from drain extension region. Accumulation hole DT current(I ) and electron DT (I ) both contribute to gate/channel tunneling. (b) Schematic cross section near gate/drain overlap region underV > 0 V and V = 0V . Three tunneling current paths are shown. (c) Band diagram located at gate/drain overlap region, showing hole EDT and GIDL.

thickness. We attribute the EDT herein to hole tunneling rather

than valence electron tunneling. This is based on the band

di-agrams in Fig. 1 which show that for low-voltage

, it is

extremely improbable that valence electrons will tunnel across

the oxide to the forbidden gap in polysilicon side. In Fig. 2(c)

for

nm, the bulk current is solely due to

gate-to-channel tunneling, making GIDL impossible to detect. Note

that hole EDT dominates the gate current for all

. With

the source grounded and

V, the measured

ter-minal currents versus both polarities of

are plotted in Fig. 3.

Obviously, the GIDL dominates the drain leakage for

nm, while for a thinner

of 1.85 nm hole EDT

domi-nates from

V

V, and eventually the drain leakage

is entirely controlled by hole EDT for

nm. Fig. 3(c)

shows the bulk current reversal phenomenon due to two

oppo-site sources: GIDL and gate-to-channel tunneling. Regarding

on-state –

(negative

) in Fig. 3, the impact of hole DT

from the inverted channel on degrading drive capability is

de-scribed in our recent work [14]. Particularly for

V in

Fig. 3(c), the significant

is attributed to valence-band

elec-(a)

(b)

(c)

Fig. 2. Measured terminal currents versusV for (a)T = 2:16 nm; (b)

T = 1:85 nm; and (c) T = 1:23 nm, under V = 0V and source

open. The aspect ratioW=L = 10 m=0:5 m. In (a), hole EDT dominates the drain leakageI in 0 V < V < 2:3 V. In (b), hole EDT dominates I in0 V < V < 2:6 V and GIDL constitutes drain leakage for V > 2:6 V. In (c), the edge tunneling mechanism dominates the drain leakage current.

tron tunneling (VBET) from the p -polysilicon to the

conduc-tion band of the n-well. We also found experimentally that the

hole EDT leakage is indeed proportional to the gate width,

re-gardless of the aspect ratio. This again suggests that the induced

gate and drain leakage is better measured or evaluated per unit

gate width.

Fig. 4 displays the supply current and input current versus

input voltage

measured for a CMOS inverter with

nm and with supply voltage

as a parameter. It can be

observed in Fig. 4(a) that:

1) at low-level state

V , the standby current is

due to the electron EDT [5]–[7] in the off-state n-channel

device and the hole DT from the inverted channel in the

on-state p-channel device [14];

2) at high-level state

, the standby current

comes from the hole EDT in the off-state p-channel

de-vice and the electron DT from the inverted channel in the

on-state n-channel device.

(a)

(b)

(c)

Fig. 3. Measured terminal currents versus gate voltage for both polarities. The aspect ratio isW=L = 10 m=0:5 m. Source grounded and V = 01:8 V.

Attached in Fig. 4(b) is the measured ratio of each component.

For the inverter in low-level state,

V, the electron

EDT resulting from the off-state nMOSFET accounts for 25%

of the total input leakage current while the hole DT current

originating from on-state pMOSFET accounts for 75%. As

for high-level state

, the hole EDT resulting from

off-state pMOSFET is responsible for 36% of the total input

leakage current while the electron DT current originating from

on-state nMOSFET contributes the rest. Note that the apparent

difference of 36% versus 25% in EDT contribution can be

attributed to the fact that the p-channel pull-up device has about

two times the gate width of the n-channel pull-down device.

Obviously, as channel length continues to shrink, the role of EDT

substantially increases since diffusion extension does not easily

scale [5], [15].

III. H

EDT M

By following a published analytic electron DT model [11], a

hole EDT version was built

(1)

(a)

(b)

Fig. 4. (a) Gate leakage paths in two standby modes. (b) Measured supply currentsI andI , and input current I versus input voltageV for an inverter withT = 1:23 nm and with supply voltage V as a parameter. The gate length is 0.18m.

where

heavy hole;

light hole;

effective tunneling path area;

effective tunneling path size;

sheet charge of the accumulation layer;

hole impact frequency on p -poly/SiO

in-terface;

modified Wentzel-Kramer-Brillouin (WKB)

transmission probability including the

interface reflection correction.

Fig. 5. Band diagram drawn along p -polysilicon/oxide/drain extension. The accumulation potential bending,V , with 2-D hole gas (2DHG) concept and the silicon surface potential,V , with the deep depletion approximation are adopted in the procedure ofE calculation.

The oxide field

at gate edge is a key input parameter to the

model. It has to be estimated under each value of

. In our

work, the

–

integration technique failed to extract

be-cause hole EDT occurs only within the area of gate/drain overlap

region and it is difficult to measure such a small capacitance in

the overlap part.

at the gate edge can be obtained by solving

the following equation:

(2)

where

is the potential drop in the p

polysilicon and

is that in the drain extension region. We apply the first subband

approximation to accumulated p poly-gate and the deep

deple-tion approximadeple-tion to the underlying drain extension region, as

shown in Fig. 5 The charge

available for tunneling is modeled

as field induced, i.e.,

(3)

Relating this sheet charge density to the number of occupied

subband states leads to the charge conservation relationship

. Here,

and

. This leads to

(4)

Here,

represents the two-dimensional (2–D)

density of states. The quantized energy of the first subband

can be estimated directly with Sommerfeld-Wilson’s

quantiza-Fig. 6. Comparison of the calculated and experimental hole EDT current versusE . The extracted effective EDT range is 6 nm wide from the gate edge.W = 10 m.

tion rule under triangle-like electrostatic potential

approxima-tion to the polysilicon surface

We thus get

(5)

(6)

where

is the dopant concentration of the drain extension.

As a result, (2) can be further rearranged as

(7)

where

For

poly-grain orientation,

,

;

,

as cited in [16].

Thus, it is easy to extract

by solving (7) numerically. Once

is quantified, we can compute the hole EDT current in

terms of (1). We found from experiments (similar to [6], [7]) that

EDT is insensitive to the n-well bias under off-state condition.

This suggests that the lateral field component in the

gate-to-drain overlap region can reasonably be ignored. In other words,

a one-dimensional (1-D) approach is sufficient in our work. In

carrying out the above model, it was found that the slope of

versus

depends strongly on

. An excellent

repro-duction was achieved with a drain extension doping of

Fig. 7. Calculated hole DT current per gate width versus scaling generation oxide thickness in pMOSFETs. The table shows the scaling parameters from [1]. The inset schematically exhibits the hole EDT path in pMOSFET structure.

L = 6 nm.

cm and effective mass,

for both

heavy and light holes resulting from the parabolic dispersion

relation in tunneling oxide, as depicted in Fig. 6. The extracted

tunneling path size

was 6 nm wide from the gate edge since

the extracted

quite matches the experimental one in the

highly-doped region. This is reasonable since the drain

exten-sion beneath the gate is about 8 nm. Therefore, the modeling

work validates the hypothesis that hole EDT is the origin of the

leakage in pMOSFETs.

It was very recently recognized [5], [15] that the drain

extension may be considered a nonscalable factor, implying

a constant

of 6 nm in the scaling direction. With this in

mind, the conventional criterion of 1 A/cm can be effectively

transformed to 0.6 A/cm. Using the roadmap parameters [1],

the hole EDT current was calculated versus scaling generation

oxide thickness, as shown in Fig. 7. In this figure, the new

criterion due to hole EDT sets the ultimate oxide thickness to

around 1.42 nm.

IV. C

The EDT of holes from p

polysilicon to the underlying

p-type drain extension has been shown to have a tremendous

impact on the drain leakage and gate leakage. This unwanted

effect is more serious for thinner oxide thickness. It is shown

that the gate leakage in practical standby mode should be

mea-sured or evaluated per unit gate width rather than by the whole

gate area. We have shown experimentally that EDT contributes a

significant amount of leakage current in a CMOS inverter and is

the dominant source of leakage for

nm. A physical

model has been developed that consistently reproduces

experi-mental EDT –

characteristics. The extracted tunneling area

has been found to fall within the gate-to-drain overlap region

and the ultimate oxide thickness limit due to hole EDT has been

projected.

A

The authors wish to thank T. K. Kang for many stimulating

and helpful discussions. They also wish to thank F. O’Mahony,

a doctoral student in the Department of Electrical Engineering,

Stanford University, Stanford, CA, for improving English in the

manuscript.

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Kuo-Nan Yang received B.S., M.S., and Ph.D. degrees in electronics

engi-neering from National Chiao-Tung University (NCTU), Taiwan, in 1997, 1998, and 2001, respectively.

On April 2001, he joined Future Device Division/R&D, Hsinchu, Taiwan R. O.C., Semiconductor Manufacturing Company (TSMC), Hsinchu. His current responsibility is to explore future device candidates such as SOI CMOS, Si-Ge CMOS, and FinFET.

Huan-Tsung Huang (S’98–M’00) received B.S. degree in electrical

engi-neering from National Cheng-Kung University, Taiwan, R. O. C., in 1988, and M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1990 and 2000, respectively.

From 1990 to 1992, he served in the Chinese army as a Tactical Control Officer. From 1992 to 2000, he was with Ta-Hua Institute of Technology, Taiwan. On September 2000, he joined Device Engineering Division/R&D, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu. His current responsibility is to explore gate stack candidates in next-generations CMOS devices.

Ming-Jer Chen (S’78–M’79–SM’98) received B.S. degree in electrical

engi-neering (with highest honors) from National Cheng-Kung University, Taiwan, R.O.C., in 1977, and Ph.D. degree in electronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1985.

Since 1985, he was with the Department of Electronics Engineering, NCTU, where he became Professor from 1993. From 1987 to 1992, he was a principal consultant for TSMC, where he led a team from NCTU and ERSO/ITRI to build process window and design rule. In 1996 and 1997, he critically enabled ERSO/ITRI video A/D converter and TSMC mixed-mode CMOS processes, re-spectively. From 2000 to 2001 academic year, he was a Visiting Professor at the Department of Electrical Engineering and Center for Integrated Systems, Stan-ford University, StanStan-ford, CA. His research interests have long been focused on technology reliability physics and currently on nanoscale electronics. He has graduated nine Ph.D. students and has been granted four U.S patents and six Taiwanese patents in the above areas.

Dr. Chen received the 1992 and 1993 Chinese Young Engineering Paper Award and the 1996 Acer Distinguished Dissertation Award. He is a member of Phi Tau Phi.

Yeou-Ming Lin received B.S. degree in electrical engineering from Tatung

In-stitute of Technology, Taiwan, R.O.C., in 1991, M. S. degree in electrical en-gineering from National Hsin-Hua University, Taiwan, in 1993, and Ph.D. de-gree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1997. His Ph.D. dissertation focused on process issues of interpoly-silicon dielectric and intermetal dielectric as well as their impact on device re-liability.

From 1994 to 1995, he worked on intermetal dielectric development for 0.35-m CMOS processes in Taiwan Semiconductor Manufacturing Company (TSMC). On September 1999, he joined Advanced Module Technology Division/R&D, TSMC, being responsible for gate quality silicon and high-k gate dielectric for 0.1-m CMOS. He has been sent since 2000 to Sematech and IMEC to explore process development and reliability of gate quality silicon.

Mo-Chiun Yu was born in Hsinchu, Taiwan, R.O.C., in 1968. He received

the B.S. degree in electrical engineering form National Tsing-Hua University, Hsinchu, in 1991, and the M.S. degree in electrical engineering from Tohoku University, Sendai, Japan in 1997, under the sponsorship of the Ministry of Ed-ucation of Taiwan. In 1997, he joined Taiwan Semiconductor Manufacturing-Company Ltd., Hsinchu, where he has been engaging in research and develop-ment for ultrathin gate dielectric process and characterization.

Simon S. M. Jang received the B.S. and M.S. degrees from the National

Tsing-Hua University, Hsinchu, Taiwan, R.O.C., in 1985 and 1987, and the Ph.D. degree from the Massachusetts Institute of Technology (MIT), Cambridge, in 1993, all in materials science and engineering. His dissertation work included Si/ge CVD technology, kinetics, and thermal stability for HBT application. Sponsored by IBMand SRC, his reseach was conducted in the Microsystems Technology Laboratories, MIT, under the guidance of Prof. R. Reif in electrical engineering.

He joined Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, in 1993. He has successfully developed ozone-TEOS, spin-on coating, HDPCVD dielectrics, PECVD SiON anti-reflection layer, and CMP processes for 0.5-0.18

m CMOS technologies. He is now the Manager of Dielectric/CMP Projects in

the Advanced Module Technology Division, R&D, responsible for the modules of shallow trench isolation, gate stack, ultrashallow junction, interpoly-metal dielectric, low-K intermetal dielectric, and oxide, tungsten and copper CMP for 0.13m generation and beyond. He has authored or co-authored more than 40 technical papersand received 48 U.S. patents and 50 Taiwanese patents.

Dr. Jang is a member of Phi Tau Phi.

Douglas C. H. Yu received the Ph.D. degree from the Material Engineering

Department of the Georgia Institute of Technology, Atlanta.

He joined AT&T Bell Laboratories, Allentown, PA, where he was involved in work on PECVD thin-film processing, 256 K/l Mb SRAM process integra-tion and yield improvement, 0.35-/0.25-m ultrahigh performance logic de-vice development, modularBiCMOS, and MiM process integration. He later joined the R&D Department of the Taiwan Semiconductor Manufacturing Com-pany, Hsinchu, Taiwan, R.O.C., where he led a module team to successfully de-velop TSMC’s 0.5-m, 0.35-m, 0.25-m, and 0.18-m core logic technolo-gies. He performed yield improvement and transferred the process to manufac-turing. He also managed an advanced technology team to develop and qualify TSMC’s first Cu technology for 0.18-m technology. Recently, he developed TSMC’s 0.13-m Cu/low-K technology and transfers to manufacturing. Cur-rently, he manages a module team to develop TSMC Cu/low-K interconnect, gate stack, silicide, shallow-trench-isolation, etc. He has been been awarded 138 U.S. patents. He also has numerous publications in technical journals and con-ferences, all in the area of VLSI processing, device, and integration.

Mong-Song Liang received the B.S. and M. S. degrees from the National

Cheng-Kung University, Taiwan, R.O.C., in 1975 and 1977, respectively, and the Ph.D. degree in 1983 from the University of California (UC), Berkeley, all in electrical engineering and computer sciences. At UC Berkeley, his research was on the scaling of ultrathin gate dielectrics and device reliability physics.

In 1983, he joined Advanced Micro Devices (AMD), Sunnyvale, CA, where he worked on nonvolatile memory technologies (EEPROM and EPROM). From 1988 to 1992, he was with Mosel Electronics Corporation, Sunnyvale, where he worked on SRAM and embedded memory technology (DRAM, emb-SRAM, and emb-Flash) development. He was the Director of Memory Division of the R&D Organization until 1998. His current assignment is Senior Director of Advanced Module Technology Division of the R&D Organization. He is re-sponsible for all advanced modules development, including etch, thin film, dif-fusion, CMP, and Cu/low-K interconnect.