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Fabrication and characterization of field-effect transistors with suspended-nanowire channels
View the table of contents for this issue, or go to the journal homepage for more 2014 Jpn. J. Appl. Phys. 53 056504
(http://iopscience.iop.org/1347-4065/53/5/056504)
Fabrication and characterization of
field-effect transistors with suspended-nanowire channels
Chia-Hao Kuo1, Horng-Chih Lin1,2*, and Tiao-Yuan Huang1
1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C. 2National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C.
E-mail: [email protected]
Received October 13, 2013; accepted February 26, 2014; published online April 22, 2014
Novelfield-effect transistors (FETs) configured with suspended-nanowire (NW) channels were fabricated and characterized. Owing to the small aspect ratio of the etched structure, a simple wet etching process was adopted to release the NW channels. Our results show that the stiction issue can be eliminated as the channel length is sufficiently short or the air gap is sufficiently thick. In addition, the specific trends in pull-in and pull-out voltages as well as subthreshold swing (SS) with varying air gap thicknesses were investigated in terms of hysteresis characteristics. Finally, the devices were shown to withstand more than 500 cycles of operation in the cycling tests with repeatable hysteresis characteristics.
©2014 The Japan Society of Applied Physics
1. Introduction
Recently, micro-electro-mechanical field-effect transistors (MEM-FETs) have drawn much attention owing to their great potential in a number of applications. As an oscillator,1–4)
the vibrating object in the FET fabricated with a CMOS-compatible process could be employed as a resonator, enabling the miniaturization of the device and reduction of power consumption. Owing to the steep subthreshold swing (SS) it exhibits, the suspended-gate FET5–8) is considered
a good candidate for serving as a switching component. In addition, by taking advantage of the large hysteresis window, hybrid MEMS-FET devices could also be applied for building high-performance memory devices.9–13)
Although the idea of implementing hybrid MEMS-FET devices in integrated circuits (ICs) has been proposed,14–16) some important issues impede its realization in practical manufacturing and application. For example, usually the etched structure in MEMS-FETs is very deep, its formation involves a complex and rugged release process such as dry chemical etching5) and supercritical CO
2 drying.17,18)
Recently, we have proposed and demonstrated a new and simple approach to fabricating FETs with suspended-nano-wire (NW) channels with the structure shown in Fig. 1.19)In
this scheme a greatly simplified process is implemented to release the NW channels. Moreover, this new device offers a sub-100 nm air gap between the suspended-NW channels and the gate, which is beneficial for reducing operation voltage. In this work, we further investigate the character-istics of the suspended-NW channel FETs with specific focus placed on the hysteresis, endurance, and oscillation phenomena.
2. Device structure and fabrication
The fabrication flow of the suspended-NW-channel FET is illustrated in Fig. 2. It started with an in situ-doped n+ poly-Si gate deposited and patterned on an oxidized Si substrate [Fig. 2(a)]. Next, a silicon nitride (SiN) layer and a tetraethylorthosilicate (TEOS) oxide layer were deposited sequentially by low-pressure chemical vapor deposition (LPCVD) to serve as the gate dielectric and the sacrificial layer, respectively. The thickness of the SiN layer wasfixed at 20 nm, while that for the oxide is varied from 10 to 70 nm. Afterwards, an amorphous silicon (¡-Si) layer was deposited by LPCVD. To transform the¡-Si into polycrystalline phase,
the solid-phase crystallization (SPC) process was performed at 600 °C in N2 ambient for 24 h [Fig. 2(b)]. The source/
drain (S/D) pad regions were subsequently defined with a photolithographic step, followed by a standard dry etch-ing to form the S/D. Duretch-ing the etchetch-ing, poly-Si spacers abutting the sidewalls of the gate were simultaneously formed [Fig. 2(c)] and served as the NW channels connect-ing between the source and the drain. To dope the S/D, a photoresist (PR) pattern was generated to cover the central channel regions, followed by a P31+ S/D ion implantation
at a dose of 5© 1015cm¹2 at 15 keV [Fig. 2(d)]. Then, the
wafer was capped with a 300-nm-thick TEOS oxide layer deposited at 700 °C as the passivation layer [Fig. 2(e)]. Afterwards, another lithography process was carried out to define the region where the sacrificial layer would be etched off. Finally, a wet-etching process using an HF-containing solution was performed to remove the top passivation oxide
(a)
(b)
Fig. 1. (Color online) (a) Cross-sectional view and (b) top view of the suspended-NW-channel device.
layer as well as the sacrificial oxide layer between the NW channels and the silicon nitride layer [Fig. 2(f )]. Cross-sectional views of the device before and after the selective oxide etching step are shown in Figs. 3(a) and 3(b), respectively.
3. Stiction
3.1 Stiction phenomenon
Figure 4 shows the cross-sectional transmission electron microscopy (TEM) views of the NW channel of a fabricated device. The pictures were taken before the sacrificial oxide layer was removed. As shown in the figures, the ratio of the NW width (54 nm) to the sacrificial oxide layer thick-ness (70 nm) is 0.78, which is much smaller than the ratio of gate length/sacrificial layer of SG-MOSFET.5)
Accord-ingly, a simple wet-etching process could be successfully
employed to remove the sacrificial oxide layer by this approach.
Although wet etching is more convenient than the dry chemical process, occurrence of the stiction phenomenon represents one of the major issues.20,21) Indeed, such a
phe-nomenon was observed in this work. Figure 5(a) shows two distinct transfer characteristics recorded from the fabricated devices with identical structural dimensions. The measure-ments were conducted byfirst positively and then negatively sweeping gate voltage. The results show that the fabricated devices may or may not show the hysteresis phenomenon during the measurements. Devices with suspended-NW channels are expected to show hysteresis characteristics,19) and the operation principles are discussed in the next section. However, for a small portion of fabricated devices, the hysteresis window disappears (see the red dashed curves shown in this figure). In-line scanning electron microscopy (SEM) images of the two devices characterized in Fig. 5(a) are shown in Figs. 5(b) and 5(c). Figure 5(b) shows the device in which the NW channels were successfully released by the wet etching. In contrast, the other one, as shown in Fig. 5(c), shows the stiction issue during the wet-etching release process. The stiction failure during the wet-etching release process is caused by capillary force.20) As shown in
the SEM image, the NW channels stick to the gate nitride after the wet etching process and thus have insufficient capability to mechanically oscillate. This well explains why the device does not exhibit the hysteresis behavior in Fig. 5(a).
Fortunately, the observation of the stiction phenomenon is rare for the fabricated devices and can be completely suppressed as the channel length (L) of the device is suffi-ciently small. Figure 6 shows stiction probability as a func-tion of L for devices with various air gap thicknesses. As can be seen in the figure, the yield increases with decreasing channel length. For devices of the same L, the stiction probability decreases with increasing the gap thickness. These observations are attributed to the reduction in the capillary. For gaps of 40 and 70 nm, no stiction is observed as L is smaller than 1 µm.
3.2 Theoretical analysis
To further explore the above phenomenon, we try to theoretically analyze the experimental results by considering the elastic energy and surface adhesion energy stored in the
(a) (c) (b) (d) (f) (e)
Fig. 2. (Color online) Key fabricationflow of the suspended-NW-channel device.
Fig. 3. (Color online) Cross-sectional schematics of the device before and after the selective oxide etching.
Fig. 4. (Color online) Cross-sectional TEM images of a fabricated device.
Jpn. J. Appl. Phys. 53, 056504 (2014) C.-H. Kuo et al.
system as stiction occurs, as schematically shown in Fig. 7. The elastic energy arises from the distortion of the NW channel, and the distortion results in a repulsive force on the NW channel. Such a repulsive force is balanced by the attractive force due to the adhesion energy between the two contact objects. Major dimensional parameters indicated in the figure are defined as follows: Ext S/D regions are the source/drain extension parts, and TL is the total length of the suspended nanowire including the channel and the source/ drain extension parts, i.e., TL= L + 2Ext S/D, w and t are the width and thickness of the NW channel, respectively, and g is the initial gap thickness. The x- and y-directions are parallel and perpendicular to the source-to-drain direction, respectively. In Fig. 7, x= 0 corresponds to the end of the external source. It is assumed that the channel is in contact with the gate nitride from x= s to TL ¹ s with a bended
shape symmetrical to x= 0.5TL. Note that s < 0.5TL for stiction to occur. The displacement of the NW channel from the equilibrium position along the y-direction is expressed as u(x). To simplify the analysis, we approximate u(x) with the following form:
uðxÞ ¼ gsin sx for 0 x s, g for s x TL 2 . 8 > < > : ð1Þ
The elastic energy UEstored in the distorted suspended NW
channel is then given by22)
UE¼ EI 2 ZTL=2 0 2 d2uðxÞ dx2 2 dx; ð2Þ
where E is Young’s Modulus and I is the area moment of inertia. As shown in Fig. 4, the cross-sectional shape of the NW is like a quadrant with the radius of w, so the area moment of inertia could be expressed as23)
I¼ 16 4 9 w4¼ w4: ð3Þ Gate Voltage (V) -3 -2 -1 0 1 2 3 4 5 6 Drain Curr ent (A) 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 Suspended Stiction Gap=70nm L = 4 µm VD = 0.1 V
(a)
Fig. 5. (Color online) (a) Transfer characteristics of the fabricated devices with and without stiction. Corresponding SEM images of the devices (b) without and (c) with stiction.
Fig. 7. (Color online) Top-view diagram of suspended-NW channel adhering to gate nitride.
Channel Length (µµm) 0 1 2 3 4 5 Stiction Pr obability (%) 0 5 10 15 20 25 30 g = 70nm g = 40nm g = 10nm
Fig. 6. (Color online) Stiction probability as a function of channel length for released suspended-NW-channel FETs.
Equation (2) is solved with the boundary conditions of u(0)= 0 and u(s) = g and has the solution
UE ¼
E4w4g2
2s3 : ð4Þ
On the other hand, surface adhesion energy22)(only stored in
the contact part, namely, s x TL s) is given by US¼ swðTL 2sÞ as s < 0:5TL; ð5Þ
where£sis the effective adhesion energy per unit area in the
contacted portion, and w(TL¹ 2s) is the contact area. Note that the value of USmay vary from device to device and is
essential in determining the occurrence of stiction. It depends on the surface conditions,24,25)such as the surface roughness and formation of native oxide, of the contact materials (nitride and poly-Si NW channel). For stiction to occur, £s
must be larger than a threshold value, and the extent of the contact area (or s) depends closely on£s. In equilibrium, the
total energy (UT) of the system should be minimal, which can
be defined as22)
dUT
ds ¼
dðUEþ USÞ
ds ¼ 0: ð6Þ
Substitution of Eqs. (4) and (5) into Eq. (6) yields
s¼ 3E
4w3g2
4s
1=4
: ð7Þ
To prevent stiction, the restoring force executed by the bended NW must be sufficiently large to overcome the stick-ing force executed by the surface adhesion energy, which is dependent on £s and the contact area w(TL¹ 2s) [Eq. (5)].
As mentioned above, s is smaller than 0.5TL as stiction happens (Fig. 7). To address this point, Eq. (7) can be further modified to express £sas a function of the structural
param-eters, and then the threshold value s for stiction to happen can be defined as s¼ 12E4w3g2 s4 12E4w3g2 ð0:5TLÞ4 ¼ s: ð8Þ
The above expression indicates that s increases with increasing g and decreasing TL (or L). The predicted trends are consistent with the results shown in Fig. 6, that is, the stiction probability increases as L increases or g decreases.
4. Electrical characteristics of suspended-NW-channel TFTs
4.1 Hysteresis characteristics
Figure 8 shows the typical hysteresis characteristics of a suspended-NW-channel device with a channel length of 1 µm and an air-gap thickness of 40 nm. Definitions of several major electrical parameters are shown in the figure and described as follows. During the forward sweeping, the gate voltage (VG) corresponding to a jump in drain current (ID) is
defined as the pull-in voltage Vpi. The pull-out voltage Vpois
defined as VGwhen IDdrops to the level dominated by the
off-state leakage during the reverse sweeping measurement. The threshold voltage Vthis simply defined as VGwhen IDreaches
1© 10¹9A. The hysteresis window is defined as the differ-ence in Vthbetween the forward (Vth,F) and reverse sweeping
(Vth,R) measurements. SS values of different subthreshold
regions are denoted as SSF, SSR, and SSpi, as specified in the
figures. Among the parameters, SSpiis the smallest.
The operation of the suspended-NW-channel device is described as follows: In the forward sweeping measurement, an abrupt increase in IDat Vpi(1.35 V in thefigure) and then
an ultra low SSpi of 55 mV/dec are observed. This is an
indication that the pull-in action of the suspended-NW channels is triggered by the increase in gate voltage. How-ever, unlike the observation reported in a previous work on SG-MOSFET5) that the rise in ID is dramatic and sudden,
the current remains at a modest level after pull-in and continuously increases with increasing VG. This is ascribed to
the fact that the current jump is limited by the small contact region at the channel center during the initial pull-in stage.19) After pull-in, the contact area of the NW channel with the side gate gradually increases with increasing gate voltage, so does the drain current. The aforementioned action reflects on the subthreshold characteristics of the device. In Fig. 9, SS is shown as a function of ID. The transition from a low-SS
region corresponding to the pull-in action to the relatively stable region with a higher SS results from the aforemen-tioned process. More interestingly, in Fig. 9, we can also see that the SS seems to oscillate in the IDregion between 10¹9
and 10¹7A. Thisfinding implies that the vibration action of the suspended subject may take place as it is in contact with the gate nitride, although the process is complicated and needs further study.
Drain Current (A)
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 SS (mV/dec) 0 60 120 180 240 300 360 420 L = 1 µm, VD=0.1V Air Gap =40 nm WNW=54nm
Fig. 9. (Color online) SS as a function of IDfor the device characterized in Fig. 8.
Fig. 8. (Color online) Hysteresis characteristics of the suspended-NW-channel device under forward and reverse sweeping.
Jpn. J. Appl. Phys. 53, 056504 (2014) C.-H. Kuo et al.
In the reverse sweeping measurement, owing to the fact that the charges that were induced during the forward sweeping still reside in the channel,19) V
th,R is significantly
lower than Vth,F. Moreover, no abrupt current drop is seen in
the reverse sweeping. This indicates that the detachment of the NW channels occurs gradually. Another feature is the asymmetric SS of forward and reverse sweeping. As shown in Fig. 8, the SSF(³198 mV/dec) extracted in the IDrange
from 10¹11 to 10¹9A is steeper than that in the reverse sweeping (SSR³ 245 mV/dec). This effect can be explained
by the appearance of an additional adhesive force as the channel is in contact with the gate nitride.26)This force tends to impede the detachment of suspended NWs from the gate nitride. As a result, a significant degradation in SS during the reverse sweeping can be observed. Finally, as the gate voltage is sufficiently low, the channel is eventually released and the device returns to the open-gap state.
The measured hysteresis characteristics with various drain voltages (VD) are illustrated in Fig. 10, which shows that an
increase in VDtends to reduce Vpi. A higher VDmeans that the
electrons are easier to be dragged into the channel from the source and thus facilitate the pull-in of the channel. On the other hand, the pumping out of the stored electrons in the channel during the pull-out period is faster as VDincreases,
resulting in a more positive Vpo, as shown in the figure,
although the effect is less profound than that for Vpi.
4.2 Effects of air gap thickness
Figure 11 shows the hysteresis characteristics of the fabricated devices with various air gap thickness of 10, 40, and 70 nm. The air-gap thickness dependence on pull-in voltage has been briefly discussed in our previous work,27)
in which it was found that a smaller gap thickness led to a smaller pull-in voltage owing to the smaller electrostatic force needed to be overcome. Another important indicator of the switching characteristics is the SS; the extracted results (SSpi, SSF, and SSR) are plotted as a function of air gap
thickness in Fig. 12. As can be seen, the device with a 70 nm air gap thickness shows a smaller SSpithan the others with a
smaller air gap thickness. This observation is reasonable as the increase in drain current after pull-in increases with increasing gap thickness.
Nevertheless, SSFand SSR exhibit trends opposite to that
of SSpi, as shown in Fig. 12. As has been mentioned, SSFand
SSRare extracted in the drain current range of 10¹11–10¹9A
where the portion of the NW channel in contact with the gate nitride is modulated by the gate voltage. At this stage, for the device with a larger gap thickness, a larger resilient force is exerted on the channel owing to the larger displacement. This affects the capability of the applied gate voltage to manipulate the channel; thus, SS is degraded. In addition, it can be seen that pull-out voltage (Vpo) becomes more
negative for devices with a larger gap thickness. This is attributed to the high adhesive force, which is present as the channel contacts the gate nitride. It prevents the detachment of the NW channel from gate nitrides; therefore, an additional repulsive electrostatic force by negative gate bias is needed to effect the detachment.
4.3 Reliability characteristics
In this section, we address the endurance properties of the fabricated devices. Figure 13(a) shows the typical endurance characteristics of a device in which the threshold voltages under forward and reverse modes were recorded during the cycling tests. The air gap of the device is 40 nm. In thefigure,
Gate Voltage (V)
Drain Current (A)
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 0.5V 0.1V 0.05V L = 1 µm, VD=0.1V Air Gap =40 nm WNW=54nm -1 0 1 2 3 4
Fig. 10. (Color online) Hysteresis curves of suspended-NW-channel FETs with drain voltages of 0.05, 0.1, and 0.5 V.
Gate Voltage (V) Drain Curr ent (A) 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 70nm Air Gap 40nm Air Gap 10nm Air Gap L = 1 µm VD = 0.1 V WNW=54nm -3 -2 -1 0 1 2 3 4 5
Fig. 11. (Color online) Hysteresis curves of suspended-NW-channel FETs with air gap thicknesses of 70, 40, and 10 nm.
Air Gap Thickness
10nm 40nm 70nm SS (mV/dec) 0 50 100 150 200 250 300 350 SSpi SSF SSR
Fig. 12. (Color online) Extracted SS of suspended-NW-channel FETs with air gap thicknesses of 70, 40, and 10 nm.
three stages denoted as regions A, B, and C are identified. In regions A (cycles 1–100) and B (cycles 100–500), both Vth,F
and Vth,Rslightly increase with increasing number of cycles.
To gain more insight into these results, Fig. 13(b) shows the ID–VG curves of the device measured at various number of
cycles. It can be seen that there is no obvious change in SS in thefirst 100 cycles (blue solid curves); thus, the Vth shift
induced in this stage is mainly attributed to the electron trapping in the nitride layer28–30)while the interface degrada-tion can be neglected. However, from cycles 100–500 (green dashed curves), both Vth,Fand Vth,Rincrease and accompanied
by a rise in the subthreshold swing, as shown in Fig. 13(b). This indicates that the interface degradation is no longer negligible. When the cycle reaches beyond 500, Vth,F and
Vth,R become comparable and even show a reverse order
while the occurrence of the hysteresis is limited to the current <10¹10A. These are signs of device failure. The failure is attributed to the accumulation of degradation induced in the dielectric and at the interface. To improve the endurance, improving the quality of the gate dielectric is essential.
Figure 14 shows the endurance characteristics of a device with a larger air gap of 70 nm. It is seen that obvious window shrinkage occurs just after 60 cycles. The measured transfer curves of the device (data not shown) indicate that the
degradation is primarily due to the increase in the sub-threshold swing of the device. The performance is much worse than the results shown in Fig. 12. A similar observa-tion was also documented previously31) and the cause is
attributed to the larger strain resulting from the larger displacement of the channels during operation. The deformed channel is expected to suffer from the larger stress as the gap is thicker; consequently, a larger number of surface defects are generated in a limited number of operation cycles, leading to the quick shrinkage in the widow, as shown in Fig. 14. In short, although a thicker gap tends to improve the stiction issue as demonstrated in Sect. 3, it would also deteriorate the reliability of the devices. These results indicate that there exists a tradeoff between device performance and yield in selecting the gap.
5. Conclusions
Novel devices with suspended poly-Si NW channels were fabricated and characterized in this study. In this scheme, the suspended poly-Si NW channels are separate from the side gate by a nanometer-scale air gap. Owing to the low ratio of the etch depth to the thickness of the sacrificial layer, simple wet etching can be performed to release the NW channel. Stiction of the NW channels after the release process is observed and its occurrence destroys the hysteresis operation of the device. Fortunately, the problem can be eliminated as the channel is sufficiently short or the air gap is sufficiently thick.
From the hysteresis characteristics of the devices, an SS smaller than 60 mV/dec is observed at the pull-in point. The effects of gap thickness on device performance are also addressed in this work. The endurance test confirms that successful operation of the devices can be repeated retained more than 500 times. Accumulation of degradation inside and on the surface of the gate dielectric would lead to the collapse of the hysteresis characteristics.
Acknowledgments
This work was sponsored in part by the Ministry of Science and Technology, Taiwan under contract No. NSC-102-2221-E-009-133, the NCTU-UCB I-RiCE program under contract No. NSC-103-2911-I-009-302, and the Ministry of Educa-tion in Taiwan under the ATU Program.
(a)
Cycle Number
Threshold V
oltage (V)
(Forwrd & Reverse)
-1 0 1 2 3 4 5
Region A Region B Region C
Reverse Forward L = 1 µm w/ 40 nm Air Gap 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 (b) Gate Voltage (V) -3 -2 -1 0 1 2 3 4 5 6 Drain Curr ent (A) 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 Cycle 1-100 Cycle 100-500 Clcye 550-700 L = 1 µm w/ 40 nm Air Gap
Fig. 13. (Color online) (a) Typical endurance characteristics of suspended-NW-channel FET with air gap thickness of 40 nm. (b) Hysteresis I–V curves of test device selected from several cycles of measurements.
Cycle Number 10 20 30 40 50 60 Threshold V o ltage (V )
(Forwrd & Reverse)
0 1 2 3 4 L = 1 µm w/ 70 nm Air Gap
Fig. 14. Endurance characteristics of suspended-NW-channel FET with air gap thickness of 70 nm.
Jpn. J. Appl. Phys. 53, 056504 (2014) C.-H. Kuo et al.
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