CMOS 2.4 GHz receiver front end with area-efficient
inductors and digitally calibrated 901 delay network
C.-H. Wu, C.-C. Tang, K.-H. Li and S.-I. Liu
Abstract: A 2.4 GHz CMOS Hartley image-reject receiver utilising the area-efficient inductors and a digitally calibrated 901 delay network is proposed. Compared with the conventional planar inductor, the proposed area-efficient inductor saves 80% of the silicon area without degrading the quality factor. In addition, employing the digitally calibrated 901 delay network rather than the RC–CR network can make the traditional Hartley receiver tolerant to temperature and process variations. A prototype chip with a fully integrated low-noise amplifier followed by the proposed image-reject mixer has been fabricated in a 0.35 mm single-poly–four-metal standard CMOS technology and the active area is 3.13 mm2. While operating at 2.4 GHz, this receiver achieves a 30 dB image-rejection ratio, a 3 dB third-order input intermodulation intercept point, and an 11 dB noise figure with 54 mW power consumption from a 3.3 V supply.
1 Introduction
Due to the tremendous demands of portable wireless devices, providing a low cost solution is becoming increasingly more important. For non-zero IF receiver systems, the image signal may corrupt the desired signal. Several new techniques and receiver architectures[1, 2]have been proposed to suppress the image signal.
In this work, the Hartley receiver[3]is studied because of its simpler architecture and lack of second image problem. Two main nonidealities cause the incomplete image cancellation. One is the gain and phase imbalances due to the inaccurate quadrature LO signals and mismatched I/Q signal paths. The other originates from the imperfect 901 shift network, which is implemented by a RC–CR network in practice. Due to process variations, the absolute values of resistors and capacitors in the RC–CR network cannot be well controlled by using only the simple circuit technique. Hence, we wished todevelop an accurate shift-by-901 stage toreplace the RC–CR network in the Hartley image-reject receiver.
Besides the architecture passive devices, such as the inductors, on the lossy substrate also significantly influence the performance of the receiver. Much effort has been put into increasing the quality factors of the on-chip inductors [4–6]. To reduce the on-chip inductor area, we propose a new configuration inductor, which is not only small in size but also has a quality factor comparable to that of the planar inductor.
2 Architecture
The Hartley image-reject receiver is shown in Fig. 1. This topology mixes the RF input signal with the quadrature LO signals and shifts the down-converted signal in one branch by 901. The signals in these twobranches are then added together to obtain the desired signal and cancel the image signal. In this technique, the amplitude and the phase mismatches between the quadrature LO signals cause the incomplete image cancellation. Given that the phase error is f, the image-rejection ratio (IRR) can be derived as[7]
IRR¼ðDALO=ALOÞ
2
þf2
4 ð1Þ
where ALOis the amplitude of the LO signal and DALOis
the amplitude difference between the qudarature LO signals. It should be noted that (1) is true only when the phase difference between these twosignals (at points B and C) is 901. In the traditional Hartley image-reject receiver, a RC–CR network is implemented to provide the 901 phase difference between the twosignal paths. The simulation indicates that the magnitude responses of the two signal paths are equal only at the one frequency, which is specified by the RC constant. However, the on-chip passive devices, especially the resistors, often suffer from mismatches and inaccurate values due to the process variations. The mismatches of the resistors and capacitors between two signal paths introduce the magnitude and phase errors. It has been proved that slight deviations of resistance and capacitance will dramatically degrade the IRR[7].
B 90° RF input sin LOt cos LOt low-pass
filter adder outputIF
A
C
Fig. 1 Architecture of Hartley image-reject receiver C.-H. Wu and S.-I. Liu are with the Electronic Circuits Laboratory,
Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, Republic of China C.-C. Tang is with the MediaTek Corp., Science-Based Industrial Park, HsinChu, Taiwan, Republic of China
K.-H. Li is with the SiS Corp., Science-Based Industrial Park, HsinChu, Taiwan, Republic of China
rIEE, 2003
IEE Proceedings online no. 20030528 doi:10.1049/ip-cds:20030528
Our proposed modified Hartley image-reject receiver architecture is shown in Fig. 2. It includes a low-noise amplifier, mixer, and the digitally calibrated 901 delay network, which consists of a 901 delay circuit and an off-chip 3-bit digital-to-analogue converter (DAC). This proposed circuit allows the system to adjust the 901 delay network to compensate for inaccurate delay results from the process variations.
3 Circuit designs
3.1
Area-efficient inductor
On-chip inductors usually occupy an enormous die area resulting in increased cost. An area-efficient inductor structure has been proposed to significantly minimise the size of the inductor without degrading its quality factor.
The conventional stacked inductor [8] consists of the series connected spiral inductors in the different metal layers. Every spiral inductor in the different metal layers may have the same or different turns. The wires wind downward from the top metal layer to the bottom one. Our proposed area-efficient inductor consists of at least two stacked inductors with series connections and every stacked inductor has only one turn in every metal layer. Figure 3 shows the structure of the proposed area-efficient inductor [9]. There are two advantages of this proposed area-efficient inductor: one is the small area, and the other is the higher self-resonance frequency fSR. Compared with the planar
inductor, the area-efficient inductor saves 80% of the die area without degrading the inductance and the quality factor. The fSRof the area-efficient inductor is higher than
that of a conventional stacked inductor[9].
To predict the performances, such as the quality factor (Q) and the fSR, of the area-efficient inductor, the equivalent
capacitance and the series resistance have tobe obtained. For simplicity, the following assumptions are made: (i) Assume the spacing between metal lines can be ignored because it is much smaller than the metal width;
(ii) Voltage is constant in the same turn and it is determined by averaging the voltage of the previous and the next turn; (iii) Voltage drop is proportional to the length of the metal line.
Suppose we have an area-efficient inductor with inner radius r, metal width w, with n turns, and m layers. The lengths of turns 1yn are l1, l2, y, ln, respectively, and the
total length is ltot. A1, A2, y, Anrepresent the areas of the
tracks from the first to the nth turn, respectively. The voltage profile of an m-layer n-turn area-efficient inductor is shown in Fig. 4. With tedious evaluation, the total equivalent capacitance of the area-efficient inductor can be obtained as Ceq¼ Xn k¼1 fCm;m1þ Cm1;m2þ . . . þ C2;1gAkð lk mÞ 2 þ C1;sfA1ð1 l1þ 1 2ml1Þ 2þ A 2ð1 l1 1 2ml2Þ 2 þ A3ð1 l1 l2 l3þ 1 2ml3Þ 2þ . . .g ð2Þ
where Cm,m1 represents the capacitance per unit area
between the mth and the (m1)th layers and C1,S is the
capacitance per unit area between the lowest metal layer (metal layer 1) and the substrate. In the same manner, to analyse an m-layer n-turn conventional stacked inductor, the total equivalent capacitance is derived as
Ceq; stacked¼ Xn k¼1 1 4fCm; m1þ Cm2; m3þ . . . þ C3; 2g Ak 4 m 2 mdðkÞ 2 m 2 þX n k¼1 1 4fCm1; m2þ Cm3; m4þ . . . þ C2; 1g Ak 2 mdðkÞ þ 2 mdðk 1Þ 2 þX n k¼1 1 4C1; sAk 1 mdðk 1Þ þ 1 mdðkÞ 2 ð3Þ RF input LO input 90° delay circuit LOQ LOI LNA 3-bit DAC 180° hybrid second-order passive polyphase filter digitally calibrated 90° delay network IF output RF interstage match
Fig. 2 Proposed image-reject receiver architecture with digitally calibrated 901 delay network
Fig. 3 Architecture of the area-efficient inductor
3 n mth layer n 3 signal direction (m−1)th layer (m−2)th layer 1st layer V0 0 V0(1−d(n−1)) V0(1−d(2)) V0(1−d(1)) 2 2 1 1
Fig. 4 Voltage profile of n-turn m-layer proposed area-efficient inductor
After deriving the equivalent capacitance, the series resistance is alsostudied. Unlike the equivalent capacitance, the series resistance is a complex combination of many effects, such as the skin effect, eddy current effect, and the magnetic coupling effect. Hence, it is difficult to obtain the general analytical form. In our work, an empirical equation, given as (4), is adopted to estimate the series resistance of the area-efficient inductor
Rs¼ RDC 1þ 0:17f þ Bf2
ð4Þ In (4), RDC is the resistance at DC, f is the operating
frequency in GHz, and the coefficient B is very small and can be ignored in this case. It should be noted that (3) is process- and geometry-dependent.
Using an inductance simulator, such as ASITIC[10]or SONNET, the Q and fSRcan easily be predicted. Based on
(2)–(4) and TSMC 0.35 mm CMOS single-poly–four-metal (1P4M) CMOS process parameters, the equivalent capaci-tance of the 4-turn 2-layer conventional stacked inductor and proposed area-efficient inductor with different inner radius (r) and metal width (w) are sho wn in Figs. 5a and Fig. 5b respectively. The analytic simulation reveals that the equivalent capacitance of the area-efficient inductor is much lower than that of conventional stacked inductor for all geometrical parameters.
Toverify the predicted performances, which are calcu-lated from (2)–(4), Table 1 shows the predicted and measured Ceq, Q and fSR of the area-efficient and
conventional stacked inductors in a 0.35 mm 1P4M CMOS process. It can be observed that predicted performances quite coincide with the measurement results irrespective of the area-efficiency or the stacked inductors.
3.2
Low-noise amplifier and down-conversion
mixer
The two-stage common source low-noise amplifier (LNA), as shown in Fig. 6, with the fully on-chip LC-matching is employed in this receiver. A stand-alone LNA test-key was fabricated in a 0.35 mm 1P4M CMOS technology and its active area is 280 640 mm2. By virtue of the area-efficient inductors, the die size of this LNA is very small compared with the other LNAs [11, 12]. Experimental results show that S11, S22 and S21 at 2.4 GHz are14 dB, 13 dB and 10 dB, respectively. The measured NF50is 4.8 dB.
Twoidentical Gilbert-cell double-balance mixers[13]are chosen to down-convert 2.4 GHz RF to 1.5 MHz IF in the quadrature phase. At the RF port, a series capacitor performs AC coupling and a shunt inductor acts as an RF choke to give the bias voltage. Quadrature LO signals are generated by passing the differential LO signals through an on-chip second-order passive polyphase filter, whose schematic is shown in Fig. 7. An off-chip 1801 hybrid is used togenerate the differential LO signals.
3.3
90 1 delay network and combiner
The 901 delay circuit consists of two cascaded delay cells. Based on the conventional delay cell circuit [14], two additional MOS capacitors are added at the output terminals symmetrically, as shown in Fig. 8, to achieve the desired phase delay at 1.5 MHz. An off-chip control circuit, which includes the 3-bit DAC, fine tunes the delay phase by adjusting the voltage of the terminal Vbp. Figure 9 shows the
simulated transient response of the digitally calibrated 901 delayed network. It demonstrates that the output signal, which passes through the delay network, is 901 phase shifted tothe input signal.
After passing through the 901 delay circuit, the desired signals in the I and Q channels are in phase but the image signals are out of phase. A combiner, shown in Fig. 10, adds the signals from the I and Q channels together to cancel the image signal. MC1 and MC2 are added to control the bias current to adjust the amplitude balance, and the control signal comes from the off-chip control circuit. For example, if tuning the voltage of the control terminal, say bbc1, then the amplitude of the signal at out+ can be adjusted as shown in Fig. 11.
4 Experimental results
The proposed image-reject receiver was fabricated in a 0.35 mm 1P4M CMOS techno lo gy. The to tal active area is 3.13 mm2without the test-keys, and the die photo is shown in Fig. 12. The circuits have been tested in a chip-on-board assembly while operating under a 3.3 V power supply. Figure 13 shows the measured transient response of the 901 delayed network test-key. It shows that the phase difference between the input and output signals is adjusted to 901 by the delayed network with conjugation of an off-chip 3-bit DAC. Applying a40 dBm 2.4 GHz RF signal, a 40 dBm 2.397 GHz RF image signal and a 10 dBm 2.3985 GHz LO signal, the signal gain at 1.5 MHz IF is 0 dB and the image rejection ratio is 30 dB without an off-chip preselect filter. The measured gain is low because no amplifiers
20 30 40 50 0 50 100 150 200 250 equivalent capacitance, fF inner radius, µm stacked proposed 0 100 200 300 400 500 600 equivalent capacitance, fF metal width, µm 20 15 10 5 stacked proposed a b
Fig. 5 Equivalent capacitance
a Different inner radii with w¼ 10 mm, m ¼ 2 b Different metal widths with r¼ 40 mm, m ¼ 2
Table 1: Predicted and measured Q and fSRat 2.4 GHz of 4-layer area-efficient and stacked inductors with 1 lm spacing and 10 lm (*¼ 15 lm) metal width Inductors L (nH) Inner radius (mm) Turns Sim. Ceq(fF) Meas. Ceq.(fF) Sim. fSR(GHz) Meas. fSR(GHz) Sim. Q Meas. Q Stacked 1 7.3 30 2 52.4 54.2 8.2 7.8 5.24 5.23 Area-efficient 1 9.7 40 2 37.8 35.3 8 8.6 1.85 2.03 Area-efficient 2* 7.5 30 2 32.5 31.2 10 10.4 3.58 3.5 input output VDD VDD
indicates the proposed area-efficient inductor 5.5 nH 5.8 nH 0.26 pF 0.6 pF 4.7 nH bias 4.6 nH
Fig. 6 Schematic of the single-ended double-stage LNA
in1 in2 in3 in4 out1 out2 out3 out4
Fig. 7 Two-stage passive poly-phase filter
in− in+
out+ out−
bias
Vbp
Fig. 8 Schematic of the delay cell
0 1 2 3 4 −4 −2 0 2 4 6 time, µs voltage, mV
Fig. 9 Simulated transient response of the 901 delayed network
FF input signal - - - - o utput signal V1+ out+ M5 M6 M1 M2 M3 M4 V1− V2− V2+ out− bias bbc2 bbc1 MC1 MC2 R R
Fig. 10 Schematic of the combiner
0.5 1.0 1.5 2.0 2.5 3.0 0 0.2 0.4 0.6 0.8 1.0 gain, dB bbc1, V out +
Fig. 11 Relationship between the control voltage and output voltage in the combiner
compensate for the loss of the delay cells and the combiner. In spite of the gain, this circuit indeed performs the image-rejection function. The measured intermodulation intercept
point is 3 dBm and the total noise figure (NF) is 11 dB with 54 mW power consumption. This receiver can correctly down-convert a 2.4 GHz GFSK signal to 1.5 MHz IF band. The GFSK signal emulates a Bluetooth RF signal with a modulation index of 0.35, 200 kHz frequency deviation, and 1 MHz symbol rate. Figure 14 shows the GFSK spectrum at intermediate frequency. Table 2 summarises the char-acteristics of this 2.4 GHz receiver.
5 Conclusions
An image-reject receiver has been proposed. Inaccurate delay resulting from the temperature and process variations can be mitigated by the digitally calibrated 901 delay network. In addition, the chip also adopts the proposed area-efficient inductor to significantly save the silicon area. Furthermore, the proposed method can predict the Q and fSRof various inductors, such as the stacked and the
area-efficient inductors. According to the experimental results, this receiver can meet the Bluetooth in-band image rejection specification.
6 Acknowledgment
The authors would like to thank the National Chip Implementation Center (CIC), Taiwan, Republic of China for fabricating this chip.
7 References
1 Samavati, H., Rategh, H.R., and Lee, T.H.: ‘A 5-GHz CMOS wireless LAN receiver front end’, IEEE J. Solid-State Circuits, 2000, 35, (5), pp. 765–772
2 Der, L., and Razavi, B.: ‘A 2-GHz CMOS image-reject receiver with sign-sign LMS Calibration’. Proc. IEEE Int. Solid-State Circuits Conf., ISSCC, San Francisco, CA, USA, 2001, pp. 294–295 3 Hartley, R.: US Patent 1,666,206, April 1928
4 Yue, C.P., and Wong, S.S.: ‘On-chip spiral inductors with patterned ground shields for Si-based RF ICs’, IEEE J. Solid-State Circuits, 1998, 33, (5), pp. 743–752
5 Burghartz, J.N., Soyuer, M., and Jenkins, K.A.: ‘Microwave inductors and capacitors in standard multilevel interconnect silicon technology’, IEEE Trans. Microw. Theory Tech., 1996, 44, (1), pp. 100–104 6 Chang, J.Y.-C., Abidi, A.A., and Gaitan, M.: ‘Large suspended
inductors on silicon and their use in a 2-mm CMOS RF amplifier’, IEEE Electron Device Lett., 1993, 14, pp. 246–248
7 Razavi, B.: ‘RF microelectronics’ (Prentice-Hall, Eaglewood Cliffs, NJ, 1998), Chap. 5, p. 143
8 Koutsoyannopoulos, Y., Papananos, Y., Bantas, S., and Alemanni, C.: ‘Novel Si integrated inductor and transformer structures for RF IC design’. Proc. Int. Symp. on Circuits and systems ISCAS, Orlando, FL, USA, 1999, Vol. 2, pp. 573–576 LNA 2 nd -order passive poly-phase filter I/Q mixer
90-degree delay cells
combiner
90-degree delay cells testkey
VCO testkey
Fig. 12 Die photo of the test chip
0 V C2 C1 pha 0° low signal amplitude C2 C1 pha 88.6° low signal amplitude 2 1 average IF : −30 dBm@ 1.5 MHz V1p-p : 50 mV V2p-p : 50 mV V1/V2 : −0.5 dB
Fig. 13 Measured transient waveform of the 901 delayed network test-key
S
Fig. 14 GFSK output spectrum at IF
Centre frequency: 1.5 MHz Span: 2 MHz
Marker:1.483 MHz, 62.50 dBm
Table 2: Performances summary of the test chip
Value RF 2.4 GHz LO 10 dBm at 2.3985 GHz IF 1.5 MHz IF gain 0 dB IIP3 3 dBm IRR 30 dB NF 11 dB Sensitivity 80 dBm Power consumption 54 mW @ 3.3 V Process TSMC 0.35 mm 1P4M CMOS Area 3.13 mm2
9 Tang, C.C., Wu, C.H., and Liu, S.I.: ‘Miniature 3D inductors in standard CMOS process’, IEEE J. Solid-State Circuits, 2002, 37, (4), pp. 471–480
10 Niknejad, A.M., and Meyer, R.G.: ‘Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs’, IEEE J. Solid-State Circuits, 1998, 33, (10), pp. 1470–1481
11 Zhou, J.J., and Allstot, D.J.: ‘Monolithic transformers and their application in a differential CMOS RF low-noise amplifier’, IEEE J. Solid-State Circuits, 1998, 33, (12), pp. 2020–2027
12 Kim, C.S., Park, M., Kim, C.H., Hyeo n, Y.C., Yu, H.K., Lee, K., and Nam, K.S.: ‘A fully integrated 1.9-GHz CMOS low-noise amplifier’, IEEE Microw. Guided Wave Lett., 1998, 8, (8), pp. 293–295 13 Sullivan, P.J., Xavier, B.A., and Ku, W.H.: ‘Low voltage performance
of a microwave CMOS Gilbert cell mixer’, IEEE J. Solid-State Circuits, 1997, 32, (7), pp. 1151–1155
14 Maneatis, J.G.: ‘Low-jitter process-independent DLL and PLL based on self-biased techniques’, IEEE J. Solid-State Circuits, 1996, 31, (11), pp. 1723–1732
