行政院國家科學委員會專題研究計畫 成果報告

行政院國家科學委員會專題研究計畫 成果報告

應用於下世代 CMOS 元件之簡易且新穎式雷射製程技術 研究成果報告(精簡版)

計 畫 類 別 ： 個別型

計 畫 編 號 ： NSC 98-2218-E-216-002-

執 行 期 間 ： 98 年 04 月 01 日至 99 年 06 月 30 日 執 行 單 位 ： 中華大學微電子工程學系

計 畫 主 持 人 ： 吳建宏

計畫參與人員： 碩士班研究生-兼任助理人員：洪瑞陽 碩士班研究生-兼任助理人員：黃俊哲

報 告 附 件 ： 出席國際會議研究心得報告及發表論文

處 理 方 式 ： 本計畫涉及專利或其他智慧財產權，2 年後可公開查詢

中 華 民 國 99 年 09 月 30 日

行政院國家科學委員會補助專題研究計畫 ■成果報告

□期中進度報告 應用於下世代 CMOS 元件之簡易且新穎式雷射製程技術

計畫類別： ■ 個別型計畫 □整合型計畫 計畫編號：NSC 98－2218－E－216－002－

執行期間： 98 年 04 月 01 日至 99 年 06 月 31 日 執行機構及系所：中華大學微電子系

計畫主持人：吳建宏 共同主持人：

計畫參與人員：吳建宏、洪瑞陽、黃俊哲、林智偉

成果報告類型(依經費核定清單規定繳交)： ■ 精簡報告 □完整報告

本計畫除繳交成果報告外，另須繳交以下出國心得報告：

■ 赴國外出差或研習心得報告

□赴大陸地區出差或研習心得報告

□出席國際學術會議心得報告

□國際合作研究計畫國外研究報告

處理方式：除列管計畫及下列情形者外，得立即公開查詢

□涉及專利或其他智慧財產權，□一年□二年後可公開查 詢

中 華 民 國 99 年 09 月 29 日

行政院國家科學委員會研究計畫成果報告

應用於下世代 CMOS 元件之簡易且新穎式雷射製程技術 計畫編號： NSC 98－2218－E－216－002－

全程執行期間： 98 年 04 月 01 日至 99 年 06 月 31 日

主持人：吳建宏 助理教授 執行單位：中華大學微電子工程系

中文摘要

對於發展下世代 CMOS 元件之簡易且新

穎式雷射技術而言，將是半導界的主流。本 研究團隊於研發出金屬閘極搭配氧化鑭高 介電係數介電層的 n 型金氧半場效電晶 體。接著我們更進一步利用高介電常數氧化 鑭來製作鍺金氧半場效電晶體，二氧化矽做 為介面層，氮化鉭做為金屬閘極。利用雷射 退火的方式去達到改善元件的特性，得到低 的片電阻值 68 Ω/sq，理想因子為 1.3 和 在源極和汲極的 PN 接面得到了大的順向/

逆向電流.雷射退火後的閘極優先

TaN/La2O3/SiO2/Ge n 型金氧半場效電晶 體，在等效氧化層厚度為 1.9nm 下，顯示出 高的遷移率 603 cm²/Vs，在 0.75 MV/cm 下 遷移率為 304 cm²/Vs。

The small bandgap (EG) Ge shows high potential for MOSFET application due to both higher electron and hole mobility than Si.

However, the difficult challenges are the high leakage current of small EG Ge, poor high-κ/Ge interface property, and low doping activation at ion-implanted source-drain [1]-[16]. To address the leakage current issue, we pioneered the defect-free Ge-on-insulator (GOI or GeOI)[1] structure and ultra-thin

body Ge-on-Si[11]. The high-κ/Ge interface property can also be improved by using an ultra-thin robust SiO2 interfacial layer.

Nevertheless, the poor doping activation by RTA is still an issue, while the high temperature RTA degrades the mobility by Ge out-diffusion and forming poor interface.

Although a gate-last process with GeO2

dielectric was developed for this purpose [11]-[15], the gate-first process is still attractive for much simple process. Besides, the filling in narrower gate opening with both high-κ and metal using gate-last process is another concern, since Ge is expected to implement in 15~10 nm node CMOS. In this paper we have used low energy laser annealing [16] to improve the doping activation of ion-implanted source-drain and preserve good high-κ/Ge interface, while laser annealing is also essential for ultra-shallow junction. High performance gate-first TaN/La2O3/SiO2/Ge n-MOSFET was obtained using laser annealing, with high peak mobility of 603 cm²/Vs and 0.75 MV/cm mobility of 304 cm²/Vs at small 1.9 nm EOT. The good mobility at high effective electric field (Eeff) is required for highly scaled MOSFET with small EOT. These results are beyond the best reported data for gate-first metal-gate/high-κ/Ge n-MOSFET at small

一、 簡介

EOT <2 nm.

二、 實驗步驟

Standard 2-in p-type Ge (100) wafers were used for the experiments. After standard clean, ultra-thin 0.8 nm SiO2 and 2 nm La2O3 were deposited by physical vapor deposition (PVD) and followed by post-deposition anneal under oxygen ambient. After 150 nm TaN gate metal deposition and patterning, the n+

source-drain regions are formed by As+

implantation at 25 KeV and 5×1015 cm-2 dose. Then scanned KrF laser annealing (248 nm, <30 ns pulse) was applied to activate the implanted dopant [6],[16]-[19]. The junction characteristics and sheet resistance were measured to characterize the effect of laser annealing. Finally, Al metal contacts were added to source-drain and form the Ge n-MOSFET. The fabricated devices were characterized by C-V and I-V measurements using an HP4284A precision LCR meter and HP4156C semiconductor parameter analyzer, respectively.

三、 結果與討論

Figures 1(a) and 1(b) show the sheet resistance (Rs) and n+/p junction characteristics of As+-implanted Ge after laser annealing. The increasing laser energy density improves Rs, the junction ideality factor (n) and forward current, while still maintaining a low reserve leakage current. The Rs decreases rapidly with increasing laser fluence (energy/area) to 0.16 J/cm2. This value is significantly lower than previous 0.36 J/cm2 value for Si device anneal [16] that is due to the much lower melting temperature of Ge than Si. The lower laser fluence is important to decrease the energy absorbed by TaN gate that can cause unwanted interface reaction and

Vfb roll-off [16]. The Rs as low as 68 　/sq was obtained at 0.2 J/cm2 laser fluence that is 40% better than the 112 　/sq Rs using RTA at 550oC. Small n-factor of 1.3 and very large

~105 forward/reverse current ratio are measured for n+/p junction using laser annealing and also better than the control RTA devices. The higher forward current in the n+/p junction is crucial to reach the higher drive current of Ge n-MOSFET.

Figures 2(a) and 2(b) show the C-V and J-V characteristics of TaN/La2O3/SiO2/Ge devices, where slight Vfb shift and increasing gate current were found by laser annealing.

An EOT of 1.9 nm was obtained from quantum-mechanical C-V calculation with Ge material values [14],[16]. The effect of laser annealing on gate dielectric was further examined by cross-sectional TEM. Still sharp interfacial SiO2 layer was observed by laser annealing that gives the good C-V characteristics. This is due to the low 0.2 J/cm2 laser fluence, although it is high enough to melt and crystallize the ion-implanted Ge.

Besides, 1/3 energy was reflected at top TaN surface from the measured reflectivity [16].

These further lower the energy absorbed by high-　/Ge interface. The higher gate leakage current may be related to TaN/La2O3 inter-diffusion by laser annealing, although more detailed study is needed.

Figures 3(a) and 3(b) show the Id-Vd and Id-Vg characteristics of La2O3/SiO2/Ge n-MOSFETs using laser annealing. Well behaved transistor characteristics were reached, with a good sub-threshold swing of 125 mV/dec. A negative threshold voltage (Vt) of -0.47 V is due to the negative Vfb measured from C-V characteristics in Fig. 2(a).

Although this indicates less Fermi-level pinning, further adjusting the Vt to positive value is needed. Figure 4 further shows the mobility over a wide Eeff range. High peak

mobility of 603 cm2/Vs and 0.75 MV/cm mobility of 304 cm2/Vs are reached for the Ge n-MOSFETs using laser anneal, which is the highest electron mobility for gate-first Ge n-MOSFET.

四、 結論

Using low energy laser anneal on TaN/La2O3/SiO2 Ge n-MOSFETs, small junction n-factor of 1.3, big 10⁵ n⁺

/p junction

forward/reverse current, high 603 cm²/Vs peak mobility and good high-field (0.75 MV/cm) mobility of 304 cm²/Vs were reached simultaneously at small EOT of 1.9 nm.

五、 參考文獻

[1] C. H. Huang, M. Y. Yang, A. Chin, W. J.

Chen, C. X. Zhu, B. J. Cho, M.-F. Li, and D. L. Kwong, “Very low defects and high

performance Ge-On-Insulator p-MOSFETs with Al2O3 gate

dielectrics,” in VLSI Symp. Tech. Dig., 2003, pp. 119-120.

[2] C. Chui, H. Kim, D. Chi, B. B. Triplett, P.

C. McIntyre, and K. C. Saraswat, “A sub-400ºC Ge MOSFET technology with high-k dielectric and metal gate,” in IEDM Tech. Dig., Dec. 2002, pp.

437–440.

[3] W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L.

Kwong, D. Wristers, A. Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD HfO2 gate dielectrics and TaN gate electrode,” in Symp. VLSI Tech. Dig., 2003, pp.

121–122.

[4] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M. F. Li, A.

Chin, J. K. O. Sin, and D. L. Kwong, “A TaN-HfO2-Ge pMOSFETs with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, pp. 631-633, Sept.

2004.

[5] W. P. Bai, N. Lu, and D.-L. Kwong “Si interlayer passivation on Germanium MOS capacitors with high-k dielectric and metal gate,” IEEE Electron Device Lett., vol. 26, no. 6, pp.378-380, June 2005.

[6] Q. Zhang, J. Huang, N. Wu, G. Chen, M.

Hong, L. K. Bera, and C. Zhu,

“Drive-current enhancement in Ge n-channel MOSFET using laser annealing for Source/Drain activation,” IEEE Electron Device Lett., vol. 27, no. 9,pp.

728–730, 2006.

[7] T. Takahashi, T. Nishimura, L. Chen, S.

Sakata, K. Kita, and A. Toriumi, “Proof of

Ge-interfacing concepts for metal/high-k/Ge CMOS - Ge-intimate material selection and interface conscious process flow -,” in IEDM Tech. Dig., 2007, pp. 697-700.

[8] J. H. Park, M. Tada, D. Kuzum, P. Kapur, H. Y. Yu, H-.S. P. Wong, and K. C.

Saraswat, “Low temperature (≤ 380ºC) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration,” in IEDM Tech. Dig., 2008, pp. 389-392.

[9] K. Kita, S. K. Wang, M. Yoshida, C. H.

Lee, K. Nagashio, T. Nishimura, and A.

Toriumi, “Comprehensive study of GeO2 oxidation, GeO desorption and GeO2-metal interaction – understanding of Ge processing kinetics for perfect interface control –,” in IEDM Tech. Dig., 2009, pp. 693-696.

[10] D. Kuzum, T. Krishnamohan, A. J. Pethe, A. K. Okyay, Y. Oshima, Y. Sun, J. P.

McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Ge-interface engineering with Ozone oxidation for low interface-state density,” IEEE Electron

Device Lett., vol. 29, no. 4, pp. 328–330, 2008.

[11] K. Morii, T. Iwasaki, R. Nakane, M.

Takenaka, and S. Takagi, “High performance GeO2/Ge nMOSFETs with Source/Drain junctions formed by gas phase doping,” in IEDM Tech. Dig., 2009, pp. 681-684.

[12] G. Thareja, M. Kobayashi, Y. Oshima, J.

McVittie, P. Griffin and Y. Nishi, “Low Dit optimized interfacial layer using high-density plasma oxidation and nitridation in Germanium high-k gate stack,” in Device Research Conference, pp.87-88, 2008.

[13] D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H. S-. P. Wong, and K. C. Saraswat, “Experimental demonstration of high mobility Ge NMOS,” in IEDM Tech. Dig., 2009, pp.

453-456.

[14] W. B. Chen and Albert Chin, “High performance of Ge n-MOSFETs using SiO2 interfacial layer and TiLaO gate dielectric,” IEEE Electron Device Lett., vol. 31, pp. 80-82, Jan. 2010.

[15] T. Yamamoto, T. Kubo, T. Sukegawa, E.

Takii, Y. Shimamune, N. Tamura, T.

Sakoda, M. Nakamura, H. Ohta, T.

Miyashita, H. Kurata, S. Satoh, M. Kase, and T. Sugii, “Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology,” in IEDM Tech. Dig., 2007, pp. 143-146.

[16] C. C. Liao, A. Chin, N. C. Su, M.-F. Li, and S. J. Wang, “Low Vt gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection,”

in Symp. VLSI Tech. Dig., pp.190-191, 2008.

[17] F. Liu, H. S. Wong, K. W. Ang, M. Zhu,

X. Wang, D. M. Y. Lai, P. C. Lim, and Y.

C. Yeo, “Laser annealing of amorphous Germanium on Silicon – Germanium Source/Drain for strain and performance enhancement in pMOSFETs,” IEEE Electron Device Lett., vol. 29, no. 8, pp.

885–888, 2008.

[18] C. Ortolland, L. -A. Ragnarsson, P. Favia, O. Richard, C. Kerner, T. Chiarella, E.

Rosseel, Y. Okuno, A. Akheyar, J. Tseng, J. –L. Everaert, T. Schram, S. Kubicek, M.

Aoulaiche, M. J. Cho, P. P. Absil, S.

Biesemans, and T. Hoffmann, “Optimized ultra-low thermal budget process flow for advanced high-k/metal gate first CMOS using laser-annealing technology,” in Symp. VLSI Tech. Dig., pp.38-39, 2009.

[19] C. Y. Ong, K. L. Pey, K. K. Ong, D. X.

M. Tan, X. C. Wang, H. Y. Zheng, C. M.

Ng, and L. Chan, “A low-cost method of forming epitaxy SiGe on Si substrate by laser annealing,” Appl. Phys. Lett., vol.94, No.082104, pp.1-3, 2009.

120 140 160 180 200 220 240 0

100 200 300 400 500 600

RTA 550^oC

Sheet resistance

(

Ω/sq

)

Energy (mJ/cm²)

-2.0 -1.5 -1.0 -0.5 0.0

10^-10 10^-8 10^-6 10^-4

10^-2 before LA

after LA

Voltage (V) Current Density ( A/cm2 )

(b)

Fig. 2.(a)

C-V and (b) J-V characteristics of

TaN/La2O3/SiO2/Ge n-MOS capacitors before and laser annealing.

(a)

-2 -1 0 1 2

10^-8 10^-6 10^-4 10^-2 10⁰ 10² 10⁴

Junction Current(A/cm2 )

Voltage (V)

LA 0.24 J/cm² LA 0.2 J/cm² LA 0.16 J/cm² LA 0.12 J/cm² 550^oC RTA

0.0 0.5 1.0 1.5 2.0 2.5

0 2 4 6 8 10 12

W/L= 100/10 μm

Vg-V

t = 0V V_g-V_t = 0.25V Vg-V

t = 0.5V V_g-V_t = 0.75V Vg-V

t = 1V

I d ( mA )

V (V)

V_g-V_t = 1.25V

d

(b) (a)

Fig. 1. (a) Sheet resistance and (b) n+/p junction characteristics of As+-implanted Ge after laser annealing.

-1.0 -0.5 0.0 0.5 1.0

10^-7 10^-6 10^-5 10^-4 10^-3 10^-2

W /L= 100/10 μm

V_d= 1V LA Vd= 0.1V LA

I d (A)

V_g (V)

125 m V/dec

-3 -2 -1 0 1

0.0 0.5 1.0 1.5 2.0

Capacitance (μF/cm2 )

Voltage (V)

before LA after LA

QM C-V Simulation

(b)

Fig. 3. (a) Id-Vd and (b) Id-Vg of gate-first TaN/La2O3/SiO2/Ge n-MOSFET using laser annealing.

(a)

0.0 0.2 0.4 0.6 0.8 200

400 600 800

μeff(cm2 /V-sec)

E_eff (MV/cm)

Fig. 4. Theelectron mobility as a function of effective electric field of TaN/La2O3/SiO2/Ge

n-MOSFETs

using laser annealing.

行政院國家科學委員會補助團隊參與國際學術組織會議報告 98 年 7 月 13 日

報告人姓名 吳建宏 服務機構 中華大學

微電子系 職稱 助理教授

會議正式名稱 中文：2009 年 IEEE 北東討論室在電路與系統之 TAISA 研討會 英文：

2009 IEEE North-East Workshop on Circuits and Systems and TAISA Conference

會 議 時 間

自 98 年 6 月 28 日至

98 年 7 月 1 日

地點（國、州、城市）

法國

土魯斯

報告內容應包括下列各項：

一、 參加會議經過

本次會議共 4 天，所探討的主題，除了工業界十分重視的 Computer and System architecture, RF, digital, analog and mixed-signal circuit design, Data and signal processing, Microsystems, memories, sensors and associated analog processing Mathematical methods and design tools Telecommunications, radio-frequencies and microwaves 等，而歐洲也是全球太陽能電池發展最先進的地方順道了解一下 城市的綠能。此大會之 plenary talks 邀請國際知名學者演講。本會議之水準 相當不錯。

二、 與會心得

在我所參加的 RF circuit 方面，目前於國際半導體藍圖規化中，將於未來 32nm node 之技術中。然而目前技術上尚有許多的困難及挑戰，如何達到最好 的效能，如何降低漏電流，操作更高的頻段。然而在歐洲研發中心-IMEC 的 推動下，相信未來將有長足的進步。

在會場還遇到大陸方面的學者，相當有興趣來台灣做研究或是就業，也有 邀請她來學校當訪問學者。有關 RF 電路的技術，目前最新的消息為國外大廠 紛紛準備上生產線，故國內 IC 公司亦預計明後年能上線，以利國際間的競爭。

我亦在大會中提及，台灣乃是全球代工與電路研發中心，故生產成本將不 斷下降，因此未必歐洲可領先。此觀點亦獲得大家的認可。

三、 考察參觀活動（無是項活動者省略）

無

四、 建議事項

此次參加本會議，驚覺中國大陸所參與的人數遠超過台灣，而其所發表的 論文品質，亦具國際化的水準。國內應多鼓勵同仁參加，以確保領先的地位。

五、 其他

NEWCASTAISA 會議論文一份

A Wideband 0.18Ӵm CMOS LNA with RC-Feedback Topology for UWB Applications

C. H. Wu

¹

, H. L. Kao

²

, Y. C. Chang

²

, C. H. Kao

³

, M. H. Chen

¹

, C. H. Yang

²

, and B. S. Lin

²

1

: Dept. of MicroElectronics Engineering, Chung Hua Univ., Hsinchu, Taiwan

2

: Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan e-mail:snoopy@mail.cgu.edu.tw

3

: Department of Accounting Information, Takming College, Taipei, Taiwan

Abstract - A 0.18 μm CMOS low noise amplifier using RC- feedback topology is proposed with optimized matching, gain, noise, linearity and area for UWB applications. The IC prototype achieved 9.5 dB of average power gain, low 3.4 dB noise figure (NF), -9.2 dB input match, -13.5 dB return loss, -6 dBm of IIP3 and only 0.54 mm² size with 15 mW power consumption. Good agreement between the simulated and measured results is found.

I. INTRODUCTION

The Federal Communications Commission (FCC) has distributed 7500 MHz bandwidth for ultra-wideband (UWB) applications. Ultra-wideband technology using the unlicensed frequency band from 3.1 to 10.6 GHz has become much interest of broadband wireless communication due to its high data rates, low power transmission, robustness for multi-path fading and low power dissipation. Among possible applications, UWB technology may be used for imaging systems, vehicular and ground penetrating radars, and communication systems. For such broadband applications, the low noise amplifier (LNA) is the first stage in the UWB receiver. It must provide good input impedance matching, low power consumption, low noise performance and sufficient gain with good S/N for the following stages, and small size over the entire frequency band [1]-[13]. Recently, the CMOS technology is a candidate for UWB LNA system [7]-[19] when considering the time to market, hardware cost, the degree of difficulty, and high integration with baseband digital circuits – for a good System-on-Chip (SoC) solution. However, these performance requirements for UWB are very challenging using CMOS technology. This is because the CMOS technology can only provide small gain at high frequency, low cut-off frequency (f_T) [20]-[22], significant substrate loss [23]-[24]

and poor inductor Q-factors [22] compared with GaAs technology. Several different circuit approaches, including distributed amplifier (DA), LC ladder, current-reused, shunt feedback, etc., have been proposed to overcome these issues [7]-[19].

The RC-feedback cascode topology is one of the main methods for wideband amplifier design [11]-[16]. The RC- feedback cascode configuration can provide good input matching and improve gain flatness. However, the challenge of this technique is very wide bandwidth along with low noise and high gain. In this work an ultra-wideband CMOS LNA is proposed a cascode amplifier with three stages: new RC-

feedback cascode topology, LC shunt configuration and output current buffer technology, implemented in 0.18 μm CMOS technology. With new RC-feedback cascade connection and LC shunt techniques, this LNA achieved a 9.5 dB average power gain, a 3.4 dB NF, input reflect loss less than -9.2 dB, output return loss less than -13.5 dB and the input IIP3 is -6 dBm from ultra-wide band LNA circuit. These results are suitable for UWB LNA circuit application.

II. CIRCUIT DESIGN

The UWB LNA requires high gain, low noise figure and high linearity over the entire band with low power consumption. The LNA also needs to have a good input mating over the whole band to capture the transmitted RF energy efficiently. Figure 1 shows a schematic of the proposed three stages amplifier. The first stage is the capacitance- resistance feedback cascode topology that provides high gain, wider bandwidth, better stability and well reverse isolation.

The middle stage is an inductor-capacitor parallel configuration (L_B//C_B) to pull up high frequency gain. The output stage is a simple current buffer that gives broadband output impedance of 50 Ω for measurement purposes. This circuit was designed with Agilent’s Design System (ADS), and implemented in TSMC’s 0.18 μm RF CMOS technology.

Fig. 1. Schematic of the ADS-designed UWB CMOS RC-feedback LNA circuit. The dashed circle is L_B//C_B shunt topology.

119

For input matching, we used RC-feedback cascode topology for matching. The cascode configuration can reduce the high frequency roll-off of the input devices due to the Miller effect.

It provides input and output matching independently. We can select Z_f (R_f and C_f components) to achieve good input matching and high gain. The output stage of the RC-feedback LNA circuit is used current buffer (M₃ and M₄ transistors) to tune the whole frequency to achieve 50 Ω. The M3 is the source follower and the M₄ provide the stable current source for M₃. We only fine tune the bias and transistors size to achieve good output matching.

Among several topologies that provide a gain over a wideband, the RC-feedback loop is one of the most popular to use in amplifiers circuit for its wideband input matching and good linearity [11]-[13]. The substrate bias of transistor M₁ is used to raise the gain and reduce the power dissipation.

However, the gain was confined at high frequency due to gate- drain capacitance and gate-source capacitance. For further rise up the gain at higher frequency, an inductor-capacitor parallel configuration (L_B//C_B) was connected to the second stages to extend bandwidth as the dashed circle in Fig. 1. The L_B//C_B is chosen to resonate at 10.6GHz for the bandwidth extension.

The power gain (S₂₁) can increase at high frequency. The wide band and high gain was obtained in our LNA circuit design.

Fig. 2. The schematic of input stage for RC-feedback UWB LNA added noise circuit. The solid line is our work and the dash line is general design for comparison.

The RC-feedback topology in first stage is dominated the noise characteristics for LNA. To analysis the noise performance of the RC-feedback CMOS amplifier, the noise sources are added to the schematic circuit of first stage as shown in Fig. 2, also comparison with general circuit design [12]-[17]. Compare with general circuits, the proposed feedback topology is connected in front of the matching gate inductor (L_g). From the noise circuit, the total noise vi2

of the general design circuit is one item (i_f²R_Lg²) more than that of our circuit due to the noise current i_f does not go through the L_g. The NF_min of new FB circuit and general design are compared using ADS simulated as shown in Fig. 3. The NF can be reduced 0.54 dB at high frequency. Therefore, the noise figure can be reduced using new feedback topology circuit. A high

voltage and low noise UWB LNA can be achieved. The observation of our design is presented in the following section.

2 4 6 8 10 12 14 16

1 2 3 4 5 6 7 8

General circuit for ref.

New feedback connection

NFmin (dB)

Frequency (GHz)

0.54 dB

Fig. 3. Simulated noise figure (NF_min) using new feedback topology and general circuit for comparison.

III. RESULTS ANDDISCUSSION

The CMOS UWB LNA was tested via on-wafer probing. A network analyzer and ATN-NP5B noise-parameter system meter were used to measure the small-signal S-parameters and NF over the frequency range from 1 to 16 GHz. Fabricated in 0.18 μm 1P6M standard CMOS process this prototype chip using power supply of 1.8 V consumes 15 mW including the output buffer stage. The microphotograph of fabricated CMOS UWB LNA with a chip size 0.54 mm² including the probe pads is shown in Figure 3.

Fig. 3. Image of the fabricated RC-Feedback UWB LNA.

Figures 4 and 5 show the two-port measured S-parameters from 1 GHz to 16 GHz. Figure 4 shows the dependence of measured input reflection coefficient (S₁₁) and output return loss (S22) on frequency. The measured S11 was lower than -9.2 dB for input matching across the frequency band of 3.1~10.6 GHz. The measured S22 was less than -13.5 dB for output matching over a 3.1~10.6 GHz range. In Figure 5 the measured forward gains (S21) and reverse isolation (S12) are reported for

120

the UWB LNA circuit. The S₂₁ displays a maximum gain of 11.7 dB at 3.1 GHz and the average S₂₁ value over the 3.1-10.6 GHz frequency band is 9.5 dB. With RC-feedback cascade topology, the bandwidth extends to cover from 3.1 to 10.6 GHz. An excellent S₁₂ of less than -25.7 dB was obtained due to effective cascode configuration. It is noted that the input impedance was optimized for low noise figure while keeping the corresponding return loss at an acceptable level.

0 2 4 6 8 10 12 14 16

-40 -30 -20 -10 0 10

-30 -25 -20 -15 -10 -5 0

S11 (dB)

Frequency (GHz)

Symbol: Measurement data Line: Simulation data

S22 (dB)

Fig. 4. Measured and simulated input return loss (S₁₁) and output loss (S₂₂) of the RC-Feedback UWB LNA.

0 2 4 6 8 10 12 14 16

-30 -20 -10 0 10 20

-60 -50 -40 -30 -20 -10

S21 (dB)

Frequency (GHz)

S12 (dB)

Symbol: Measurement data Line: Simulation data

Fig. 5. Measured and simulated power gain (S₂₁) and reverse isolation (S₁₂) of the RC-Feedback UWB LNA.

To optimize the performance, the transistors have been sized to provide good noise characteristics, while allowing a good input impedance matching over the required bandwidth. The measured NF of the implemented amplifier is shown in Figure 6. The measured NF shows a minimum value of 3.41 dB at 9 GHz. The measured NF range was 3.41~ 4.04 dB over the 3.1~10.6 GHz range. Figure 7 shows the two-tone test for third-order intermodulation distortion of the UWB CMOS LNA circuit. The third order input intercept point (IIP3) is -6 dBm.

0 2 4 6 8 10 12 14 16

0 5 10 15 20 25 30

Symbol: Measurement data Line: Simulation data

NFmin (dB)

Frequency (GHz)

3.41 dB

Fig. 6. Measured and simulated noise figure (NF_min) of the RC- Feedback UWB LNA.

-30 -25 -20 -15 -10 -5

-80 -70 -60 -50 -40 -30 -20 -10 0

Output Power (dBm)

Input Power (dBm)

P1dB P3dB

-6dBm

Fig. 7. Measured IIP3 of the RC-Feedback UWB LNA.

Table 1 summarizes the measured performance of the LNA and compares the other reported circuit performance. Our proposed CMOS LNA can achieve a wide bandwidth, high gain, good linearity, low NF and low power consumption, and compares well with other published reports [15]-[17].

Table 1. Comparison of LNA circuit performance: published and this work.

Ref. [15] [16] [17] This Work BW (GHz) 2.8 ~ 7.2 3.1 ~ 10.6 1.2 ~ 11.9 3.1 ~ 10.6

S11(dB) < -4 <-9.7 < -11 < -9.2 S22(dB) < -7.5 N/A N/A < -13.5 Gain (dB) 16 ~ 19.5 7.4 ~ 9.2 5 ~ 9.7 7.5 ~ 11.7 NFmin(dB) 3.1 ~3.8 4.1 ~ 7 4.2 ~ 5.1 3.4 ~4.04

IIP3 (dBm) -1 7.25 -6.2 -6

PD (mW) 32 23.5 20 15

Area (mm²) 1.63 0.78 0.59 0.54

Topology 0.18μm Feedback

0.18μm Feedback

0.18μm Noise- Canceling

0.18μm Feedback

121

IV Conclusion

A CMOS UWB LNA with new RC-feedback connection has been designed. This UWB LNA exhibited a high 11.7 dB gain, low 3.4 dB NF, input reflect loss less than -9.2 dB, output return loss less than -13.5 dB and the input IIP3 is -6 dBm from 3.1 to 10.6 GHz, while only 15 mW power dissipation.

The fabricated LNA satisfies UWB LNA system requirements.

ACKNOWLEDGEMENT

The authors wish to thank Dr. G. W. Huang at the National Nano-Device Laboratory and the Chip Implemental Center (CIC) of the National Science Council in Taiwan for their help with the RF measurements and circuit tape-out. This work was partially supported by NSC (97-2221-E-182-017) and CGU (UERPD280012) of Taiwan.

REFERENCES

[1] B. Razavi, “RF Microelectronics,” 1^st editor NJ, USA:

Prentice-Hall PTR, 1998.

[2] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,’ 1^st editor New York: Cambridge University Press, 1998.

[3] B. Razavi, “Design of Analog CMOS Integrated Circuits,”

International editor NY: McGraw Hill Co.,2001.

[4] G. Gonzalen, “Microwave Transistor Amplifiers Analysis and Design,” 2^nd editor MJ: Prentice-Hall, Inc., 1997.

[5] Y. Park, C.-H Lee, J. D. Cressler, J. Laskar, and A.

Joseph, “A very low power SiGe LNA for UWB application,” in IEEE MTT-S Int. Microwave Symp. Dig., 2005, pp. 1041-1044.

[6] J. Lee and J. D. Cressler, “A 3-10 GHz SiGe Resistive Feedback Low Noise Amplifier for UWB Applications,”

in IEEE RF IC Symp. Dig., 2005, pp. 545-548.

[7] S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, “A sub- mW 960-MHz Ultra-Wideband CMOS LNA,” in IEEE RF IC Symp. Dig., 2005, pp. 35-38.

[8] M. T. Reiha, J. R. Long, "A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 _m CMOS", IEEE Journal of Solid-State Circuits, 2007, 42, (5), pp. 1023-1033.

[9] Bevilacqua, and A. M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6 GHz Wireless Reveivers,” in IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 2005, pp.

2259-2268.

[10] A. Ismail and A. Abidi, “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” in IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 2004, pp. 2269-2277..

[11] R.-C. Liu, K.-L. Deng, and H. Wang, “A 0.6-22 GHz broadband CMOS distributed amplifier,” in IEEE RFIC Symp. Dig., 2003, pp. 103-106.

[12] C. W. Kim, M.-S. Kang, P. T. Anh, H.-T. Kim and S.-G. Lee,

“An Ultra-Wideband CMOS Low Noise Amplifier for 3-5GHz UWB System,” in IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, 2005, pp. 544-547.

[13] J. Jung, K. Chung, T. Yun, J. Choi, and H. Kim, “Ultra-wideband low noise amplifier using a cascode feedback topology,” in Silicon Monolithic Integrated Circuits in RF Systems Dig., 2006, 202-205.

[14] H. Xie, X. Wang, A. Wang, Z. Wang, C. Zhang and B. Zhao, “A Fully-Integrated Low-Power 3.1-10.6GHz UWB LNA in 0.18Ӵ

m CMOS,ϙ in IEEE Radio Frequency Integrated Circuits Symposium, 2007.

[15] Y. J. E. Chen, and Y. I. Huang, “Development of Integrated Broad-Band CMOS Low-Noise Amplifiers,” in IEEE Transactions on Circuits and Systems, Vol. 54, Issue 10, Oct.

2007. pp. 2120-2127.

[16] R. L. Wang, M. C. Lin, C. C. Lin, and C. F. Yang, “A 1V Full- band Cascoded UWB LNA with Resistive Feedback,” in IEEE Radio-Frequency Integration Technology, Dec. 2007, pp. 188- 190.

[17] C. F. Liao, and S. I. Liu, “A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers,” in IEEE Journal of Solid-State Circuits, Vol. 42, No. 2, February 2007. pp. 329-339.

[18] G. D. Nguyen, K. Cimino, and M. Feng, “A RF CMOS Amplifier with Optimized Gain, Noise, Linearity and Return Losses for UWB Applications,” in IEEE Radio Frequency Integrated Circuits Symposium, 2008.

[19] Q. Li, and Y. P. Zhang, ”A 1.5-V 2–9.6-GHz Inductorless Low- Noise Amplifier in 0.13-μm CMOS,” in IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 10, October 2007. pp. 2015-2023.

[20] C. H. Huang, K. T. Chan, C. Y. Chen, A. Chin, G. W. Huang, C.

Tseng, V. Liang, J. K. Chen, and S. C. Chien, “The minimum noise figure and mechanism as scaling RF MOSFETs from 0.18 to 0.13 μm technology nodes,” in IEEE RFIC Symp., 2003, pp.

373-376.

[21] H. L. Kao, A. Chin, J. M. Lai, C. F. Lee, K. C. Chiang and S. P.

McAlister, “Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout,” in IEEE RF IC Symp. Dig., 2005, pp.157-160.

[22] H. L. Kao, Albert Chin, C. C. Liao, C. C. Chen, S. P. McAlister and C. C. Chi, “Electrical stress effects and device modeling of 0.18 m RF MOSFETs,” in IEEE Trans. Electron Device, vol.

53, 2006, pp. 636-642.

[23] A. Chin, K. T. Chan, H. C. Huang, C. Chen, V. Liang, J. K. Chen, S. C. Chien, S. W. Sun, D. S. Duh, W. J. Lin, C. Zhu, M.-F. Li, S.

P. McAlister, and D. L. Kwong, “RF passive devices on Si with excellent performance close to ideal devices designed by Electro-Magnetic simulation,” in IEDM Tech. Dig., 2003, pp.

375-378.

[24] K. T. Chan, A. Chin, S. P. McAlister, C. Y. Chang, J. Liu, S. C.

Chien, D. S. Duh, and W. J. Lin, “Low RF noise and power loss for ion implanted Si having an improved implantation process,”

IEEE Electron Device Lett., vol. 24, pp. 28-30, Jan. 2003.

122

無研發成果推廣資料

98 年度專題研究計畫研究成果彙整表

計畫主持人：吳建宏 計畫編號：98-2218-E-216-002- 計畫名稱：應用於下世代 CMOS 元件之簡易且新穎式雷射製程技術

量化

成果項目 ^{實際已達成}

數（被接受 或已發表）

預期總達成 數(含實際已

達成數)

本計畫實 際貢獻百

分比

單位

備 註 （ 質 化 說 明：如 數 個 計 畫 共 同 成 果、成 果 列 為 該 期 刊 之 封 面 故 事 ...

等）

期刊論文 2 2 100%

1.Nai-Chao Su, Shui-Jinn Wang, Chin-Chuan

Huang, Yu-Han Chen, Hao-Yuan Huang, Chen-Kuo Chiang,

Chien-Hung Wu, and Albert Chin, ＇The Role of High-κ TiHfO Gate Dielectric in Sputtered ZnO Thin-Film

Transistors, ＇ Jpn. J. Appl.

Phys., 49 (2010) 04DA12

（SCI=1.138）

2.C. H. Wu, C. K.

Chiang, Y. H.

Chen,N. C. Su, S.

J. Wang, C. C.

Huang, K. L. Kao, M. S. Yeh and I.

J.

Hsieh, ＇Defect Density

Extraction of high-κ

Dielectric Gate

Stack by

Combining Charge Pumping and Low Frequency

Measurement,＇

Chung Hua

Journal of Science and Engineering, Vol. 7, No. 3, pp.79-83, 2009.

研究報告/技術報告 0 0 100%

研討會論文 0 0 100%

論文著作 篇

專書 0 0 100%

申請中件數 0 0 100%

國內

專利 已獲得件數 0 0 100% 件

件數 0 0 100% 件 技術移轉

權利金 0 0 100% 千元

碩士生 0 0 100%

博士生 0 0 100%

博士後研究員 0 0 100%

參與計畫人力

（本國籍）

專任助理 0 0 0%

人次 無

期刊論文 0 0 100%

研究報告/技術報告 0 0 100%

研討會論文 0 0 100%

論文著作 篇

專書 0 0 100% 章/本

申請中件數 0 0 100%

專利 已獲得件數 0 0 100% 件

件數 0 0 100% 件

技術移轉

權利金 0 0 100% 千元

碩士生 0 0 100%

博士生 0 0 100%

博士後研究員 0 0 100%

國外

參與計畫人力

（外國籍）

專任助理 0 0 100%

人次

其他成果

(

無法以量化表達之成

果如辦理學術活動、獲 得獎項、重要國際合 作、研究成果國際影響 力及其他協助產業技 術發展之具體效益事 項等，請以文字敘述填 列。)

成果項目 量化 名稱或內容性質簡述

測驗工具(含質性與量性) 0

課程/模組 0

電腦及網路系統或工具 0

教材 0

舉辦之活動/競賽 0

研討會/工作坊 0

電子報、網站 0

科 教 處 計 畫 加 填 項

目 計畫成果推廣之參與（閱聽）人數

國科會補助專題研究計畫成果報告自評表

請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用價 值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性） 、是否適 合在學術期刊發表或申請專利、主要發現或其他有關價值等，作一綜合評估。

1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估

■達成目標

□未達成目標（請說明，以 100 字為限）

□實驗失敗

□因故實驗中斷

□其他原因 說明：

2. 研究成果在學術期刊發表或申請專利等情形：

論文：■已發表 □未發表之文稿 □撰寫中 □無 專利：□已獲得 □申請中 ■無

技轉：□已技轉 □洽談中 ■無 其他：（以 100 字為限）

3. 請依學術成就、技術創新、社會影響等方面，評估研究成果之學術或應用價 值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）（以 500 字為限）

對於發展下世代 CMOS 元件之簡易且新穎式雷射技術而言，將是半導界的主流。本研究團 隊於研發出&amp；#63754；屬閘極搭配氧化鑭高介電係&amp；#63849；介電層的 n 型&amp；

#63754；氧半場效電晶體。接著我們更進一步利用高介電常數氧化鑭來製作鍺金氧半場效 電晶體，二氧化矽做為介面層，氮化鉭做為金屬閘極。利用雷射退火的方式去達到改善元 件的特性，得到相當優異的元件特性，相信未來業界也一定會陸續採用這樣的技術和製 程。這樣的計畫也陸續發表了數篇論文和研討會論文。