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行政院國家科學委員會專題研究計畫 成果報告

使用多段曲線擬合方法實現 CMOS 電流模式函數 研究成果報告(精簡版)

計 畫 類 別 : 個別型

計 畫 編 號 : NSC 100-2221-E-216-033-

執 行 期 間 : 100 年 08 月 01 日至 101 年 07 月 31 日 執 行 單 位 : 中華大學電子工程學系

計 畫 主 持 人 : 林國珍

計畫參與人員: 博士班研究生-兼任助理人員:鄭智仁

報 告 附 件 : 出席國際會議研究心得報告及發表論文

公 開 資 訊 : 本計畫可公開查詢

中 華 民 國 101 年 10 月 27 日

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中 文 摘 要 : 由於愈來愈多的類比電路採用 CMOS 電流模式來發展,輸入動 態範圍一直都是電流模式優於電壓模式的項目。然而為了解 決更多的問題,輸入動態範圍也被要求提高,因此如何設計 電路讓輸入動態範圍提昇將是一個重要的議題。

本研究計畫將一函數在所要求的輸入動態範圍內採用多 段曲線擬合的方法來提升精確度,也就是説在一個固定誤差 範圍內,增加輸入動態範圍。我們將預先設定範圍之函數依 照曲率的不同作分段,使用 Divide-and-Conquer (分治法) 以二元樹架構來做分割。分割後的每一分段是以 Taylor 展開 式的二次多項式來擬合,兼顧電路精簡化及擬合精準度。

控制如何分段的電路是參考差動放大器為基礎的電壓比 較器,並經修改後成為電流模式比較器,以作為分割線段的 依據。每一分段的二次多項式均含有控制界面,受電流模式 比較器的控制。二次多項式電路的構成是採用 PMOS 與 NMOS 的背對背電路架構,再根據不同的 ax2 + bx + c 二次多項式 係數,改變 Mirror 比例及定電流值所形成,最後將各段之電 流輸出合起來產生所要函數的電流輸出。

在本研究計畫已將電路下線製作成晶片,Post-

Simulation 所得結果與模擬結果及理想函數作比較來驗證成 果。

中文關鍵詞: CMOS 電流模式電路、輸入動態範圍、電流模式比較器、差動 放大器、分段函數、二次多項式電路、曲線擬合。

英 文 摘 要 : A significant increase in the use of CMOS current- mode technology for the realization of analog circuits has been observed. In most applications, high accuracy result and large input dynamic range are required. Therefore, how to design a large input dynamic-range circuit becomes an important issue.

In this project, we will use a multi-segments method to fit a function with a large input dynamic range and high accuracy result. We use a divide-and- conquer algorithm, according to the curvature of a function, to construct a binary tree. In each divided segment, we approximate the segmented function using a second-order polynomial which is suited for simple circuit and good for accurate result.

We implement a current-mode comparator, using a modified voltage-mode comparator based on a

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differential amplifier, to divide a function. The segmented function is constructed by a pair of PMOS and NMOS. We can properly use the scale of current- mirror and add a current source to make a second- order polynomial form of ax2 + bx + c.

In this project, we design and implement chips to verify a large input dynamic range and a high

accuracy result. We also compare measurement results with corresponding simulations.

英文關鍵詞: CMOS current-mode circuit, input dynamic range, current-mode comparator, differential amplifier, segmented function, quadratic circuit, curve fitting.

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行政院國家科學委員會補助專題研究計畫 行政院國家科學委員會補助專題研究計畫 行政院國家科學委員會補助專題研究計畫

行政院國家科學委員會補助專題研究計畫 □ □ □ □期中進度報告 期中進度報告 期中進度報告 期中進度報告

▓期末報告 期末報告 期末報告 期末報告

(使用多段曲線擬合方法實現 CMOS 電流模式函數)

計畫類別:▓個別型計畫 □整合型計畫

計畫編號:NSC 100 - 2221 - E - 216 - 033 -

執行期間: 100 年 08 月 01 日至 101 年 07 月 31 日 執行機構及系所:中華大學電子工程學系

計畫主持人:林國珍 共同主持人:

計畫參與人員:鄭智仁

本計畫除繳交成果報告外,另須繳交以下出國報告:

□赴國外移地研究心得報告

□赴大陸地區移地研究心得報告

▓出席國際學術會議心得報告及發表之論文

□國際合作研究計畫國外研究報告

處理方式:除列管計畫及下列情形者外,得立即公開查詢

□涉及專利或其他智慧財產權,□一年□二年後可公開查詢

中 華 民 國 101 年 10 月 27 日

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中文摘要

由於愈來愈多的類比電路採用 CMOS 電流模式來發展,輸入動態範圍一直都是電流模式優於 電壓模式的項目。然而為了解決更多的問題,輸入動態範圍也被要求提高,因此如何設計電路讓 輸入動態範圍提昇將是一個重要的議題。

本研究計畫將一函數在所要求的輸入動態範圍內採用多段曲線擬合的方法來提升精確度,也 就是説在一個固定誤差範圍內,增加輸入動態範圍。我們將預先設定範圍之函數依照曲率的不同 作分段,使用 Divide-and-Conquer (分治法)以二元樹架構來做分割。分割後的每一分段是以 Taylor 展開式的二次多項式來擬合,兼顧電路精簡化及擬合精準度。

控制如何分段的電路是參考差動放大器為基礎的電壓比較器,並經修改後成為電流模式比較 器,以作為分割線段的依據。每一分段的二次多項式均含有控制界面,受電流模式比較器的控制。

二次多項式電路的構成是採用 PMOS 與 NMOS 的背對背電路架構,再根據不同的 ax2 + bx + c 二次 多項式係數,改變 Mirror 比例及定電流值所形成,最後將各段之電流輸出合起來產生所要函數的 電流輸出。

在本研究計畫已將電路下線製作成晶片,Post-Simulation 所得結果與模擬結果及理想函數作比 較來驗證成果。

關鍵詞:CMOS 電流模式電路、輸入動態範圍、電流模式比較器、差動放大器、分段函數、二次

多項式電路、曲線擬合。

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Abstract

A significant increase in the use of CMOS current-mode technology for the realization of analog circuits has been observed. In most applications, high accuracy result and large input dynamic range are required. Therefore, how to design a large input dynamic-range circuit becomes an important issue.

In this project, we will use a multi-segments method to fit a function with a large input dynamic range and high accuracy result. We use a divide-and-conquer algorithm, according to the curvature of a function, to construct a binary tree. In each divided segment, we approximate the segmented function using a second-order polynomial which is suited for simple circuit and good for accurate result.

We implement a current-mode comparator, using a modified voltage-mode comparator based on a differential amplifier, to divide a function. The segmented function is constructed by a pair of PMOS and NMOS. We can properly use the scale of current-mirror and add a current source to make a second-order polynomial form of ax2 + bx + c.

In this project, we design and implement chips to verify a large input dynamic range and a high accuracy result. We also compare measurement results with corresponding simulations.

Keywords: CMOS current-mode circuit, input dynamic range, current-mode comparator, differential amplifier, segmented function, quadratic circuit, curve fitting.

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目錄 目錄 目錄 目錄

中文摘要 ………...I 英文摘要 ………..…II

一、前言 ………1

二、研究目的 ………..1

三、文獻探討 ………..1

四、研究方法 ……….….2

五、結果與討論 ………....16

六、參考文獻 ………..…..17

七、計畫成果自評 ……….20

八、可供推廣之研發成果資料表 ………21

九、附錄 ………....21

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一、前言

輸入動態範圍一直都是 CMOS 電流模式優於 CMOS 電壓模式的項目。然而為了解決更多的問 題,輸入動態範圍也一再被提升,因此如何設計電路讓輸入動態範圍擴大是一個重要的議題。

本研究計畫採用分割的方法將一函數分成多段二次多項式函數,控制分割的方法及電路為主 要的研究對象。我們將控制電路分成兩種方法來實現,一為 CMOS 差動比較電路,一為 CMOS 電 流比較電路。最後整體電路經由 HSPICE 模擬及晶片製作所量測結果做比較以保證電路之可行性。

二、研究目的

本研究計畫希望使用分段的方式將一複雜的函數分成數段,再將每段使用二次多項式 Taylor 展開式來趨近,以達到輸入電流之動態範圍大幅提升。例如要發展一個 exp(x)的電路功能,可以將 exp(x)利用 Taylor 展開式轉換為 n 段的二次多項式來趨近,其中第 k 段可以表示成 akx2 + bkx + ck。 因此,本研究最後可以獲得控制分段的電路及 n 段二次多項式電路來實現一複雜函數的功能,可 以大幅改進類比電路之應用範疇及執行效率,例如應用於可變增益放大器(Variable Gain Amplifier) 電路發展,可以不需串聯多級電路即可提升線性度;而應用於 LCD 控制電路、FUZZY 控制電路 及複雜算術計算電路的發展,均可降低功率消耗及提升動態輸入電流範圍。

三、文獻探討

近二十年來,電流模式類比電路已經漸漸地在類比功能的應用中出現。透過電壓模式信號處 理與電流模式的信號處理的結合,可以很明顯地獲得系統性能的提升優勢[1]。現今電流模式的類 比信號處理愈來愈成熟,有多種應用系統使用此技術如[1-11]。由於很多潛在的優點 [7, 8, 9], 電流 模式電路獲得相當多的注意。與電壓模式電路相比較,電流模式電路擁有以下的潛在的優點︰

1. 更高的頻寬能力︰雙極電晶體(BJT)和金氧半場效電晶體(MOS)兩個都是電流輸出裝置,以 電晶體做為促成均一增益頻寬(fT)之電流放大器。電流模式的關鍵性特徵是在更高的頻率下,雜散 電容可以有效地當成增益的元件[10],而電壓模式電路則被限制。

2. 高操作速度︰積體電路技術的尺寸縮小導致寄生電容成為電路快慢的因素。因此電流模式 電路能在電路內部的節點取得低阻抗和低電壓振幅達到高操作速度。

3. 算術計算的低電路複雜性︰在電流模式下,加法和減法的計算可以直接透過在一個結點的 連接來執行。再使用電流模式的電流鏡架構可以輕易地處理信號的反向、總和及比例大小等基本 功能,而這些基本功能電壓模式就難以處理。很明顯地,電流模式擁有低的電路複雜性和低的功 率消耗。

4. 更大的操作動態範圍︰當 IC 製程技術愈來愈縮小,為了保證元件可靠性,電源的電壓必須 降低。降低的電源電壓導致降低了電壓模式的動態範圍。解決這個問題顯然可從電壓模式改變為 電流模式,可以避免電源電壓的限制[11]。

以 CMOS 為主流之 IC 設計及製程而言,MOS 在飽和狀態下,電流與電壓平方的關係成為電 流模式的基礎。相關的平方電路及平方根電路已經漸漸地出現在類比功能的應用中[6, 12, 13, 15, 17-21]。其中,最著名的是 MOS Translinear Principle 或稱為 Quadratic-translinear Principle 的提出

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及應用[15, 17, 19, 21],但是這些應用還是受限於平方及平方根的特性。

過去我們利用一個精簡的平方電路架構[22]作為基礎,使用二次多項式 Taylor 展開式來趨近較 複雜的函數電路,以精簡的電路實現特殊及較為複雜的功能應用[1-5]。由於 Taylor 展開式的 truncation error 及平方電路的限制,輸入電流之動態範圍在誤差的考量下無法有效及大幅的提升。

四、研究方法

對於一非線性及二次多項式函數或一複雜函數 (例如 EXP(x)),我們可以將一較大的輸入動態 範圍區間分成 n 段,每一段均使用二次多項式來表示。以下就控制分段電路之設計、二次多項式 電路設計、整合電路設計、模擬電路結果及晶片製作分別作說明。

1、控制分段電路:

首先介紹以差動放大器作為基礎的傳統電壓模式比較器如圖一[24],作為電流模式控制分段電 路設計之參考。

圖一:傳統電壓模式比較器

當 Vin > Vt,可得 Vout 為邏輯 1,否則 Vout 為邏輯 0。由於採用電流模式,我們將傳統電壓模 式比較器修改成如圖二。

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圖二:電流模式比較器

我們可以獲得當 Iin > It,可得 Vout1 為邏輯 1,Vout2 為邏輯 0,否則 Vout1 為邏輯 0,Vout2 為邏 輯 1。其中 Vout1 及 Vout2 為互補的輸出。因此,我們可以將以此電流模式比較器作為控制分段電 路的基礎。

其次,我們要介紹另一控制分段電路如圖三所示。

Mdd I

d

Md I

x

I

1

I

2

S : 1

圖三:電流模式比較器

當 Ix > Id,Md 導通,I2 >0,最後 I2 = SI1

2、二次多項式電路

電路原理分析如下。由於 MOS 工作在飽和區時會有平方的特性,因此在設計上可使用[6]如 圖四所示之電路架構,來實現電流模式的平方原理。假設圖四中 M1、M2 皆工作在飽和區且 K 值完全匹配,即 K=Kn=Kp

L C W 2

Kp

=

1

µ

p ox

L C W 2

Kn

=

1

µ

n ox ,當輸入電流 Ix之流向為

流出時,Ix會切分 I1與 I2兩電流,I1與 I2可分別表示為:

2 2

1 GS tp DD tp

I = K (V − | V |) = K (V − V

C

− | V |)

(19)

2 2

2 GS tn tn

I

= K

(V

| V |)

= K

(VC

| V |) (20) I2=I1-IX,將(19)與(20)代入得:

2 2

tn DD tp X

(V

C

V ) (V V

C

| V |) I

K − = K − − −

(21)

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圖四:核心電路(平方電路)

整理(21),以 Ix為表示式:

2 2

X DD tp tn

I = K [V − (V

C

+ | V |)] − K (V

C

− V )

DD tn

2 2 2 2

DD tp tp tn

[V 2V (V | V |) (V |V |) ] (V 2V V V )

C C C C

K K

= − + + + − − +

DD tp tn

2 2 2

DD DD tp tp tn

(V V 2V VC 2V | V | 2V | V | 2V VC C V )

= K + − − + + −

2 2

DD tp tn DD tp tn

[(V -|V |) -V ]-2 (V -|V | V )V

C

K K

= −

(22) 在(22)式中,VC可表示成:

DD tp tn DD tp tn X

DD tp tn DD tp tn

(V |V | V )(V |V |+V ) I

V +

2(V |V | V ) 2 (V |V | V )

C

K

− − −

= − − − −

DD tp tn X

DD tp tn

(V |V |+V ) I

2 +2 (V

K

|V | V )

= −

− −

(23) 將(23)代入(19)與(20)式,I1及 I2可表示成:

DD Tp Tn X 2

1

DD Tp Tn

V V V I

I K[ ]

2 2K(V V V )

− −

= +

− −

(24)

DD Tp Tn X 2

2

DD Tp Tn

V V V I

I K[ ]

2 2K(V V V )

− −

= −

− −

(25)

在(24)式與(25)式中,我們假設

2 V V V

V0 DD

Tp

Tn

=

即可將方程式改寫成:

2 X 2

1 0 2

0

I KV (1 I )

= +

4KV

(26)

(12)

2 X 2

2 0 2

0

I KV (1 I )

= −

4KV

(27) 圖五為二次多項式電路雛型,其原理是使用圖四的平方電路搭配電流鏡電流比值的關 係,使用電流方式來達成 Iout=I0(ax2+bx+c)形式的二次多項式。

圖五:二次多項式電路雛型

在此二次多項式電路中 M1、M2 兩電晶體作用在於產生 I1與 I2兩電流作為主要 Miror 用電流,而 M3 與 M4 兩電晶體功能在於調整修正我們所想要的平方項 I0 (ax2)的部分,一次 項 I0bx 的部分由 M5 與 M6 來達成,而定電流 IV1與 IV2部分則是常數項 I0c 部分的修正,利 用此六顆 MOS 與定電流源可以達到我們所期望的二次多項式電路。

假設我們所有電晶體皆工作在飽和區且輸出電流為 Iout=I0(ax2+bx+c),當輸入 Ix電流時 我們會從 M1、M2 兩電晶體得到 I1與 I2兩電流,其電流可分別表示為:

2 2

1 0 2

0

I KV (1 I )

4KV

= +

x

2 2

2 0 2

0

I KV (1 I )

4KV

= −

x

假設

0 x

mI

x = I

可得 Ix=mxI0 我們可將 I1、I2改寫成:

2 0 2

1 0 2

0

I KV (1 I )

4KV

= + m x

(28)

2 0 2

2 0 2

0

I KV (1 I )

4KV

= − m x

(29) 其中 m 值為一待定的常數,並且假設

I

0

= KV

02所以我們可從(28)、(29)式推得:

(13)

2 2 0

1 0 0

0

I I (1 I ) I (1 )

4I 4

m x mx

= + = +

(30)

2 2

0

2 0 0

0

I I (1 I ) I (1 )

4I 4

m x mx

= − = −

(31) 再將 I3從(30)式做 s 倍的電流鏡,I4也從(31)式做 s 倍的電流鏡,我們利用此兩電流對方程式 中的平方項做調整,但值得注意的是當我們平方項係數 a 值是正值時,我們會選用 I3項電流 做為調整用,若負值則用 I4項電流做為調整用,所以首先將 I3從(30)式做 s 倍的電流鏡,I4

也從(31)式做 s 倍的電流鏡可得:

2

3 0

I I (1 )

4

s mx

= +

(32)

2

4 0

I I (1 )

4

s mx

= −

(33) 我們也可以利用 I5從(30)式做 r 倍的電流鏡,I6也從(31)式做 r 倍的電流鏡來對方程式中的一 次項做調整,可得:

2

5 0

I I (1 )

4

r mx

= +

(34)

2

6 0

I I (1 )

4

r mx

= −

(35) 在常數項的 IV部分,我們是將電流乘上一個 q 值的倍率來做修正,若常數項(c)

為正值,則使用電流源(IV1),若常數項為負值得時候,則使用電流源(IV2),並假設 IV1=IV2=qI0 (36) 假設多項式 ax2+bx+c 中的係數 a、b、c 值皆為正值,從(32)、(34)、(35)、

(36 及圖五可得:

Iout=I5+Isq-I6+IV1

2 2 2

0 0 0 0

I (1 ) I (1 ) I (1 ) I

4 4 4

mx mx mx

r s r q

= + + + − − +

整理後可得:

2 2

I [(0 ) ( ) ( )]

16 2

sm sm

x rm x s q

= + + + +

(37) 而 Iout=I0(ax2+bx+c) (38) 比較(37)式與(38)式可得:

2

2 2

[a +b +c] [( ) ( ) ( )]

16 2

sm sm

x x = x + + rm x + + s q

2

a 16

= sm

(39)

(14)

b 2

sm rm

= +

(40) c

= + s q

(41) 將(39)式、(40)式、(41)式,整理成 s、r、q 各電流鏡比值表示形式:

2

s 16a

= m

(42) r b

2

s

= − m

(43) q

= −

c s (44) 我們可依據(42)(43)(44)三式來調整電晶體內 W/L 比,以求得電路中我們所需的 W/L 值。在此設計中,我們又能依據使用者所訂定的 a、b、c 係數,來對電路調整比值以達到使 用者所需要的二次多項式組合。

3、整合電路:

圖五之二次多項式電路雛型為二次多項式電路之一般型,真正使用的電路,並非 M3、M4、

M5、M6、Iv1及 Iv2都使用到,如圖六、七所示,圖六是當 ax2+bx+c 中的係數 a、b、c 值皆為正 值,所使用的電路;而圖七則是 a、b、c 值為”負正負”時,所使用的電路。

圖六:二次多項式電路(a,b,c 係數為正正正型式)

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圖七:二次多項式電路(a,b,c 係數為負正負型式)

我們將圖五之二次多項式電路雛型加上控制界面如圖八,圖中 Vout受前述之控制分段電路 Vout

控制。假設要實現一 f(x)函數,我們將輸入範圍分為兩段,分別使用 Taylor 的二次多項式展開為 a1x2 + b1x + c1及 a2x2 + b2x + c2。實現步驟以圖九來表示,圖中(A)方塊為圖二之電路;(B)(C)方塊 為圖八之電路,電流 It為分段處的電流。

圖八:具有控制界面之二次多項式電路

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圖九:二分段之函數產生方塊圖 4、模擬電路結果:

Sigmoid 函 數 在 神 經 網 路 中 被 廣 泛 使 用 , 如 Artificial neural networks(ANN) 與 Fuzzy networks(FNN)。在人工神經網路(ANN)的硬體實現上,非線性函數的計算對於影響系統使用的面積 或延遲時間為重要因素。本模擬電路是利用多段方式實現 Sigmoid 函數電路為例來提升 Sigmoid 函 數之準確度、速度與寬輸入電流為目的,應用 CMOS 電流模式之方法,並創新以類比電路方式做分 段的概念將 Sigmoid 函數實現。以往用 Gradient-descendent type 演算法計算 Sigmoid 函數過於複雜,

這裡以較簡單的泰勒二階展開式取代,由於泰勒二階展開式相對較不準確近而搭配分段的概念,將 Sigmoid 函數分成四段實現,而完成高準確度、速度快與寬輸入電流之 CMOS 電流模式 Sigmoid 函 數電路。

Sigmoid 電路架構由四個主要方塊組成如下(圖十),分別為 current source、second-order circuit、

current control switch、multi segment。current source 設計目的為提供多個 second-order circuit 輸入電 流,second-order circuit 為實現各分段之電路,current control switch 是作為控制個分段電路導通之 用,multi segment 合成個分段電路。Multi-segment 架構目的在於利用簡單二次多項式電路實現複雜 不同的函數,提高準確度並節省面積。

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圖十:Sigmoid 電路架構之四個主要方塊圖

current source(圖十一)由多組電流鏡組成,在單一輸入電流下轉換提供下級所許之多個輸入 電流。

圖十一:多組電流鏡電路圖

second-order circuit(圖十二)由簡易二次多項式電路將實現之函數分成多段製作,利用分段電路 提升整體函數之準確度。

圖十二:二次多項式電路圖

current control switch(圖十三)在一個較大輸入電流下,以定電流源控制所需分段之電流端點 進行切割,並以 inverter 特性做 I-V 轉利用換搭配不同電壓做切換控制。

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圖十三:定電流源控制分段電路圖

multi segment(圖十四)將電流控制電路轉換出分段電壓,經由 NMOS 做整體電路合成,最 後實現所需之函數。

圖十四:NMOS 電路合成圖

圖十五為實現 Sigmoid 函數之整體電路圖。

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圖十五:Sigmoid 函數電路圖

5、晶片製作:

晶片製作規格列表如下:

電路名稱:利用多段趨近法設計高準確度 CMOS 電流模式 Sigmoid 電路

Technology:TSMC 0.18 um CMOS Mixed Signal RF General Purpose Standard Process FSG Al 1P6M 1.8&3.3V

Package:18 S/B DIP

Transistors/MOS Count:82 MOS Chip Size : 0.32

×

0.32 um2 Power Dissipation:4.27 mW

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此電路模擬之輸入電流 Iin=-400µA~400µA,VDD=1.8V。圖十六為 pre-simulation 與 post-simulation 輸出電流比較圖與絕對誤差圖,對於電路變異上,應用蒙地卡羅分析,亂數模擬 30 次中,百分之 八十相對誤差都在 3%以內。

圖十六: pre-simulation 與 post-simulation 及蒙地卡羅分析圖

圖十七為 TT、FF、FS、SF、SS 各種不同狀態下的模擬圖。

圖十七:TT、FF、FS、SF、SS 模擬圖

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電壓變動對此電路影響,應用 PSRR 做為模擬(圖十八),此電路 PSRR 為 71.4。

圖十八:PSRR 模擬圖

圖十九為 pre-simulation 與 post-simulation 電路頻寬模擬圖。

圖十九:電路頻寬模擬圖

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打線圖如下:

測試規格如下列表:

Parameter Spec. Pre-simulation Post- simulation

Power Supply(V) 1.8 1.8 1.8

Input range(µA) ±400 ±400 ±400

Input Voltage(V) 0.38 ~ 0.9 0.38 ~ 0.9 0.38 ~ 0.9 Output Voltage(V) <0.85 0.7 ~ 0.83 0.7 ~ 0.83

Power Dissipation(mW) <4.3 4.272 4.284

Oscillator Frequency(MHz) <308 308 297

Chip size (mm2) 0.33x0.33 0.32 x 0.32

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文獻比較表如下:

This work Abu.,M.T.

2006[25]

Chun Lu 2002 [26]

Genov, R.

2004[27]

Tech. CMOS 0.18µm 0.18µm 0.5µm 0.5µm

Vdd(V) 1.8 1.8 3.3 1.5

Power

Consumption(mW)

4.283 x 10 82

Input range(µA) ±400 -25~0 x x

Input range(V) 0.38 ~ 0.9 x x 1.8~3.2

Bandwidth(MHz) 308 x x 128

Chip size (mm2) 0.32x0.32 x 1.5 x 0.7 0.7 x 2

本電路應用 TSMC 0.18μm 製程,Power 消耗相較於[26-27]低。在 Input range 以 CMOS 電流模式範 圍擴展之多段法,使輸入電流為±400μA 遠大於[25]文獻。頻寬上更可達到 308MHz,大於[27]文獻。

Chip size 為 0.32 x 0.32 小於[26-27]文獻。

在測試晶片的階段,由於電源供應器無法提供輸入電流±400µA,因而利用輸入輸出兩個節點做 I-V 轉換,其電流範圍的電壓值在 0.38 V~ 0.9V 間,我們量測上主要使用電壓方式去量測結果。所 使用設備有電源供應器與數位式示波器,其中電源供應器提供.38 V~ 0.9 V 的輸入電壓,而數位式示 波器用來量測輸出值,若輸出端電壓量測結果為 0.7 V~ 0.83V,即可推出輸出電流是否正確。

五、結果與討論

本研究計畫之 CMOS 電流模式多分段控制二次多項式電路已發展完成,在 ICEOE 2012 國際會 議中發表兩篇 EI 論文[28][29]。在[28]中,利用電流比較器的方式做分段控制。在[29]中,則是利用 差動放大器的方式做分段控制。另外,二次多項式電路的應用也被 IEICE 期刊接受,預計於 2012 的 11 月刊登[30] 。本研究計畫之實作晶片預計於 2012 的 11 月產出。我們可以從 Post-Simulation 中看出當溫度及 VDD 固定在要求的範圍時,可以保證在 3%的相對誤差範圍內,達到高輸入動態範 圍的要求,輸入電流從-400 µA 到 400 µA,克服了一般非分段的方法之範圍限制。

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六、

參考文獻

[1] Kuo-Jen Lin, “Two-Quadrant CMOS Plug-in Divider,” IEICE Trans. Fundamentals., Vol.E91-A, No. 9, pp. 2682-2684, 2008.

[2] Kuo-Jen Lin, “CMOS Current-Mode Companding Divider,” IEICE Trans. Electron., Vol.E92-C, No. 3, pp. 380-382, 2009.

[3] Kuo-Jen Lin, “Two-Quadrant Compact CMOS Current Divider,” IEICE Trans. Fundamentals., Vol.E92-A, No. 7, pp.1713-1715, 2009.

[4] Kuo-Jen Lin and Chih-Jen Cheng, “CMOS Nth-Switchable-Root Circuit,” IEICE Trans. Electron., Vol.E93-C, No. 1, pp. 145-147, 2010.

[5] Kuo-Jen Lin and Chih-Jen Cheng, “CMOS Current-Mode Geometric-Mean Circuit with N Inputs,” IEEE International Symposium on Signal, Circuits & Systems, Iasi, Romania, pp. 1-4, Jul.

9-10, 2009.

[6] A. Ravindran, K. Ramarao, E. Vidal, and M. Ismail, “Compact low voltage four quadrant CMOS current multiplier," Electron. Lett., vol.37, no.24, pp.1428-1429, 2001.

[7] C. Toumazou, F.J. Lidgey, and D.G. Haigh, Analogue IC Design: the current mode approach, Peter Peregrinus, London, 1990.

[8] B. Wilson, “Recent developments in current conveyors and current-mode circuits,” IEE Proc. G, 137, pp. 63-77, 1990.

[9] A.F. Arbel and L. Goldminz, “Output stage of current-mode feedback amplifiers, theory and applications,” Analog Integrated Circuits and Signal Processing, 2, pp.243-255, 1992.

[10] A.F. Arbel, J.E. Bowers, and J. Lauch, “Low-noise high-speed optical receiver for fiber optic systems,” IEEE J. Solid-State Circuits, 19, pp. 155-157, 1984.

[11] T. Kaulberg, “A CMOS current-mode operational amplifier,” IEEE J. Solid-State Circuits, 28, pp.

849-852, 1993.

[12] H. Song, C. Kim, “A MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers,” IEEE J. Solid-State Circuits, SC-25, pp. 841-894, 1990.

[13] Z. Wang, “A MOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance,” IEEE J. Solid-State Circuits, SC-26, pp. 1293-1301, 1991.

[14] T.S. Lande, J.A. Nesheim, Y. Berg, “Auto correlation in micropower analog CMOS,” Analog Integr. Circuits Signal Process, 1, 1995, pp. 61-68, 1995.

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[15] R.J. Wiegerink, “Analysis and synthesis of MOS translinear circuits,” Kluwer, Boston, 1993.

[16] C.Y. Huang, C.Y. Chen, B.D. Liu, “Current-Mode Fuzzy Linguistic Hedge Circuits,” Analog Integr. Circuits Signal Process, 19(3), pp. 255-278, 1999.

[17] C.A. De La Cruz-Blas, A. Lopez-Martin, A. Carlosena, “1.5-V MOS Translinear Loops with Improved Dynamic Range and Their Applications to Current-Mode Signal Processing,” IEEE Trans.

Circuit Syst.-II, 50(12), pp. 918-927, 2003.

[18] J.K. Seon, “Design and application of precise analog computational circuits,” Analog Integr.

Circuits Signal Process, 54, pp. 55-66, 2008.

[19] S. Menekay, R.C. Tarcan, H. Kuntman, “Noval high-precision current-mode circuits based on the MOS-translinear principle,” AEU Int. J. Electron. Commun., 63, pp. 992-997, 2009.

[20] T. Rungkhum, A. Julsereewong, V. Riewruja, P. Julsereewong, “A CMOS-based Square-Rooting Circuit,” International Conference on Control, Automation and Systems, pp. 161-164, 2007.

[21] W. Petchakit, A. Lorsawatsiri, W. Kiranon, C. Wongtaychathum, P. Wardkein, “Current-mode squaring, square-rooting and vector summation circuits,” AEU Int. J. Electron. Commun., 64, pp.

443-449, 2010.

[22] M. mottaghi-kashtiban, A. Khoei, K. Hadidi, “A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions,” IEICE TRANS.

Electron., E90-C(6), pp. 1258-1266 2007.

[23] A. Motamed, C. Hwang, M. Ismail, “CMOS exponential current-to-voltage converter,” Electron.

Lett., 33(12), pp. 998-1000, 1997.

[24] N. Onizawa and T. Hanyu, “Robust multiple-valued current-mode circuit components based on adaptive reference-voltage control,” 39th International Symposium on Multiple-Valued Logic, pp.

36-41, 2009.

[25] M. T. Abuelma'ati and A. Shwehneh, “A Reconfigurable Satlin/Sigmoid/Gauusian/Triangular Basis Functions Computation Circuit,” IEEE International Conference on Computer Systems and Applications,pp. 232 – 239, 2006.

[26] Chun Lu, Bingxue Shi, and Lu Chen, “A general-purpose neural network with on-chip BP learning,” IEEE International Symposium on Circuits and Systems, pp. 520-523, 2002.

[27] R. Genov and G. Cauwenberghs, “Dynamic mos sigmoid array folding analog-to-digital conversion,” IEEE Transactions on Circuits and Systems I Regular Papers, pp. 182-186, 2004.

[28] Kuo-Jen Lin, Chih-Jen Cheng, and Jwu-E Chen, “Multi-Point Correction Method in CMOS Current-Mode Function Design,” 2nd International Conference on Electronics and Optoelectronics, Shenyang, China, pp. 294-298, 2012.

[29] Chih-Jen Cheng, Kuo-Jen Lin, and Jwu-E Chen, “CMOS Current-Mode Hyperbolic Tangent Sigmoid Function Implementation Using Multi-Segment Approximations,” 2nd International

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Conference on Electronics and Optoelectronics, Shenyang, China, pp. 299-303, 2012.

[30] Kuo-Jen Lin, Chih-Jen Cheng, Hsin-Cheng Su, and Jwu-E Chen “A CMOS Current-Mode S-Shape Correction Circuit with Shape-Adjustable Control,” IEICE Trans. Electron., Vol.E95-C, No.

11, pp. --, 2012.

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七、

計畫成果自評

國科會 國科會

國科會 國科會補助 補助 補助專題研究計畫成果報告自評表 補助 專題研究計畫成果報告自評表 專題研究計畫成果報告自評表 專題研究計畫成果報告自評表

請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用價 值(簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性)、是否適 合在學術期刊發表或申請專利、主要發現或其他有關價值等,作一綜合評估。

1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估

▓ 達成目標

□ 未達成目標(請說明,以 100 字為限)

□ 實驗失敗

□ 因故實驗中斷

□ 其他原因 說明:

2. 研究成果在學術期刊發表或申請專利等情形:

論文:▓已發表 □未發表之文稿 □撰寫中 □無 專利:□已獲得 □申請中 ▓無

技轉:□已技轉 □洽談中 ▓無

其他:(以 100 字為限)

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3. 請依學術成就、技術創新、社會影響等方面,評估研究成果之學術或應用價 值(簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性)(以 500 字為限)

本研究計畫利用分段趨近的方式,提出實現的電路與趨近的二次多項式電路來達成所 要表達的複雜函數電路。所使用的電路特色是電流模式,能更擴大所需要的動態輸入範 圍,可貢獻在可變增益放大器的應用上及一些複雜函數的實現,例如應用 Sigmoid 的類神 經網路等學術應用。

在分段的技術上,我們採用電流控制的方式來切割段落。然而每個段落的二次多項式 電路也必須精準地表現該段落的曲線,因此在控制分段的電路與二次多項式電路及輸入電 流大小之間的介面就容易造成偏差,因此我們使用特別設計的定電流模組,將造成偏差的 因素,由定電流模組來共同解決。

因為有大的動態輸入範圍,如果應用於手機通訊上的可變增益放大器放大來自基地台 的微弱訊號,將可大幅提高手機的收訊品質。另外如果應用於類神經網路,則可將手機帶 入更智慧型的領域。當然,更進一步的發展,必須搭配更深入的研究,例如針對特定的精 度要求,我們必須分割更多段數來完成,而多少的段數及多大的範圍是電路所不能負擔 的,皆需要進一步的研究。對於可變增益放大器的實作上,也要下點功夫,研究適當的演 算法來實現較低功率的電路。

八、

可供推廣之研發成果資料表

九、

附錄

本研究計畫論文發表共計兩篇國際會議論文及一篇 SCI 期刊論文如下:

1. Kuo-Jen Lin, Chih-Jen Cheng, and Jwu-E Chen, “Multi-Point Correction Method in CMOS Current-Mode Function Design,” 2nd International Conference on Electronics and Optoelectronics, Shenyang, China, 2012. (EI)

2. Chih-Jen Cheng, Kuo-Jen Lin, and Jwu-E Chen, “CMOS Current-Mode Hyperbolic Tangent Sigmoid Function Implementation Using Multi-Segment Approximations,” 2nd International Conference on Electronics and Optoelectronics, Shenyang, China, 2012. (EI)

3. Kuo-Jen Lin, Chih-Jen Cheng, Hsin-Cheng Su, and Jwu-E Chen “A CMOS Current-Mode S-Shape Correction Circuit with Shape-Adjustable Control,” IEICE Trans. Electron., Vol.E95-C, No. 11, pp. --, 2012. (SCI)

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ICEOE2012 and OEMR2012 CONFERENCES SCHEDULE

2012 2nd International Conference on Electronics and Optoelectronics (ICEOE 2012)

2012 International Meeting on Opto-Electronics Engineering and Materials Research (OEMR 2012)

Tianlun Regar Hotel Shenyang Shenyang, China

July 27 - 28, 2012

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July 27 , 2012 (Friday)

Lobby of Tianlun Regar Hotel Shenyang (

沈阳天伦瑞格酒店

大厅)

10:00 – 12:00

14:30 – 18:00 Arrival and Registration Note:(1) You can also register at any time during the conference.

(2) Certificate of Participation can be collected at the registration counter.

(3) The organizer won't provide accommodation, and we suggest you make an early reservation.

Morning, July 28, 2012 ( Saturday )

RUIHE A Hall of The Sixth Floor

6 层瑞和 A 厅

Time: 9:00-12:00

OE0150

Characteristic of Point Defect around the Photonic Crystal Bend

Ruei-Chang Lu, Chun-Min Wang and Keh-Yi Lee

OE0151

Wavelength Division Multiplexer based on Periodic Dielectric Waveguide Ring Resonator

Ruei-Chang Lu, Tung-Hao Chen and Yu-Ping Lia

OE0800

A new design of large area MCP-PMT for the next generation neutrino experiments

Sen. Qian

OE0183

Noise Analysis of EMCCD and Optimum Design of Its Operating Mode

Yugui Zhang,Tao Li and Zhikuan He

OE0590

Optimal Design of CCD Driving Signal Based on FLEX 10K

Zhikuan He, Songbo Wu and Yugui Zhang

OE0239

A 5-port Photonic Lantern for Light Beam Combining

Yan Qi, Haijiao Yu,Fengjun Tian and Weimin Sun OE0539

CPU Experiment of Heat Dissipation and Temperature Rise

Maode Li,Wei Wei and Yi Li

OE0235

Influence of Pump Light’s Duty Cycle on Cesium Atomic Magnetometer

Xianjin Zeng, Junhai Zhang, Qiang Liu, Zongjun Huang and Weimin Sun

OE0645

Influence of Plasmonic Light-Scattering by Gold Nano-island Structures on the Quantum Efficiency of Organic Solar Cell

Baozeng Wang,Xinping Zhang and Jian Zhang

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Multi-Point Correction Method in CMOS Current-Mode Function Design

Kuo-Jen Lin

Department of Electronics Engineering Chung Hua University

Hsinchu, Taiwan Email: kuojenlin@chu.edu.tw

Chih-Jen Cheng and Jwu-E Chen Department of Electrical Engineering

National Central University Taoyuan, Taiwan

Email: 985401005@cc.ncu.edu.tw

Abstract—We propose a multi-point correction method to design a CMOS current-mode function with high input dynamic range. The dynamic range is dependent on the number of correcting circuits. Consider the accuracy, we can properly select the turn-on current in the correcting circuit. The exponential circuit for a design example, equipped with six correcting circuits, has a linearity of 39.5dB for linearity error less than 0.3 dB and has a large input dynamic range from −60µA to 128µA.

I. INTRODUCTION

CMOS current-mode circuits are now attracting more atten- tion in analog circuit design for their bandwidth, large dynamic range, and simplified circuitry. Most of CMOS current-mode circuits operate in the saturation region for high speed appli- cations [1]–[10]. In the region, the square law characteristic of a MOS can be applied to design different functions such as exponential circuits [1]–[3], [5], geometric-mean circuits [4], [6], squarer/divider circuits [4], [6], square-rooter/multiplier circuits [6], [8], multiplier/divider circuits [4], [6], fuzzy logic circuit [6], gamma corrector [9], and fraction power circuits [3], [10].

For realizing some complex functions, several applications [2], [3], [5], [7], [9], [10] also use the second-order Taylor’s approximations to approach the functions. However, the input dynamic range of the second-order Taylor’s approximations are limited for required linearity and accuracy. Moreover, CMOS current-mode circuits suffer from the inherent second- order effects for only using the square-law approaches [4], [8]–[10].

Therefore, how to improve the accuracy and increase the input dynamic range are expected. In this paper, we propose a multi-point correction method to improve the weakness of designing a CMOS current-mode function.

II. CURRENT-MODEFUNCTIONDESIGN

A. Quadratic Function

A quadratic circuit is shown in Fig. 1, which is constructed by the back-to-back connection of M1 and M2 [1]. Assuming that M1 and M2 are operating in the saturation region, then the MOS square-law describes the M1 and M2 drain currents:

I1= Kp(Vgs− |Vtp|)2= Kp(VDD− Vc− |Vtp|)2 (1)

Fig. 1. Basic circuit.

where the transconductance parameters for M1 and M2 are:

Kp = 12µpCoxW1/L1 and Kn = 12µnCoxW2/L2 respec- tively. Since Ix = I2− I1, when K = Kp = Kn, we can derive Vc:

Vc= VDD− |Vtp| + Vtn

2 + Ix

2K(VDD− |Vtp| − Vtn) (3) Substituting (3) into (1) and (2) gives:

I1= K(VDD− |Vtp| − Vtn

2 Ix

2K(VDD− |Vtp| − Vtn))2 (4) I2= K(VDD− |Vtp| − Vtn

2 + Ix

2K(VDD− |Vtp| − Vtn))2 (5) If we set V0= VDD−|V2tp|−Vtn, then

I1= KV02(1 Ix

4KV02)2 (6)

I2= KV02(1 + Ix

4KV02)2 (7)

We observe that I1 and I2 are the quadratic functions of Ix, which means the basic circuit is a current-mode quadratic circuit. To guarantee that M1 and M2 operate in the saturation region, the simple constrains are Vc > Vtn and VDD− Vc >

|Vtp|. Therefore, from (3) we have Ix >−4KV02 and Ix <

4KV02.

B. Design Example

We design an exponential function for presentation. In order to reduce the circuit complexity, we approximate an

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Iout

M1

M2

M3 Im1

Ix

M4 Im2

Im3

Im4

M9

M10 M5

M6

M7 Im5

Ix

M8 Im6

Im7

Im8

Iv Im10 Im9

Fig. 2. Current-mode exponential circuit.

The second order polynomial for evaluating exp(x) at x = 0 is:

exp(x)≈ 1 + x +1

2x2 (8)

Assume that I0= KV02 and Ix= I0x. Equation (6) will be I1= I0(1−x

4)2 (9)

and (7) will be

I2= I0(1 +x

4)2 (10)

To realize the exp(x) by using the current-mode circuit shown in Fig. 2, we could set the possible output (Iout) as

I0exp(x) = I0(1 + x +1

2x2) (11)

We can rewrite it as

I0exp(x) = 8I0(1 +x

4)2− 3Ix− 7I0 (12) or

I0

8exp(x) = I0((1 +x

4)2+ x)−11 8 Ix7

8I0 (13) where I0((1 + x4)2+ x) could be realized by

I0((1 +x

4)2+ x) = 2I0(1 +x

4)2− I0(1−x

4)2 (14) which is the result of (Im7− Im8) as Im7= 2I0(1 +x4)2and Im8= I0(1x4)2. Therefore, we could take mirrors from Im5

and Im6to Im7and Im8with scale two and one, respectively.

If we take mirrors from Im1 and Im2 with scale 118 to Im9 and Im10, respectively, then we can realize

Im10− Im9=11

8 Ix (15)

because 11

8 (I0(1 + x

4)2− I0(1−x

4)2) = 11

8 Ix (16) If Iv is set to 78I0, and Iout= I80g(x) = Iug(x)≈ Iuex, then (13) can be rewritten as

Iout= Im7− Im8+ Im9− Im10− Iv (17)

Pd1 Pi1

ideal simulation

Pi2 Pd2

first correction first correction

x f(x)

second correction

second correction

Fig. 3. Correcting points and their corrections.

III. MULTI-POINTCORRECTIONMETHOD

In the previous circuit design, truncation errors are due to the Taylor’s expansion; K-match errors are due to the assumption of (3); nonlinear errors are due to second-order effects such as channel length modulation, body effect, and mobility degradation. For reducing the errors, we could take some strategies as follows.

A. Sizing Strategy

We could tune the size of transistors which construct a current-mode function circuit to fit a function as possible.

For example, we could size M3 and M4 in Fig. 2 to make the same value of two Ix. We can also tune the M7 and M8 to obtain a good result of (Im7− Im8), which could really match I0((1 +x4)2+ x). We also size the M9 and M10 to realize (15). Consequently, we can accurately realize the Taylor’s approximation circuit for the function of I80exp(x).

However, the input dynamic range is also limited.

B. Multi-Point Correcting Circuit

In the design stage, simulation results could show the error figures. We could arrange some correcting points to correct errors. Figure 3 shows the error and correction examples. As x > Pi1 shown in Fig. 3, we could conduct Pi1 circuit to increase the output current. As x > Pd2, we conduct Pd2

circuit to decrease the output current. As x < Pd1, we could conduct Pd1circuit to decrease the output current. As x < Pi2, we conduct Pi2circuit to increase the output current. The Pi1, Pd2, Pd1, and Pi2 circuits are shown in Fig. 4.

Consider accuracy and the input dynamic range, we need carefully tune the scales of current-mirrors of the correcting circuits. By using the multi-point correcting circuits, we can re-design the circuit shown in Fig. 2 into the circuit shown in Fig. 5. In Fig. 5, three Pi1 circuits are used for Ix > 0 and two Pd2 circuits and one Pi1 circuit are used for Ix< 0. The number of correcting circuits is dependent on the accuracy and the input dynamic range.

IV. SIMULATIONRESULTS

To verify the sizing strategy and multi-point correcting

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Iout

M1

M2

M3

Iv

Im1

Ix

M4

M9

M10

M11

m2 M12 I

Im3

Im4 Im10

M5

M6

M7 Im5

Ix

M8 Im6

Im7

Im8

M1b

M2b M1a

M2a

M1c

M2c

M1d

M2d

M1e

M2e

M5f

M6f

Mb Mbb

Ma Maa

Mf Mff

Mc Mcc

Mdd Mee

Im9

Ia

If

Ie

Ic

Id

Ib

Md Me

Ix x -

I - Ix

-

Ix Ix Ix

loader a

circuit

Pi1 Pi1circuitb Pi1circuitc

f circuit− Pi1

d circuit

Pd2 Pd2circuite

Fig. 5. Multi-point correction circuit for design example.

Ipi1

Ipd2

Ix

Ipi2 Ix

Ix

Ipd1

Ix

circuit Pi2

(c)

circuit Pd2

(b)

circuit Pd1

(d) circuit

Pi1

(a)

Fig. 4. Four different correcting circuits.

TSMC technology. The supply voltage VDD of the circuit in Fig. 5 is set to be 2.5V . If Ix is from −120µA to 120µA, then I should be set to be 40µA for comparing to the input

middle value of the input current range is 0µA, the width of M5 and M6 is designed to be 3.5µm and 1.3µm, respectively for making Kp = Kn = K at Ix= 0µA. Consequently, due to I0= KV02, I0 is tuned to be 41.1µA.

Figure 6 shows the Iout simulation results. The multi-point correction method nearly match the ideal exponential function for Ixfrom−60µA to 128µA. The linearity is about 39.5dB observed from Fig. 7 for linearity error less than 0.3dB shown in Fig. 8. The linearity of Taylor approximation is only 9dB.

From Fig. 8, we can observe that the correction points are located at Ix= 18µA, Ix= 57µA, Ix= 93µA, Ix=−30µA, Ix = −53µA, and Ix = −57µA. When Ix = 18µA, the Pi1 circuit-a is on for Ia = 18µA, which controls the linearity error below 0.3 dB. Similarly, Ib = 57µA and Ic = 93µA for Pi1 circuit-b and Pi1 circuit-c, respectively.

When Ix = −30µA and Ix = −53µA, Pd2 circuit-d and Pd2 circuit-e are on for Id = 30µA and Ie = 53µA, which control the linearity error less than -0.3 dB. When Ix =−57µA, the Pi1 circuit-f is on for If = 57µA, which controls the linearity error less than -0.3 dB. Obviously, the most efficient correction points for the exponential function design are located in the side of I > 17µA. This side

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