Design of low-voltage CMOS low-noise
amplifier with image-rejection function
L.-S. Wei, H.-I. Wu and C.F. Jou
A new design is presented that combines a low-noise amplifier (LNA) with an on-chip filter instead of external filter to eliminate image signal based on TSMC 0.18 mm CMOS technology. The fully integrated 5.9 GHz LNA exhibits 15.2 dB gain, 3.2 dB noise figure, better than 215 dB input and output return loss, and 227 dB image rejec-tion. The circuit operates at a supply voltage of 1 V and consumes only 6.1 mW power.
Introduction: For radio-frequency (RF) integrated circuit wireless recei-vers, the need for low-power and low-cost systems demands the use of CMOS technology to arrive at a single-chip solution. However, the image problem requires an off-chip filter. The image-rejection (IR) filter usually is an external component, such as a surface-acoustic wave filter. This kind of filter is often expensive and large, which increases power consumption and costs, and is thus not suitable for inte-gration. For this purpose, research into LNA with IR technique has developed [1 – 3] and improved RF level of integration. In [1], the active notch filter, which provides the lowest dip of input impedance at image frequency, is implemented in the signal path of a cascode LNA circuit; thus the image signal will be connected to ground. However, the active filter will contribute extra power and noise, and in addition a stack of three stages needs higher supply voltage (3 V). In this Letter, we present a new design that employs the current-reuse technique with an LC tank at inter-stage to achieve simultaneously an IR function and a lower power dissipation than in[1 – 3]. From measured results, it successfully provides 227 dB IR while exhibiting comparable performance to the traditional current-reuse amplifiers.
VDD Ld Cbs X RFin Y C1 M1 Ls G1 G1 C2 M2 L1 L2 Cout Vbias RFout
Fig. 1 Circuit schematic of proposed LNA
Circuit design: The schematic diagram of the proposed LNA is shown inFig. 1. The supply voltage (VDD) is 1 V and the bias voltage (Vbias) is
0.7 V. The circuit topology exploits the current-reuse technique, M1and
M2transistors are a stack and use the same bias current and therefore the
total power consumption is minimised. To achieve input impedance matching, only a small Lsvalue is required. This Lsvalue is done by
layout of a small transmission line at M1source connected to ground,
instead of using a spiral inductor component, so that area and cost can be saved. A simple LC network (Ld, Cout) is used to match the 50 V
output impedance for measurement requirements. The passive IR filter is implemented at inter-stage and consumes no additional power com-pared with the active filter. The LC tank (L1, C1) is added and designed
to resonate at image frequency so as to provide high impedance to reject the image. In the signal path as shown inFig. 2a, the voltage ratio of node X to node Y, Av, can be derived as
Av’ 1=sCin2 1=sCin2þ ð1=sC1==sL1Þ ¼ s 2þ1=L 1C1 s2þ1=L 1C1ð1 þ Cin2=C1Þ ð1Þ where Cin2is gate parasitic capacitance of M2, which has small value
(7 fF in this design) compared to the DC blocking capacitor C2, thus
C2is negligible in the analysis. From (1), the image and RF frequencies
are located at zero and pole, respectively: fimage¼ 1 2p ffiffiffiffiffiffiffiffiffiffiL1C1 p and fRF¼ 1 2p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiL1C1ð1 þ Cin2=C1Þ p ð2Þ
The RF signal is enhanced and the image signal is filtered out from node Y to node X. With design for small Cin2/C1, the image signal can be set
to close to the RF signal. In general, the quality factor Q of the on-chip integrated inductor is worse. To overcome this problem, the Q enhance-ment technique is proposed in this design. As shown inFig. 2b, the input impedance of M2at high frequency can be expressed as
Zin¼rg2 gm2 v2C gs2Cbs þ 1 jv 1 Cgs2 þ 1 Cbs ð3Þ
where Cgs2is the gate-to-source parasitic capacitance, and rg2is the
series gate parasitic resistance. Note that L2serving as an RF choke
can be ignored at high frequency for simplicity. In (3) the second term on the right-hand side is negative resistance proportional to gm2,
and by adjusting the size of M2, sufficient negative resistance can be
generated to cancel out rg2and the parasitic resistance of the on-chip
inductor L1. To verify the IR ability of the filter, the simulation result
of Av is shown in Fig. 3a. We can observe that the RF signal at
5.9 GHz passes through the filter and the image signal at 7.3 GHz is fil-tered out. In addition to rejecting the image signal, the filter is also used as the inter-stage matching.Fig. 3bshows that, at node Y, the simulated reflection coefficients G1and G2are approximately complex conjugate
matching to achieve maximum power transformation.
Y X a b X C2 C1 L1 Cin2 rg2 Zin Cgs2 Vgs2 Cbs gm2·Vgs2
Fig. 2 IR filter and small-signal equivalent circuit looking into gate of M2
a IR filter b Equivalent circuit 5 0 Av , dB 1 2 3 4 5
frequency, GHz operation frequency
6 7 a b 8 9 10 –5 –10 –15 –20 –25 –30
Fig. 3 Simulation of Av¼ X/Y and inter-stage matching
a Av¼ X/Y
b Inter-stage maching
Measured results: The proposed LNA with IR function for wireless local area network (WLAN) receivers has been fabricated based on TSMC 0.18 mm CMOS 1P6M technology. It operates at 5.9 GHz, and image frequency is at 7.3 GHz. The chip photo of the proposed LNA is shown inFig. 4, and the total chip size is 0.69 mm2including the
probing pads. The pads use bottom ground metal as shielding. The total power consumption is 6.1 mW from a 1 V supply voltage. The measured input and output return loss are 216.4 and 215 dB at 5.9 GHz, respectively, as shown inFig. 5. The lowest dip of S22shifts
0.1 GHz owing to process variation.Fig. 6shows gain (S21) and noise
figure. The measured gain achieves a maximum of 15.2 dB at 5.9 GHz and IR of 227 dB at 7.3 GHz. The measured noise figure is 3.2 dB and input-referred third-order intercept point (IIP3) is 29 dBm.
Fig. 4 Photograph of proposed LNA 0 –5 –10 S11 , S22 , dB –20 –15 –25 1 2 3 4 5 frequency, GHz 6 7 S22 S11 8 9 10
Fig. 5 Measured results of input and output return loss
20 15 10 5 S21 NF 0 2 3 4 5 6 frequency, GHz 7 8 9 10 S21 , dB NF , dB –5 –10 –15 –20 –25 –30 30 27 24 21 18 15 12 9 6 3 0
Fig. 6 Measured results of gain and noise figure
Conclusions: A fully integrated low-voltage IR LNA using Q enhance-ment technique for WLAN is proposed, based on current-reuse configur-ation for low-power operconfigur-ation, not cascode as in major traditional IR LNA. The IR filter is composed of passive components in order to allow less noise and less power consumption compared to an active filter. The experimental results show that this circuit provides better IR ability and lower power than[1]. The performance of the proposed LNA satisfies the system specification and chip size is comparatively small.
Acknowledgment: The authors thank the Chip Implementation Center (CIC) of the National Science Council, Taiwan, Republic of China, for supporting the TSMC CMOS process.
#The Institution of Engineering and Technology 2008 9 May 2008
Electronics Letters online no: 20081246 doi: 10.1049/el:20081246
L.-S. Wei, H.-I. Wu and C.F. Jou (Department of Communication Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan 300, Republic of China)
E-mail: lswei1984@gmail.com References
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