新型紅外線偵測器陣列之互補式金氧半電流讀出積體電路設計與分析及影像應用

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(1)國立交通大學電機學院 IC 設計產業研發碩士班碩士論文. 新型紅外線偵測器陣列之互補式金氧半電流讀出積體電路設計與分析及影像應用 THE ANALYSIS AND DESIGN OF NEW CMOS CURRENT READOUT INTEGRATED CIRCUIT FOR INFRARED DETECTOR ARRAY AND IMAGE APPLICATIONS. 研究生：李允斌指導教授：吳重雨教授. 中華民國九十六年一月 - iv -.

(2) 新型紅外線偵測器陣列之互補式金氧半電流讀出積體電路設計與分析及影像應用 THE ANALYSIS AND DESIGN OF NEW CMOS CURRENT READOUT INFRARED CIRCUIT FOR INFRARED DETECTOR ARRAY AND IMAGE APPLICATIONS 研究生：李允斌. Student: Yun-Bin Lee. 指導教授：吳重雨博士. Advisor: Dr. Chung-Yu Wu. 國立交通大學電機學院 IC 設計產業研發碩士班碩士論文. A Thesis Submitted to College of Electrical and Computer Engineering National Chiao Tung University in partial Fulfillment of the Requirements For the Degree of Master In Industrial Technology R & D Master Program on IC Design June 2007 Hsinchu, Taiwan, Republic of China. 中華民國九十六年一月 -v-.

(3) 新型紅外線偵測器陣列之互補式金氧半電流讀出積體電路設計與分析及影像應用. 研究生：李允斌. 指導教授：吳重雨博士. 國立交通大學電機學院 IC 設計產業研發碩士班. 摘. 要. 當積分電容是由一整行共用時，我們必須減小積分端點的總寄生電容，對於減少積分時間與提昇電路操作速度。一個新的像素架構對於減小積分端點的寄生電容是這個論文中被提出，且這一個晶片是首次應用雙重三角取樣（Double Delta Sampling）電路在砷化銦鎵感測器陣列，此電路可用來減小固定樣式雜訊（fixed pattern noise），時脈回饋雜訊和通道電荷注入。有著新的像素架構和雙重三角取樣技術的的32 x 32讀出電路晶片是透過國家晶片系統設計中心委託台灣積體電路製造股份有限公司以0.35微米互補式金氧半導體的製程製造。晶片的面積是2500 μm x 2461 μm和操作在3.3 V電源供應時產生的18 mW功率消耗。整個 32 x 32 電流讀出電路已經被完整地設計、製造與量測完成。這個實驗性的晶片已經成功地證明了新提出的像素架構可以應用在共用積分電容的紅外線偵測器影像系統。. - vi -.

(4) The ANALYSIS AND DESIGN OF NEW CMOS CURRENT READOUT INFRARED CIRCUIT FOR INFRARED DETECTOR ARRAY AND IMAGE APPLICATION. Student: Yun-Bin Lee. Advisor: Dr. Chung-Yu Wu. Degree Program of Electrical Engineering Computer Science National Chiao-Tung University. Abstract When the integration capacitor is shared by one column, we must decrease total parasitic capacitance of integration capacitor for decreasing integration time and increasing operational speed. A new pixel structure for decreasing total parasitic capacitor of integrated node is proposed in this thesis, and this chip is first application to double delta sampling (DDS) for InGaAs IR detector array. The double delta sampling (DDS) circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed 32 x 32 ROIC with new pixel structure and double delta sampling technique has been fabricated by using 0.35 μm CMOS technology support by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center. Chip size is 2500 μm x 2461 μm, and power dissipation is 18 mW under the power supply of 3.3V. The proposed 32 x 32 ROIC is completely design, fabrication and tested. It has been demonstrated that this chip can be applied in the design of infrared imaging systems with shared integration capacitor by one column. -vii-.

(5) 誌. 謝. 能夠順利完成碩士論文，首先要感謝我的指導教授吳重雨博士；在研究所的這兩年半裡，老師提供我一個良好的學習環境，並且在學習與研究上適時的給予我指導與啟發且給予我能夠受到這個環境薰陶的機會，其嚴謹的研究精神以及對人謙虛和善的態度，使我受益良多。其次要感謝論文口試的評審委員，柯明道教授、謝志成博士與廖枝旺博士對我的論文提出了許多建議，使我的論文內容更加完整。另外，我要感謝中華電信研究所洪朝基博士、何博士、劉一鳴大哥、在 IC 量測上提供我許多的幫助。再來要感謝實驗室的學長們，施育全學長、林俐如學姊、陳勝豪學長、王文傑學長、虞繼堯學長、蘇烜毅學長、陳旻珓學長、林韋霆學長、陳煒明學長、歐欣華學長、劉衛宗學長、王仲益學長、金毛學長們給予我的幫助與指點和研究上的經驗傳承。同時也感謝怡凱、志遠、豪傑、汝玉、立龍、神童、鯉魚、Acer、晏維、國忠、萬諶、順維、柏宏，在學校瑣事的幫忙，並陪伴我度過這段研究生活，也增添了許多歡笑與回憶。最後，要感謝我的父母以及周玲、韻竹、烏龜、盈鋒、阿達，當我面臨壓力時鼓勵我，給我繼續前進的動力，當我研究繁忙時體諒我，讓我可以全心衝刺。得之於人者太多，謹以此篇論文獻給所有關心我的人。. -viii-.

(6) CONTENTS Chinese Abstract. i. English Abstract. ii. Acknowledgement. iii. Contents. iv. Table Captions. vi. Figure Captions. vii. CHAPTER 1 INTRODUCTION. 1. 1.1 Background. 1. 1.2 Review on CMOS readout technique for IR FPA. 4. 1.3 Motivation. 12. 1.4 Thesis organization. 13. CHAPTER 2 ARCHITECTURE AND CIRCUIT DESIGN 2.1 Chip architecture. 14 14. 2.1.1 The chip architecture of 32 x 32 IR FPA. 14. 2.1.2 The chip architecture of 320 x 256 IR FPA. 15. 2.2 Circuit implementation. 16. 2.2.1 The circuit implementation of 32 x 32 IR FPA. 17. 2.2.2 The circuit implementation of 320 x 256 IR FPA. 24. 2.3 Chip operational principle. 29 - ix -.

(7) 2.3.1 The chip operation of 32 x 32 IR FPA. 29. 2.3.2 The chip operation of 320 x 256 IR FPA. 31. 2.4 Simulation results. 33. 2.4.1 Simulation results of 32 x 32 IR FPA. 35. 2.4.2 Simulation results of 320 x 256 IR FPA. 41. CHAPTER 3 CMOS READOUT CIRCUIT APPLICATION TO BIOCHEMISTRY. 46. 3.1 Background. 46. 3.2 Circuit implementation. 48. 3.3 Simulation results. 49. CHAPTER 4 THE EXPERIMENTAL RESULTS. 52. 4.1. Measurement of 32 x 32 IR FPA. 52. 4.2. Measurement of biochemical chip. 67. CHAPTER 5 CONCLUSIONS AND FUTURE WORK. 74. 5.1 Conclusions. 74. 5.2 Future work. 75. REFERENCES. -x-.

(8) Table Captions Table I. The device parameters of the unit cell. .................................................................25. Table II. The summary of specification of the 32 x 32 readout chip................................40. Table III The summary of specification of the 320 x 256 readout chip. .........................45 Table IV. Important biochemicals that can be determined by HRP-luminol-H2O2. system.......................................................................................................................................47 Table V The summary of operational specification of the readout chip.........................49 Table VI. The summary of measured results of the 32 x 32 ROIC. .................................66. - xi -.

(9) Figure Captions Fig. 1. The technologies of the hybrid array structures: (a) the flip-chip array. technology; (b) the Z-plane technology...................................................................................3 Fig. 2. Hybrid IR FPA interconnect techniques between a detector array and a silicon. multiplexer. (Indium bump technique)...................................................................................3 Fig. 3. (a) The direct injection (DI) readout circuit;(b) The small signal ac equivalent. circuit for the DI structure.......................................................................................................6 Fig. 4. The gate modulation input (GMI) readout circuit...................................................7. Fig. 5. (a) The buffered direct injection (BDI) readout circuit; (b) The equivalent circuit. for the BDI structure. ...............................................................................................................8 Fig. 6 The capacitive transimpedance amplifier (CTIA) readout circuit.........................9 Fig. 7. The buffered gate modulation input (BGMI) readout circuit. ............................. 11. Fig. 8. Structure of the Current Mirroring Integration circuit. .......................................12. Fig. 9. The block diagram of 32 x 32 IR FPA.....................................................................15. Fig. 10. The block diagram of 320 x 256 IR FPA...............................................................16. Fig. 11 The united-cell stage (a) conventional united-cell stage of SCI readout structure (b) proposed new united-cell stage. .......................................................................................18 Fig. 12 The simulation results of the reset signal and integrated signal (a) conventional united-cell stage of SCI structure (b) new united-cell stage. ..............................................19 Fig. 13. Typical double delta sampling circuit. ..................................................................20. Fig. 14. The timing of typical double delta sampling circuit. ...........................................21. Fig. 15 The improved DDS circuit......................................................................................21 Fig. 16. The united-cell stage of 320 x 256 IR FPA............................................................24. Fig. 17. The column CDS stage of 320 x 256 IR FPA. .......................................................26. Fig. 18. The dynamic output stage of 320 x 256 IR FPA...................................................28 -xii-.

(10) Fig. 19. The detailed circuit involving united-cell stage, column sampling circuit, and. output CDS circuit..................................................................................................................29 Fig. 20. The timing major diagram of the 32 x 32 IR FPA. ..............................................31. Fig. 21. The detailed circuit of 320 x 256 readout chip. ....................................................32. Fig. 22. The timing major diagram of the 320 x 256 IR FPA. ..........................................33. Fig. 23 The responsitivity of the InGaAs detector developed by Chunghwa Telecom laboratory. ...............................................................................................................................34 Fig. 24 The characteristic of the InGaAs detector array developed by Chunghwa Telecom laboratory. ................................................................................................................34 Fig. 25. Measurement of dark current of InGaAs detector array developed by. Chunghwa Telecom laboratory. ............................................................................................35 Fig. 26. The chip photo of the InGaAs detector developed by Chunghwa Telecom. laboratory. ...............................................................................................................................35 Fig. 27. The voltage difference between Vout_S and Vout_R of Fig. 19 for the input. photocurrent from 5p to 105p with 10pA step. ....................................................................37 Fig. 28. The linearity of the voltage difference between Vout_S and Vout_R for input. photocurrent 5pA to 105pA with 10pA step. ........................................................................37 Fig. 29. The voltage difference between Vout_S and Vout_R of Fig. 19 for the input. photocurrent from 100p to 5000p with 350pA step. ............................................................38 Fig. 30. The linearity of the voltage difference between Vout_S and Vout_R for input. photocurrent 100pA to 5000pA with 350pA step. ................................................................38 Fig. 31. The series output voltage difference between Vout_S and Vout_R of 32 cells for. input photocurrent 40pA to 5000pA with 160pA step. ........................................................39 Fig. 32. The cell array masks of 32 x 32 IR FPA. ..............................................................39. Fig. 33. The simulated waveforms of output voltage Vout in the dynamic output stage. for the input photocurrent from 0pA to 500pA with 50pA step. ........................................42 -xiii-.

(11) Fig. 34. The linearity of output voltage Vout in the dynamic output stage for the input. photocurrent from 0pA to 500pA with 50pA step................................................................42 Fig. 35. The simulated waveforms of output voltage Vout in the dynamic output. stage for the input photocurrent from 0p to 5000pA with 500pA step. .............................43 Fig. 36. The linearity of output voltage Vout in the dynamic output stage for the input. photocurrent from 0pA to 5000pA with 500pA step............................................................43 Fig. 37 The series output voltage (Vout) of 32 cells for input photocurrent 40pA to 5000pA with 160pA step. ........................................................................................................44 Fig. 38 The layout of 320 x 256 readout chip. ...................................................................44 Fig. 39. The readout circuit for detection chemiluminescence. ........................................48. Fig. 40. The simulated waveforms of output voltage Vout for the input photocurrent. from 10pA to 250pA with 10pA step. ....................................................................................50 Fig. 41. The linearity of output voltage Vout for the input photocurrent from 10pA to. 250pA with 10pA step. ............................................................................................................50 Fig. 42. The simulated waveforms of output voltage Vout for the input photocurrent. from 1nA to 111nA with 10nA step........................................................................................51 Fig. 43. The linearity of output voltage Vout for the input photocurrent from 1nA to. 111nA with 10nA step. ............................................................................................................51 Fig. 44. Die photograph of the 32 x 32 readout chip for InGaAs detector array............53. Fig. 45. The environment setup for measuring digital function. ......................................53. Fig. 46. The measured waveform of digital component. ...................................................54. Fig. 47. The environment setup for measuring analog function.......................................54. Fig. 48 The measured output waveforms (Vout = Vout_S – Vout_R) of single pixel and equivalent image under different current. ...........................................................................56 Fig. 49. The linearity of the voltage difference between Vout_R and Vout_S for input. photocurrent 1000pA to 5000pA with 500pA step. ..............................................................56 -xiv-.

(12) Fig. 50. The CHIP_J (clock rate=400 KHz) combined with InGaAs detector array has. been measured under two conditions: (a) unilluminated condition (b) fluorescent lamp. ..................................................................................................................................................58 Fig. 51 The measured output voltage (Vout) of chip_J with clock rate of 400 KHz has been measured under two conditions: (a) unilluminated condition (b) fluorescent lamp. ..................................................................................................................................................58 Fig. 52. The CHIP_J (clock rate=200 KHz) combined with InGaAs detector array has. been measured under two conditions: (a) unilluminated condition (b) Fluorescent lamp. ..................................................................................................................................................59 Fig. 53 The measured output voltage (Vout) of chip_J with clock rate of 200 KHz has been measured under two conditions: (a) unilluminated condition (b) fluorescent lamp. ..................................................................................................................................................59 Fig. 54. The CHIP_F (clock rate=400 KHz) combined with InGaAs detector array has. been measured under two conditions: (a) unilluminated condition (b) fluorescent lamp. ..................................................................................................................................................60 Fig. 55. The measured output voltage (Vout) of chip_F with clock rate of 400 KHz has. been measured under two conditions: (a) unilluminated condition (b) fluorescent lamp. ..................................................................................................................................................60 Fig. 56. The environment setup of measuring laser light..................................................61. Fig. 57. The measured output voltage (Vout) of single pixel of 32 x 32 ROIC combined. with InGaAs detector array via laser light with wavelength 1550 nm. .............................63 Fig. 58. The measured output voltage (Vout) of pixel #1 versus different laser power. from 0 uW ～ 7.452 uW........................................................................................................64 Fig. 59 The measured output voltage (Vout) of pixel #2 versus different laser power from 0 uW ～ 5.812 uW. ................................................................................................................64 Fig. 60 The measured laser power of Photonetics tunable cavity laser. (a) around 3 uW -xv-.

(13) by power meter, max = 3.322 uW, min = 3.176 uW, error = 4.6 %. (b) around 5 uW by power meter, max = 5.196 uW, min = 4.951 uW, error = 4.86 %. ......................................65 Fig. 61. Die photograph of the readout chip for detection chemiluminescence. .............68. Fig. 62. The environment setup of measurement...............................................................68. Fig. 63. The measured Vout waveforms of biochemical chip with clock=125 KHZ. ......69. Fig. 64. The measured linearity of biochemical chip with clock = 125 KHZ. .................69. Fig. 65. The measured Vout waveforms of biochemical chip with clock=10 KHZ. ........70. Fig. 66. The measured linearity of biochemical chip with clock = 10 KHZ. ...................70. Fig. 67. The environment setup for measuring chemical reactions. ................................71. Fig. 68. The Coupled enzyme reaction kinetics using incubation method detected by (a). CMOS chip and (b) UV 3300 system. ...................................................................................73 Fig. 69. The H2O2 concentration with CHOD = 0.02U, HRP = 0.016U detected by (a). CMOS readout chip and (b) UV-Vis-3300. ..........................................................................73. -xvi-.

(14) CHAPTER 1 INTRODUCTION 1.1 Background. The discovery of infrared radiation occurred in 1800 when Sir William Herschel essentially repeated Newton’s famous prism experiment and detector heat in the region just above the visible spectrum. The Planck radiation formula was derived in 1900 and quantitatively predicted the amount of energy radiated from a blackbody as a function of temperature and wavelength. During the 1950’s and 1960’s infrared sensors were used in anti-air missile seeker. At the same time, rapid advances were made in narrow bandgap semiconductors that would later prove to be useful in extending wavelength capabilities and improving sensitivity [1]. Infrared focal plane arrays have been developed for various applications including medical examination [1], astronomy [2], forward-looking infrared (FLIR) system, missile guidance, and night vision equipment. The rapid advancement in CMOS VLSI with the progress in infrared focal-plane array (IR FPA) technologies like detector material, sensing structure, optics, coolers, readout electronics, image enhancement, and intelligent signal processing results in the revolution of IR image systems to a new generation with significant performance improvement. The application of various developed technologies on the design of IR FPAs has resulted in the advantages of simplified electrical interconnection, reduced signal number leads, higher performance reliability, and simplified package. Some commonly used structures of the three major classes of IR FPAs, namely, hybrid array, monolithic array, and pseudo-monolithic array. In the following, the hybrid array employed in this thesis will be described in detail.. 1.

(15) Hybrid Array： The most commonly used IR FPA structures in the hybrid array [3] are flip-chip and Z-plane technologies [4] as shown in Fig. 1(a) and 1(b), respectively. In Fig. 1(a) involves mating the detector array to a silicon multiplexer where the front side of the detector array is aligned with multiplexer and one contact for each detector is made using a previous deposited set of indium bumps fabricated on both the detector array and on the silicon multiplexer [5], [6] as shown in Fig. 2. IR detector array chip and silicon readout chip are compounded by the indium bump grown on the aligned pixels of both chips. The detector array can be illuminated from either the front side (with the photons passing through the transparent silicon multiplexer) or backside (with the photons passing through the transparent detector array substrate). This is the mostly used structure in the hybrid array technology, and this method is also used in my work. In the Z-plane technology shown in Fig. 1(b), the readout chips are stacked one on top of another and then the detector array is mounted to the third dimensional plate on the edge. In the Z-plane structure, one readout chip is used by one channel of detectors so that many electrical circuit techniques like complex input circuit, gain offset correction, analog-to-digital converter, filter, smart and neural function, as well as image signal processing stage can be implemented on the readout chip [7]. To achieve very small detector sizes however, the silicon IC chips must be thinned to very small dimensions. The image resolution is limited by the readout chip thickness. In the application of hybrid array technology, uniformity of indium bumps, chip alignment as well as thermal expansion effect and mechanical damage on the detectors should be considered during the hybridization process [8].. 2.

(16) Photon Flux Hybrid/Indium Bond. Readout chip Detector Array (InSb, HgCd) Detector Array Back plane Multiplexer. Readout/Multiplexer (Silicon). To Preamp, ADC. In bump contact. (a). Fig. 1. (b). The technologies of the hybrid array structures: (a) the flip-chip array technology; (b) the Z-plane technology.. Fig. 2. Hybrid IR FPA interconnect techniques between a detector array and a silicon multiplexer. (Indium bump technique). 3.

(17) 1.2 Review on CMOS readout technique for IR FPA. In the design of the infrared (IR) focal-plane array (FPA), high resolution has become a common requirement in many applications. To achieve the optimal overall performance of the IR FPAs, suitable trade-off among circuit performance, power dissipation, chip area, and image resolution should be made. A number of readout structures have been developed for different system application and concern. A high performance readout circuit should provide a stable and near zero detector bias to reduce the dark current and detector noise. It should have low input impedance to obtain high injection efficiency, large dynamic range, large charge capacity, high output swing, and low input referred noise. The integration capacitor is preferred to be placed outside of the pixel to increase its value without increasing the pixel size. Earlier. readout. structures,. including. source-follower-per-detector. (SFD). [9],. direct-injection (DI) [10], and gate modulation input (GMI) [11] are simple occupy small area, but they cannot satisfy most of the high performance requirement. Later amplifier structures, such as buffered-direct-injection (BDI) [12], and capacitive feedback transimpedance amplifier (CTIA) [13], provide a better performance in term of injection efficiency and detector bias stability with the help of an in-pixel opamp, but their performance is limited with the quality of the opamp that should be implemented in a small pixel area. A novel approach, buffered gate modulation input (BGMI) [14], provides in-pixel detector current amplification and background flux suppression and places the integration capacitance outside of the pixel, but it also requires in-pixel operational amplifier components for detector bias stabilization. Another approach, current mirroring integration (CMI)[15], [16], satisfies the high injection efficiency and almost-zero detector bias requirement. However, the CMI also requires the integration capacitor to be in the pixel, and therefore has large pixel area, low dynamic range, and low charge storage capacity. A recent novel 4.

(18) approach, switched current integration (SCI) [17], provides large charge storage capacity, stable detector bias, high injection efficiency, and very low input impedance. A number of readout structures have been developed for different system application and concern. In the following, some of commonly used CMOS readout techniques are described below.. 1) Direct Injection（DI）[10]： A simple readout circuit called direct injection (DI) is shown in Fig. 3(a), and the small signal ac equivalent circuit for the DI is shown in Fig. 3(b). The charge carries generated by the detector are directly injected into the input diffusion and potential well under the storage gate where it is accumulated. The direct injection approach has the advantage of simplicity (small area) and high injection efficiencies. The injection efficiency of direct injection can be expressed as. η ( s )( DI ) =. gm ⋅ (CGS + C D ). 1 1 + gmRD S+ RD (CGS + C D ). (1.1). At the low frequency can be expressed as. η LF ( DI ) =. gmRD 1 + gmRD. (1.2). where gm is the transconductance of MOSFET, CD is the internal capacitance of detector, and RD is the internal resistance of detector at the operating voltage. The 3-dB injection bandwidth for detector current can be expressed as. fBW =. 1 + gmRD 2πRD (CD + CGS ). (1.3). The origin of these dc offsets between different DI structures is attributed to the MOS threshold voltage. The dc offset variations (about ±250mv) are significant, and cause IR detector to become noisy.. 5.

(19) Vdetector IR Sensor. gmVG. detector model. S. RD. CD VGS. Idetecto. CGS. Io. r. Vgate. Mpi. Vcas. Id. CD. RD. Mncas. Fig. 3. (a) The direct injection (DI) readout circuit;(b) The small signal ac equivalent circuit for the DI structure.. 2) Gated-Modulation-Input（GMI）[11]：. The conventional gate modulation input (GMI) structure is composed with the IR detector, a current mirror which mirrors and amplifies the photo excited current and a integration capacitance Cint as shown in Fig. 4. The detector absorbs the infrared flux and generates photo current. The photo excited current flows into Mload of the current mirror and amplified by Minput. The amplified current then flows into the integration capacitance and transferred it to output voltage. Similar to that in the DI circuit, the injection efficiency of the GMI is dependent on the ration of detector shunt resistance to input of Mload. The GMI leads to higher detection sensitivity, high injection efficiency and reduced input referred noise as compared to DI. Due to the simple structure, the pixel pitch can be very small to extend the array size larger. The current gain can be adjusted to suitable value according to the current level by the external adjustable Vsource. The drawbacks of GMI are that the injection efficiency and linearity are affected by the threshold voltage variation and the noise of the adjustable Vsource. 6. Cint.

(20) Fig. 4. The gate modulation input (GMI) readout circuit.. 3) Buffered Direct Injection（BDI）[12]：. A complex readout circuit called the buffered direct injection (BDI) circuit is shown in Fig. 5 where the circuit structure is similar to the DI except that an additional inverted gain stage with the gain –A is connected between gate node of the common-gate input device and detector node. The BDI can be satisfactorily alleviated by an actively compensated injection structure. In this configuration, the transfer gate is no longer held at a constant potential, but varies in proportion to the photogenerated current of the detector. Analysis of this circuit shows that it operates like the previously described direct injection circuit but with an effective gm, that is increased by a factor of (1 +A) where A is the gain of the amplifier. Another advantage of the buffered direct injection circuit is that the amplifier operating voltages can be controlled, allowing some flexibility in the level of reverse bias voltage applied to the detector. The buffered direct injection circuit achieves improved injection efficiency, better frequency response and lower noise.. 7.

(21) Fig. 5. (a) The buffered direct injection (BDI) readout circuit; (b) The equivalent circuit for the BDI structure.. The injection efficiency of direct injection can be expressed as η ( s )( BDI ) =. (1 + A) gm ⋅ C D + (1 + A)(C GS + C A ). 1 1 + (1 + A) gmRD S+ RD[C D + (CGS + C A )(1 + A)]. (1.4). At the low frequency can be expressed as. η LF ( BDI ) =. (1 + A) gmRD 1 + (1 + A) gmRD. (1.5). where C A is output-input capacitance of gain stage, gm is the transconductance of MOSFET, CD is the internal capacitance of detector, and RD is the internal resistance of detector at the operating voltage. The 3-dB injection bandwidth for detector current can be expressed as fBW =. 1 + (1 + A) gmRD 2π • RD[C D + (CGS + C A )(1 + A)]. (1.6). Clearly, the injection from the BDI structure is much less dependent on the input shunting capacitance and resistance than in conventional direct-injection case. Moreover, 8.

(22) circuit techniques exist which can minimize the output-input coupling capacitance C A of the gain stage –A such that an increase injection bandwidth is obtained.. 4) Capacitive transpedance amplifier（CTIA）[13]：. The schematic of the capacitive transimpedance amplifier (CTIA) is shown in Fig. 6. Where the integration capacitor Cint is placed on the feedback loop of the amplifier with a reset device M-Rst to discharge the integration capacitor and reset the amplifier output to the reference voltage Vcom. The detector bias is also controlled by Vcom through the virtual-short feature of the amplifier. Due to the Miller effect on the integration capacitor, its capacitance can be made extremely small. Unlike DI and BDI, the input impedance of the CTIA is independent of detector current. Thus a good detector bias control can be obtained in the CTIA as the BDI, and the CTIA can achieve very high sensitivity without the change of bias voltage. Although the CTIA can achieve high sensitivity and stable detector bias, the CTIA increase area and power consumption of the inverted gain stage. Usually, the inverted gain stage is implemented by a differential amplifier to provide low offset.. Fig. 6 The capacitive transimpedance amplifier (CTIA) readout circuit. 9.

(23) 5) Buffered gate modulation input（BGMI）[14]： 320 × 256. The schematic of the buffered gate modulation input (BGMI) is shown in Fig. 7, and the BGMI structure is improved from GMI. The BGMI consists of a shared buffer as the input stage, unbalance current mirror Mn1 and Mn2, and row select switch M-sel. The shared-buffer technique provides a good bias control for the IR detector, whereas the unbalance current mirror has a large current gain due to the threshold voltage difference Mn1 and Mn2 caused by the intentional device channel length unbalance. Through the use of the threshold voltage, the strict requirement of low noise tunable dc source bias Vsource in the GMI and the inevitable FPN due to the threshold voltage process dependent variation can be avoided. The current gain AI,BGMI and injection efficiency η SBDI of the BGMI circuit can be expressed as. AI , BGMI =. g ΔI i = m,Mn 2 η SBDI = ΔI out g m ,Mn1. I K Mn2 ⋅ Mn2 = K Mn1 I Mn1. η SBDI =. ⎛ 1 K Mn2 ΔVT K Mn2 ⎜ + ⎜ K K Mn1 I Mn1 Mn1 ⎝. (1 + A) g m ,Mn1 RD 1 + (1 + A) g m ,Mn1 RD. ⎞ ⎟ ⎟ ⎠. (1.7). (1.8). The threshold voltage difference ΔVT is geometry dependent and thus is very stable. Unlike the GMI circuit, no strict source bias voltage control is required in the BGMI circuit. The current gain of BGMI circuit is immune to threshold non-uniformity and noise of the source bias voltage. It can also be adaptively controlled by different IR background input flux. This high front-stage current gain makes the downstream circuit and system noise contribution extremely low. It results in a low input referred noise. Moreover, BGMI circuit can operate with a larger integration capacitance compared to DI and BDI and still obtain low noise performance and high charge detection sensitivity.. 10.

(24) Fig. 7. The buffered gate modulation input (BGMI) readout circuit.. 6) Current mirroring integration (CMI) [15], [16]：. The schematic of the current mirroring integration (CTIA) is shown in Fig. 6. The detector current is copied very linearly and accurately to an off-pixel integration capacitor by the help of a current feedback structure implemented with a high-swing NMOS current and a PMOS current mirror. The current feedback structure forces the drain currents of MPl and MP2 to be similar, while the MN5 and MN6 pair copies the current to the outside of the cell when the pixel is selected by turning M-sel on. Since the integration capacitor can be placed outside of the pixels, its value can be selected as large as required for high charge storage capacity and high dynamic range. The CMI structure provides a stable bias voltage, and it can be expressed as ⎛K ⎞ Vdet ector = VDD − Vbias + ⎜ P ⋅ ΔVtp + ΔVtn ⎟ ⎝ Kn ⎠. 11. (1.9).

(25) The input impedance of the CMI can be expressed as ⎛ gmP1 gm N 4 ⎞ ⎟⎟ − 1 ⎜⎜ ⋅ gm gm N2 ⎠ Rin = ⎝ P 2 gmP1. (1.10). IR detector. RD. Vbias. CD. MP1. select. MP2. Iout. Vcas. MN1. MN2. MN3. MN4. OUT. M-sel. MP2. Rout. MN6 Pixel. Fig. 8. Structure of the Current Mirroring Integration circuit.. The CMI technique provides high injection efficiency, very low input impedance, and stable detector bias while occupying small area.. 1.3 Motivation. Infrared focal plane arrays have been developed for various applications, and the readout circuit is a very important interface in the infrared image system. Generally, infrared image system is very expensive, and has difficulties to obtainment because the high performance 12.

(26) readout circuit is commonly application to military. The readout circuit array is combined with the InGaAs IR detector array which developed by Chunghwa Telecom Lab to compose an IR image system. The detector array and the readout circuit array will be combined with the indium bond. In this thesis, this chip is first application to double delta sampling (DDS) for InGaAs IR detector array, and we increase variable circuit to change sampling time at choice for all situations. The DDS circuit is composed of column sampling circuit and output correlated double sampling circuit, and it can reduce fixed pattern noise, clock feedthrough noise, and reset noise, and this technique can efficiently increase resolution and output swing. In my work, the CDS stage is shared by all column sampling circuits, and this method has no disadvantage on column CDS circuits. The disadvantages of column CDS circuits generally have some offset variation of output voltage. The output signal with offset variation of CDS circuits generates a column-wise fixed pattern noise. Because a column-wise FPN is much more conspicuous than a random fixed pattern noise, it is hard to eliminate. In this chip, output CDS circuit is shared; it does not generate a column-wise fixed pattern noise. Using the proposed input stage, the readout performance in the high-resolution large-format IR FPA can also be improved.. 1.4 Thesis organization. In chapter 2, operational principles, architectures, circuit implementations, and simulation results of 32 x 32 and 320 x 256 IR FPA are described. In chapter 3, the circuit design and simulation of biochemical chip are presented. In chapter 4, measurement results of 32 x 32 readout chip and biochemical chip are presented. Finally, the conclusions and future works are given in chapter 5. 13.

(27) CHAPTER 2 ARCHITECTURE AND CIRCUIT DESIGN 2.1 Chip architecture. In the following, chip architectures of 32 x 32 IR FPA and 320 x 256 IR FPA are described below.. 2.1.1 The chip architecture of 32 x 32 IR FPA. The block diagram of the proposed 32 x 32 IR FPA is shown in Fig. 9. The integration capacitor is put in the column sampling circuit to perform off-pixel integration. The row decoder and row counter on the left side of cell array are used to generate the control signals for row switches. The column decoder and the column counter on the top side of cell array are used to generate the control signals for the column reset operation, column switches, double delta sampling (DDS) circuit, and row counter. Each column of the cell array has a column readout circuit to lower the leakage current in the column bus and the column sampling circuits to reduce the fixed pattern noise. The column readout circuit generates two analog output voltages. One is the signal proportional to the illuminative intensity of the 32 x 32 IR FPA whereas the other is the signal proportional to the reset voltage at the integration capacitor. The output CDS circuit is used to drive the external loads and perform the CDS operation. The image information is transformed as the photocurrent in the cell array by using the IR detector. The photocurrent is delivered to the column bus and converted into a voltage signal proportional to the illuminative intensity of image after the current integration outside the pixel. The photo-signal 14.

(28) and reset signal are used for the operation of the DDS.. Fig. 9. The block diagram of 32 x 32 IR FPA.. 2.1.2 The chip architecture of 320 x 256 IR FPA. The block diagram of 320 x 256 infrared focal plane arrays is shown in Fig. 10. There are three important parts of the analog circuits in this structure which are: the unit cell, column CDS stage and dynamic discharge output stage as the common output stage. There are four important parts of the digital circuits in the proposed structure which are: column counter, row counter, horizontal column decoder and vertical row decoder. Every unit cell will combine with the detector by an indium bond. The negative feedback amplifier is separated into two parts: half of the amplifier is shared by each row as the common left half and the other half is contained in every single pixel. By this arrangement the chip area and the power 15.

(29) dissipation will decrease. When the detector absorbs infrared flux, the photo-generate current flows into the current mirror in the unit cell. Then the mirrored and amplified current flows into the integration capacitance and transferred to voltage. The integrated signals from pixels in the same row are sampled to the CDS stages one row at one time controlled by the vertical row select logic. There are column CDS stage are shared by one column. The selected CDS signal is sampled to the common output stage column by column.. Fig. 10. The block diagram of 320 x 256 IR FPA.. 2.2 Circuit implementation. In the following, circuit implementation of 32 x 32 IR FPA and 320 x 256 IR FPA are described below. The 32 x 32 IR FPA is using delta double sampling technique to reduce fixed pattern noise and reset noise. Similarly, the 320 x 256 IR FPA is using correlated double sampling (CDS) technique to reduce fixed pattern noise. 16.

(30) 2.2.1 The circuit implementation of 32 x 32 IR FPA. The 32 x 32 IR FPA is composed of united cell stage and double delta double sampling (DDS) circuit. In the following, the united cell stage and delta double sampling circuit in this chip will be described in detail. The united-cell input stage of 32 x 32 IR FPA：. The conventional united-cell stage of SCI readout structure and the proposed unit-cell stage are shown in Fig. 11 (a) and (b) respectively. When the integration capacitance is shared by one column, we must decrease total parasitic capacitance for decreasing integration time and increasing operational speed. For this reason, the Mrow is placed between MC2 and MC4 because this placing can decrease total parasitic capacitance of integration node to 43%. The readout speed can be increased by replacing integration cap by smaller one under constant integrated current (Io). In the united-cell input stage of Fig. 11 (b), a single stage opa-amp and a cascode current mirror is used. As shown in Fig. 11, the single stage opa amp of input stage circuit formed by the MOS devices Mpu1, Mpu2, Mpu3, Mnu1, and Mnu2 in each pixel and the cascode current mirror circuit formed by the MOS devices MC1, MC2, MC3, and MC4 in each pixel. Due to the function of the differential amplifier, the detector bias at the anode of the IR detector can be stabilized to Vcom through the virtual ground and the input impedance of the input MOS device MG can be decreased to obtain high injection efficiency. The high injection efficiency, good detector bias stability, low noise, and good threshold uniformity can be achieved in the unit-cell input stage. The photo-current I1 signal flowing through MG of the input circuit is further mirrored to the next stage through the high-swing cascode current mirror MC1-MC4 as shown in Fig. 11 (b). The current mirror can improve the detection sensitivity and avoid the noise coupling effect to the input stage circuit. Moreover, as compared to the conventional cascode current mirror, the high-swing cascode current mirror 17.

(31) [18] increases output impedance and ratio accuracy while decreasing the required mirror output voltage to keep the output MOS devices in the saturation region. The current ratio of Io to I1 of the current mirror is determined by the dimension ratio of the MOS devices MC1 and MC2, which is very stable [19]. The current mode readout from united-cell to column readout circuit avoids the voltage swing in the highly capacitive column bus. The optimal gain of the current mirror can be determined for different input signal levels to achieve a maximum signal-to-noise ratio without integrating saturation on the capacitor. In the design, the current gain is 4. The amplified pixel current signal at the output of the current mirror is switched to the column sampling circuits through the MOS switch Mrow controlled by the row select clock Row. The injection efficiency of the united-cell stage at the low frequency can be expressed as. η LF =. (1 + A) ⋅ gmRD 1 + (1 + A) ⋅ gmRD. (2.1). The input impedance of united-cell stage can be expressed as Rin =. 1 gm × (1 + A). (2.2). VDD. VDD. VB1. Vcom. Mpu1. VB1. IR detector. Row. Mpu2 Mpu3 MG Mnu1. I1. Vcom. Mnrow Vcas. Mnu2. to next stage. Mprow MC3. MC4. Io Rowc. Mpu1. IR detector. Mpu2 Mpu3 MG Mnu1. I1. to next stage. Vcas. Mnu2 Io. Ctotal. MC3. Mrow MC1. Fig. 11. MC2. MC1. Ctotal. MC4 Row. MC2. The united-cell stage (a) conventional united-cell stage of SCI readout structure (b) proposed new united-cell stage. 18.

(32) To Calculate total integrated capacitor：Cox = 4.5 fF Conventional united-cell stage. New united-cell stage. C total ≅ 32 i (C SG ( M prow ) + C G D ( M n row ) ). C total ≅ 32 i C GD ( M C 4 ) = 32i(W iCox) = 32i(2i 4.5fF) = 288fF. ⎡ 1 ⎤ = 32i ⎢ 2i( W i LiCox + WiCox) ⎥ ⎣ 2 ⎦ ⎡ 1 ⎤ = 32i ⎢ 2i( 2i 0.35i 4.5fF + 2i 4.5fF)⎥ ⎣ 2 ⎦ = 667.8fF. The total parasitic capacitance decreases to 43% through using new united-cell stage. The simulation results of reset signal and integrated signal of conventional united-cell stage of SCI structure and new united-cell stage under integrated time = 72.5 us and photocurrent = 2.5 nA are shown in Fig. 12 (a) and (b) respectively. In Fig. 12 (a), the integrated voltage is 1.08V. In Fig. 12 (b), the integrated voltage is 2.41V. It can demonstrate that the new united-cell stage have smaller total parasitic capacitance under the same integration time.. Reset. Reset. Vint = 2.41. Vint = 1.08. Fig. 12. The simulation results of the reset signal and integrated signal (a) conventional united-cell stage of SCI structure (b) new united-cell stage. 19.

(33) Double Delta Double Sampling (DDS) Operation circuit Due to the process non-uniformities, the differences between the threshold voltages of transistors of analog buffer cause a column FPN. To compensate this column FPN, the readout chain contains a circuit named double delta sampling (DDS) [20], [21], [22]. The typical DDS circuit is shown in Fig. 13.. Column bus VDD Mreset Reset. Analog buffer1. SHR. Pixel buffer. Cref. DDS Cint. Analog buffer2. SHS Csig. Fig. 13 Typical double delta sampling circuit.. The signal and reset levels are sampled to sample-and-hold capacitors Cref and Csig respectively. The difference between Vout_R and Vout_S is equal to Vref–Vsig + Δ 1. Then, the DDS switch is activated and capacitors Cref and Csig are short-circuited. At this time, the difference between Vout_R and Vout_S is equal to Δ 2 directly. By the subtracting this reference level from the previous reading, the offset due to threshold voltage variations is removed ( Δ = Δ 1– Δ 2). The timing of DDS process is shown in Fig. 14. The output voltage ΔVo can be expressed ΔVo( n + 1) = [Vout _ R( n) − Vout _ S (n)] − [Vout _ R(n + 1) − Vout _ S (n + 1)] = (Vref − Vsig ) + (Δ1 − Δ2). if. Δ1 = Δ 2. ⇒. (2.3) (2.4). ΔVo(n + 1) = Vref − Vsig. (2.5) 20.

(34) Δ1. Δ2. Fig. 14 The timing of typical double delta sampling circuit. The DDS operation circuit in my work is shown in Fig. 15. The DDS is composed of column sampling circuit and output correlated double sampling circuit. The column sampling circuit is used in each column whereas the output CDS circuit is shared by all columns sampling circuit.. Fig. 15 The improved DDS circuit. 21.

(35) In the column sampling circuit as shown in Fig. 15, the devices of Ms_n, MR_n, Ms_p, and MR_p controlled by the signals of SHS, SHR, ZSHS, ZSHR, respectively, are sampling switches whereas Mvce_N and Mvce_P controlled by Vce and ZVce are the equalization switch. The signals generated by the integration of photocurrent and the reset signal transferred through the source follower are sampled by the devices of Ms_n, Ms_p, and MR_n, MR_p respectively. The double delta sampling circuit is used to remove offsets due to the column source follower, and hence reduces column-to-column fixed pattern noise. Both the effects of clock feedthrough and channel charge injection resulted from the sampling operation of MS and MR in the original DDS circuit will degrade the performance of signal readout. In the improved DDS circuit of Fig. 15, the effect of signal-dependent channel charge injection caused by Ms_n, MR_n, Ms_p, and MR_p during the falling edges of SHS, ZSHS, SHR, and ZSHR is reduced by the dummy switch Mds_n, Mds_p, MdR_n, and MdR_p with their drain and source connected together. The dummy switch size of Mds_n, Mds_p, MdR_n, and MdR_p is designed to be about one half of the size of Ms_n, MR_n, Ms_p, and MR_p, respectively. The signals after the sampling are held at the nodes of VS and VR until they are readout to the output CDS circuit when the column switches Mscol and MRcol are on. Since the column readout sampling is performed simultaneously in each column and the sampled column signals are readout to the output CDS circuit successively, the signal from the last column is held for the longest time that is almost equal to the integration time. The held signal voltages at the last column will be decreased by the leakage currents at the nodes of VS and VR. An extra capacitor of 250fF is added to the nodes of VS and VR to decrease the effect of leakage current. The extra capacitor of 250fF is determined by the leakage current Ileak =0.4p/um at the nodes of VS and VR, the gain G. PGA. = 2 of the programmable gain amplifier. (PGA), the total capacitances (Ctotal) at the nodes of VS and VR, and the integration time Tint. 22.

(36) The equation can be represented as Ctotal．V1LSB = G. PGA. ．(Ileak．Tint). (2.6). The clamp signal in the output CDS circuit is then turned on to clamp the gate voltages of MSF8 and MSF10 to Vb3. Then, Mscol and MRcol are on to transfer the signal from the column sampling circuit to the output CDS circuit. Finally, Mn7, Mn8, Mvce_N, and Mvce_P are on, the voltage at both nodes of VS and VR of becomes. VS + VR . If no loss in the stored 2. charges of the capacitor, then the voltage change at the capacitors of CS2 and CR2 are transferred to the output node of the output source follower composed of MSF7 and MSF8 (MSF9 and MSF10) as shown in Fig. 15. Thus we have Vout _ S =. ΔV 1 + Vb3 + Vnoise + (VSG ( MSF 4, Vce ) − VSG ( MSF 4, Vclamp )) + VSG ( MSF 8) 2 2. Vout _ R = −. ΔV 1 + Vb3 + Vnoise + (VSG ( MSF 6, Vce ) − VSG ( MSF 6, Vclamp )) + VSG ( MSF 10) 2 2. (2.7). (2.8). Vout _ S − Vout _ R = ΔV + ⎡⎣(VSG ( MSF 4, Vce) − VSG ( MSF 4, Vclamp ) ) + (VSG ( MSF 6, Vce ) − VSG ( MSF 6, Vclamp ) ) ⎤⎦. + (VSG ( MSF 10) − VSG ( MSF 8) ). (2.9). where Vnoise is the effect of clock feedthrough on the node of VS and VR of Fig. 15 when the MOSFET of Mvce_N and Mvce_P are on, the VSG ( MSF 4, Vce ) and VSG ( MSF 6, Vce ) are under the condition that the Vce is high. The VSG ( MSF 4, Vclamp ) and VSG ( MSF 6, Vclamp ) are under the condition that the Vclamp is high. The variation of threshold voltage can be reduced by DDS circuit, but VSG ( MSF 4, Vce ) and VSG ( MSF 4, Vclamp ) can not cancel each other perfectly due to the body effect, so as VSG ( MSF 6, Vce ) and VSG ( MSF 6, Vclamp ) . As may be seen from (2.7) and (2.8), the CDS operation is realized in the output CDS circuit. In the equation (2.9), the two output signals are sent out and subtracted each other by the subtraction circuit in the off-chip data acquisition (DAQ) card. 23.

(37) 2.2.2 The circuit implementation of 320 x 256 IR FPA. The 320 x 256 IR FPA is composed of united cell stage, column CDS stage, and dynamic discharge output stage. In the following, the united cell stage, column CDS stage, and dynamic discharge output stage in this chip will be described in detail. The united-cell input stage of 320 x 256 IR FPA：. In the input stage, a single stage opa-amp and a cascode current mirror is used. The Fig. 16 shows the unit cell combines with the common left half circuit. As shown in Fig. 16, the share-buffered direct-injection (SBDI) input circuit formed by the MOS devices Mpu1, Mpu2, and Mnul in each pixel and the common left half circuit formed by the MOS devices Mps1, Mps2, and Mns1 and shared by all the pixels in one column. In the shared common left half circuit, three common output bias lines Vb1, commonS, and commonG are connected to the SBDI input circuits of all the pixels in the same column. The total power dissipation of the unit-cell input stage can be kept small because the bias current of the SBDI input circuit in each pixel is low, and the chip area can be kept small. Vsub. VDD. Vb1. Mps1. Vb1. IR detector. Mpu1. commonS. Vcom. Mps2. Vtest. VDD VDD Mptest. Mpu2. Vreset. Mpreset. Mncds1. MG I2 Mns1. commonG. R-Selp. Vcas Vcas2. Common left half circuit. Mprsel To the column CDS stage Mnrsel. Mnu1 Sample1 Vcas3. MCL8. MCL2 MCL4. MCL6. MCL7. MCL1 MCL3. MCL5. Io. R-Seln Cint. Unit-cell input stage Fig. 16 The united-cell stage of 320 x 256 IR FPA. 24.

(38) The amplifier is connected as negative feedback type, and the detector bias at the anode of the IR detector can be stabilized to Vcom and adjusted by adjusting Vcom through the virtual ground. The input impedance of the input device MG can be decreased to obtain high injection efficiency. The photo-current I2 signal flowing through MG of the input circuit is further mirrored to the next stage through the high-swing cascode current mirror with variable current gain (MCL1-MC8) as shown in Fig. 16. In normal case (Vcas = Vcas2 = 0.8V, Vcas3 = 0V), the current gain is 6. If the readout circuit is operated in weak current (below 500p), the devices of MCL5 and MCL6 can increase the current gain from 6 to 60 through controlling bias Vcas2 and Vcas3 to turning on MCL5 MCL6 and turning off MCL7 MCL8 (Vcas = Vcas3 = 0.8V, Vcas2 = 0V). The amplified pixel current signal at the output of the current mirror is switched to the column sampling circuits through the MOS switch Mprsel and Mnrsel controlled by the row select clocks R-selp and R-seln respectively. The injection efficiency and input impedance are the same in equation (2.1) and (2.2). The integration capacitance is chosen small to increase the readout speed. The detailed device sizes of the unit cell are list in Table I. Device. W/L (um/um). Mpu1 Mps1. 0.5/2.5. M=1. Mpu2 Mps2. 0.5/0.7. M=1. Mnu1 Mus1. 1/1.8. M=1. 1/1. M=1. MCL1 MCL2. 0.5/0.4. M=1. MCL3 MCL4. 3/0.4. M=3. MCL5 MCL6. 3/0.4. M=7. MCL7 MCL8. 0.5/0.4. M=2. Mpreset. 0.5/0.4. M=1. Mncds1. 2.5/0.35 M=6. Mnrsel. 1/0.35. Mprsel. 1.5/0.35 M=1. Cint. 10fF. MG. Table I. M=1. The device parameters of the unit cell. 25.

(39) The column CDS stage of 320 x 256 IR FPA：. In the correlated double sample (CDS) stage, as shown in Fig. 17, the NMOS Mncds2 with the dc gate bias Vbn is the NMOS current source load of the source follower Mncds1 when the row switch is ON. The correlated double sampling (CDS) function is realized by the row switch Mnrsel and Mprsel, the clamp device Mnclp, and the AC coupling capacitor Ccds. The PMOS devices Mpcds1 and Mpcds2 form a P-type source follower, and the Mpcds1 of Nth column is turn on when Nth column is selected. By this arrangement the power dissipation can be reduced substantially.. Fig. 17. The column CDS stage of 320 x 256 IR FPA.. The correlated double sampling (CDS) was introduced by White [24] as a signal processing technique for removal of switching transients and elimination of the Nyquist (reset) noise, both of which are associated with charge sensing circuits. An additional advantage is the attenuation of the 1/f noise and KTC noise components in the charge sensing circuits due to the zero in the CDS noise transfer function at the origin (w = 0). The effect of the CDS circuit on the reset noise and Johnson-Nyquist (white) noise in the associated circuitry has been adequately described [24]. The purpose of this correspondence is to present an analysis of the effect of the CDS circuit on the 1/f noise component generated in the preceding 26.

(40) circuitry. The reset noise on this node having a mean square value is given by kT/Co. Following reset and prior to charge transfer the clamp switch is closed briefly which causes the amplified reset noise to be stored on Ccds. Following charge transfer the sample switch is closed, resulting in an output voltage proportional to the difference in input levels at clamp and sample times. Assuming that all time constants associated with the switches are negligible compared to the sampling interval, the reset noise is fully correlated between clamp and sample and is therefore eliminated. In addition, Ccds is subject to reset noise from the clamp and sample switches and must be sufficiently large to avoid introducing additional noise components [25]. The CDS function of the column CDS stage is described below. At time T1 , the row switch is on and the clamping clock Vclamp is high and the clamp device Mnclp is on. The first sampled voltage signal is charged on the coupling capacitor Ccds and the voltages of Vcds1 and Vcds2 at time T1 can be expressed. Vcds1(T1 ) = VDD − Vint − VGSN (T1 ). (2.10). Vcds 2(T1 ) = 0. (2.11). where Vint is the integrated voltage signal on the capacitor and VGSN (T1 ) is the voltage drop of the N-type source follower composed of the devices Mncds1 and Mncds2 at the time T1 . At time T2 , the clamp device Mnclp is turned off before the internal integration capacitor is reset. Then the integrated node is reset to VDD and the second sampled voltage Vcds1 (T2) becomes Vcds1(T2 ) = VDD − VGSN (T2 ). (2.12). where VGSN (T2 ) is the voltage drop of the N-type source follower composed of the devices Mncds1 and Mncds2 at the time T2 . Since the charges on the coupling capacitor Ccds is the same at T1 and T2. From equation 27.

(41) (2.10), (2.11) and (2.12), we have Ccds[Vcds1(T1 ) − Vcds 2(T1 )] = Ccds[Vcds1(T2 ) − Vcds 2(T2 )]. (2.13). Thus, the output signal Vcds2 (T2) after the CDS is. (. Vcds 2(T2 ) = Vint − VGSN (T2 ) − VGSN (T1 ). ). (2.14). The net voltage Vcds2 (T2) is sent to P-type source follower of next stage, and the CDS function is realized. Each column CDS stage is shared by 256 unit cells, by applying CDS function the threshold variation between all the Mncds1 in every unit cell to improve the linearity.. The dynamic output stage of 320 x 256 IR FPA：. The dynamic discharge output stage is shown in Fig. 18. In the output buffer Mnout1 and Mnout2, the Mpcds1 is shared by all the column, the dynamic discharge device Mndyn is used to save the static power dissipation and maintain the proper readout speed. The NMOS Mdyn is controlled by Vclamp. During the readout period, Vclamp is low, and Mndyn is turned off to save the power dissipation. If the Mndyn is turned on by Vclamp, the output signal is pulled down, and finally readout speed can be increased.. Fig. 18. The dynamic output stage of 320 x 256 IR FPA. 28.

(42) 2.3 Chip operational principle. In the following, the chip operations of 32 x 32 and 320 x 256 IR FPA are described.. 2.3.1 The chip operation of 32 x 32 IR FPA. The detailed circuit involving united-cell input stage, column sampling circuit, and output CDS circuit is shown in Fig. 19. The column sampling circuit is shared by one column, and the output CDS circuit is shared by all column sampling circuits. VDD VDD. SHS Col VDD. VDD. VDD. Ms_n. Ms_p VB1. Mps1. IR Vreset. Is Vcom. Mps2. MSF8. VS. Mds_p. MSF4 CS1 Mn7 Vclamp. MSF1 Vce Io MC3. Row. MC1. MC2. Mn8. Mvce_P. Col. MSF2. Cint. MR_n MdR_n. Sel_C. MR_p MdR_p. VDD. VDD. SHR Vbn1. MC4. Vb3. ZVce. Mvce_N. Vcas. MSF7. CS2 Mds_n. ZSHS. Mpu2. Mns2. Vbp2 MSF3. Mreset. Mnu1 Mns1. Vbp. Vbp2 Vbp. MSF9. MSF5 CR2. VR. MSF6. MSF10. CR1. ZSHR. Fig. 19 The detailed circuit involving united-cell stage, column sampling circuit, and output CDS circuit.. The image information is transformed as the photocurrent in the cell array by using the IR detector. The photocurrent is delivered to the column bus and converted into a voltage signal proportional to the intensity of image after the current integration outside the pixel. The 29.

(43) photo-signal and reset signal are used for the operation of the double delta sampling (DDS). The two signals generated in the output CDS circuit are delivered to the programmable gain amplifier (PGA), A/D converter, and display system outside the chip to generate the raw image. The major operational timing diagram is shown in Fig. 20. Firstly, the row select signal Row1 is high and the Reset control signal is low to reset the voltage at the integrating capacitor to 3.3V. After the reset operation, the photocurrents of all pixels in the Row1 are integrated at the gate of MSF1 of Fig. 19 during the integration time. Then the control signal of SHS and ZSHS are on to sample the photo-signal in the output of the first source follower MSF1/MSF2 to the node VS. After that, the Reset control signal is on again and then the control signal of SHR and ZSHR are on to sample the reset signal in the output of the first source follower to the node VR when the Reset control signal is off. This reset signal must be sampled after the Mreset is off because the effect of clock feedthrough on VS and VR from the Reset control signal is the same. Those noises can be reduced by the CDS operation. The duration of reset time is kept long enough to eliminate the amount of residual charges due to incomplete reset. The integration time Tint and frame rate are expressed as Tint = N．TDT = 2 ⋅ N ⋅ Frame rate =. 1 f clock. f clock 1 = M ⋅ N ⋅ TDT 2 ⋅ M ⋅ N. (2.15) (2.16). where M, N, TDT, and f clock are row number of imager, column number of imager, output data rate, and system clock, respectively. This chip involving controlling logic which can switch signals SHS and ZSHS that are inputted from internal or external of the chip is used for adjusting integration time. The purpose of adjusting integration time is that when this chip is used in space, it would have wider adjusting range and wide application. 30.

(44) Fig. 20 The timing major diagram of the 32 x 32 IR FPA.. 2.3.2 The chip operation of 320 x 256 IR FPA. The detailed circuit involving common left half circuit, united-cell input stage, column CDS stage, and Dynamic output stage is shown in Fig. 21. The major operational timing diagram is shown in Fig. 22. The clock timing waveforms of the start of frame, row select clock, and column select clock and clamping control Vclamp are shown in Fig. 22 where the clock signal has a high level of 3.3V and a low level of 0V. The readout operation is described below. When the start of frame signal is on, the first row is selected and the first column select column 1 is on, the integration voltages of the unit cell input stages of the first row are switched to the CDS stages. The integration time = 6.4us is based on 64 by 64 IR FPA, and it is controlled by the reset signal.. 31.

(45) Fig. 21 The detailed circuit of 320 x 256 readout chip.. After an integration time Tint controlled by the column reset signal, the first column select signal column 1 is high again and the voltage signal of the first column in the first row is sampled to the output stage. The integration capacitor is reset immediately after it is sampled. Then the second pixel of the first row is read out serially. After all pixels in the first row have been readout, the second row select Row 2 is high and then the second row is switched to the integration capacitor. When the Row 256 is selected, the row select signal is invited to form the end-of-frame signal which indicates the first frame has been readout. Then the second frame is readout. The integration time Tint and frame rate are expressed as Frame rate = =. f clock 4⋅M ⋅ N. (2.17). where M, N, and f clock are row number of imager, column number of imager, and the system clock, respectively.. 32.

(46) Fig. 22 The timing major diagram of the 320 x 256 IR FPA.. 2.4 Simulation results. In this thesis, the 32 x 32 and 320 x 256 readout circuit array will be combined with the InGaAs IR detector array which developed by Chunghwa Telecom Lab to compose a complete IR image system. The property of the detector array is illustrated below. Fig. 23 shows the responsitivity of InGaAs detector, and the standard version with high efficiency is 900nm to 1700nm wavelength range. This detector is applied in the near-infrared (NIR) regime, and the uncooled operation is one of its remarkable features. In Fig. 24, it is shown that when the detector is biased at -3V, -1V, and 0V, the photo excited current is very stable and the detector shunt resistance is very large. The dark current measurement of InGaAs 33.

(47) detector array is shown in Fig. 25, and it shows that dark current of InGaAs detector approximates 11.5pA ~ 14.6pA under bias 0V ~ -1V. This dark current is higher than 0.5pA expected by Chunghwa Telecom laboratory. It can demonstrate that they underestimate the dark current of InGaAs detector. The chip photo of the detector is shown in Fig. 26.. Fig. 23 The responsitivity of the InGaAs detector developed by Chunghwa Telecom laboratory.. Fig. 24 The characteristic of the InGaAs detector array developed by Chunghwa Telecom laboratory. 34.

(48) 3.00E-011. 2.00E-011. 2.00E-011. 1.00E-011. 1.00E-011. 0.00E+000. 0.00E+000. -1.00E-011. -1.00E-011. Dark Current (A). 3.00E-011. -2.00E-011. InGaAs detector -5. Fig. 25. -4. -3. -2. -1. -2.00E-011. 0. Bias (volt) Measurement of dark current of InGaAs detector array developed by. Chunghwa Telecom laboratory.. Fig. 26 The chip photo of the InGaAs detector developed by Chunghwa Telecom laboratory.. In the following, the simulation results and layout description of 32 x 32 and 320 x 256 readout circuits are described.. 2.4.1 Simulation results of 32 x 32 IR FPA. The simulation results of the voltage difference between Vout_S and Vout_R of the output CDS circuit with input photocurrent 5pA to 105pA and 100pA to 5000pA are shown in 35.

(49) Fig. 27 and Fig. 29, respectively. In Fig. 27, the integration time is 73 us, the integration capacitor is 320 fF, and the input current signals are 5pA, 15pA, 25pA, 35pA, 45pA, 55pA, 65pA, 75pA, 85pA, 95pA, and 105pA. In Fig. 29, the input current signals are 100pA, 450nA, 800pA, 1150pA, 1500pA, 1850pA, 2200pA, 2550pA, 2900pA, 3250pA, 3600pA, 3950pA, 4300pA, 4650pA, and 5000pA. The normal integration capacitance (320 fF) is total parasitic capacitor at integration node (Vint). An extra capacitor of 320 fF with a MOS switch conveniently lay along vertical direction and in parallel with the 320 fF normal integration capacitor. The integration time is variable through off-chip controlled signal. The optional capacitor is used to prevent saturation when the incident light is strong and the integration time is long such as the application of still imager in the environment of strong light. The equalization of both photo-signal path and reset signal path controlled by Vce is performed after the readout of the held voltage. The equalized voltage at the two nodes of A and B is then readout to the output CDS circuit. In the output CDS circuit, the NMOS devices Mn7 and Mn8 controlled by the signal Vclamp is to clamp the voltage at the gate of MSF8 and MSF10 in the output source follower MSF7 and MSF8 (MSF9 and MSF10) to Vb3. The capacitor of 1.5 pF is used to perform the operation of correlated double sampling (CDS). In this work, the device parameters of 0.35 um 2P4M N-well CMOS technology is used for SPICE simulation. In order to observe the process variation affects the linearity, the linearity of different corners is shown in Fig. 28 and Fig. 30. As may be seen from these figures, the linearity of the readout circuit is greater than 99% and the output swing is equal to 1.26 V. The series output voltage difference Vout_S and Vout_R of 32 cells is shown in Fig. 31, and it is verified full chip functional correctness for input photo current from 40pA to 5000pA with 160pA step. The cell array mask of 32 x 32 IR FPA is design by Chunghwa Telecom Lab using OrCAD tool, and it is shown in Fig. 32. An experimental 32 x 32 readout chip has been designed and fabricated to combine with the InGaAs IR detector array. The summary of specification of the 32 x 32 readout chip is listed in Table II. 36.

(50) 105 pA 95 pA 85 pA 75 pA 65 pA 55 pA 45 pA 35 pA 25 pA 15 pA 5 pA. Fig. 27 The voltage difference between Vout_S and Vout_R of Fig. 19 for the input photocurrent from 5p to 105p with 10pA step.. Fig. 28 The linearity of the voltage difference between Vout_S and Vout_R for input photocurrent 5pA to 105pA with 10pA step. 37.

(51) 5000 pA 4650 pA 4300 pA 3950 pA 3600 pA 3250 pA 2900 pA 2550 pA 2200 pA 1850 pA 1500 pA 1150 pA 800 pA 450 pA 100 pA. Fig. 29 The voltage difference between Vout_S and Vout_R of Fig. 19 for the input photocurrent from 100p to 5000p with 350pA step.. Fig. 30 The linearity of the voltage difference between Vout_S and Vout_R for input photocurrent 100pA to 5000pA with 350pA step. 38.

(52) The voltage difference between Vout_S and Vout_R (volts). Time (sec). Fig. 31 The series output voltage difference between Vout_S and Vout_R of 32 cells for input photocurrent 40pA to 5000pA with 160pA step.. Fig. 32. The cell array masks of 32 x 32 IR FPA. 39.

(53) Table II. The summary of specification of the 32 x 32 readout chip.. Technology. TSMC 0.35 um 2P4M CMOS. Array Size. 32 x 32. Pixel Pitch. 30 um x 30 um. Integration Capacitance. 320 fF + 320 fF. Integration Time. 72.5 us. Operational Current Range. 5pA ～ 5nA. Output Swing. 1.26 V. Maximum Charge Capacity. 9.2×106 e－. Transimpedance. 5.04×108 ohms. Chip Area. 2500um X 2461 um. Power. 16.8 mW. Linearity. 99 %. Nonlinearity. < 1.8% (for 10% ~90% full swing). Maximum Readout Speed. 0.8 M Hz. Maximum Frame Rate. 714 frame/sec. 40.

(54) 2.4.2 Simulation results of 320 x 256 IR FPA. The simulation results of output voltage Vout in the dynamic output stage for input photocurrent 0pA to 500pA and 100pA to 5000pA in Fig. 18 are shown in Fig. 33 and Fig. 35, respectively. In Fig. 33, the integration time is 73 us, the integration capacitor is 10fF, and the input current signals are 0pA, 50pA, 100pA, 150pA, 200pA, 250pA, 300pA, 350pA, 400pA, 450pA, and 5000pA. In Fig. 29, the input current signals are 0pA, 500pA, 1000pA, 1500pA, 2000pA, 2500pA, 3000pA, 3500pA, 4000pA, 4500pA, and 5000pA. The linearity of different corners is shown in Fig. 34 and Fig. 36. The linearity of the readout circuit is greater than 99%, and the maximum output swing is equal to 1.5 V. When Vclamp is high during Tpixel, Vout is clamped to 0.3V. When Vreset is low during Tpixel, the integration node Vint is reset to 3.3V. These two operations realize both clamping and dynamic discharging functions. The readout speed is defined as the reciprocal of the pixel processing time (1/Tpixel), and the simulation readout speed can reach 10MHz. The total chip size is 11500 μm x 8650 μm, and will combined with the InGaAs detector array which developed by Chunghwa Telecom Lab to complete the entire IR image system. The series output voltage (Vout) of 32 cells is shown in Fig. 37, and it is verified full chip functional correctness for input photo current from 40pA to 5000pA with 160pA step. The summary of specification of the 320 x 256 readout chip is listed in Table III.. 41.

(55) 500 pA 450 pA 400 pA 350 pA 300 pA 250 pA 200 pA 150 pA 100 pA 50 pA 0 pA. Fig. 33 The simulated waveforms of output voltage Vout in the dynamic output stage for the input photocurrent from 0pA to 500pA with 50pA step.. Fig. 34 The linearity of output voltage Vout in the dynamic output stage for the input photocurrent from 0pA to 500pA with 50pA step. 42.

(56) 5000 pA 4500 pA 4000 pA 3500 pA 3000 pA 2500 pA 2000 pA 1500 pA 1000 pA 500 pA 0 pA. Fig. 35 The simulated waveforms of output voltage Vout in the dynamic output stage for the input photocurrent from 0p to 5000pA with 500pA step.. Fig. 36 The linearity of output voltage Vout in the dynamic output stage for the input photocurrent from 0pA to 5000pA with 500pA step. 43.

(57) Fig. 37 The series output voltage (Vout) of 32 cells for input photocurrent 40pA to 5000pA with 160pA step.. Fig. 38 The layout of 320 x 256 readout chip. 44.

(58) Table III The summary of specification of the 320 x 256 readout chip. Technology. TSMC 0.35 um 2P4M CMOS. Array Size. 320 x 256. Pixel Pitch. 30 um x 30 um. Integration Capacitance. 10 fF. Integration Time. 6.4 us. Current Range. 5pA ～ 5nA. Output Swing. 0.9 V. Maximum Charge Capacity. 1.125×105 e－. Transimpedance. 1.8×108 ohms. Chip Area. 10500um × 8650 um. Power. 103.7 mW. Linearity. 99 %. Nonlinearity. < 5% (for 10% ~ 90% full swing). Maximum Readout Speed. 10 M Hz. Frame Rate. 61 frame/sec. 45.

(59) CHAPTER 3 CMOS READOUT CIRCUIT APPLICATION TO BIOCHEMISTRY 3.1 Background. Rapid advancement in modern biology has produced opportunities and needs in clinical diagnostics and many other biorelated measurements. To develop a high-throughput instrument with small size, low cost, ease of use, and high accuracy is becoming more and more important. Development of a suitable sensor for a variety of biochemical reactions is the key for this progress [26]. The small size of semiconductor sensors not only contributes to their potentially low cost, but also allows them to be integrated with microelectronic circuit, creating the so called integrated sensors, further enhancing their performance [27]. The photo-multiplier tube (PMT) is the most common light sensor used in these spectrophotometers. PMT is an effective and sensitive light sensor, wherein one photon can induce approximately electrons in the photomultiplier tube. However, the need for high voltage (about 500 to 1000 V), the size, and the price of the PMT limit its application in a variety other fields such as personalized diagnosis kits. The complementary metal oxide semiconductor (CMOS) process is the most commonly used procedure in semiconductor industry. A photodiode is basically a p-n junction operated under reverse bias. Free electron-hole pairs will be generated in photodiode when photodiode is illuminated by the photon, which contains energy higher than the band gap of photodiode [28]. CMOS photodiodes act as semiconductor light sensor with the advantages of low price, small size, and low power consumption as compares to that of PMT. These features make CMOS photodiodes easy to be a personalized healthy care instrument. 46.

(60) We demonstrated a reaction that can be used as the platform light emitting reaction to permit enzymatic activity to be observed. 2H2O2 + luminol. Peroxidase. 3-aminophthalate + N2 + Light (425nm). NH2 O. NH2 COOH. NH NH. Detection by photodiode. COOH. O which shows the light emitting reaction catalyzed by horseradish peroxidase (HRP). Since many enzymes produce (Table IV), the HRP-luminol-system should be a good platform reaction to couple and detect many other enzymatic reactions by luminescence. In a CMOS photodiode system, the chemiluminescence generated from the biochemical reaction produces current flow that corresponds to the rate of enzymatic-catalyzed reaction. Table IV Important biochemicals that can be determined by HRP-luminol-H2O2 system. H2O2 producing reactions. Target. Glucose. Glucose + O2 + 2H2O. Uric acid. Uric acid + O2 + 2H2O. Cholesterol Lactate. Phospholipid Triglycerides Lipase. Cholesterol + O 2. Glucose Oxidase Uricase. Gluconic acid + 2H2O2. allantoin + CO2 + 2H2O2. Cholesterol oxidase. L-La c ta te + O 2 Phospholipids + H 2 O. cholesten-3-one + H2O 2. La c tate o x id ase. p yru vate + H 2 O 2. Phospholipase. Fatty acids + Choline. Choline oxidase. Choline + H 2 O + 2O 2. Lipase T riglycerides + 3H 2 O Glycerol oxidase Glycerol + O 2 47. betaine + 2H 2 O 2. Fatty acids + glycerol glyceraldehyde + H 2 O 2.

(61) 3.2 Circuit implementation A novel of luminescent measurement chip is designed in 0.35um technology. As shown in Fig. 39, the chip is composed of 128 by 128 photodiodes and a current readout circuit. The concentration of H2O2 is proportional to liberated luminescence. The chemiluminescence signal is absorbed by photodiode, and the photodiode generates the signal current. The signal current injects into readout circuit, and it is converted to the voltage. The signal current (Isignal) injects into readout circuit and this current flowing through MG is mirrored to integration capacitance (Cint) through the high-swing cascode current mirror M5-M8. The discharge voltage of integration capacitance is proportional to signal current, and the discharge voltage is transferred to Vout through CDS circuit. In other words, the current readout circuit can convert different signal current to linearity output voltage (Vout).. Fig. 39. The readout circuit for detection chemiluminescence.. 48.