Design and Anaylsis of A 2.5-Gbps Optical
Receiver Analog Front-End in a 0.35-
m Digital
CMOS Technology
Wei-Zen Chen, Member, IEEE and Chao-Hsin Lu
Abstract—This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabri-cated in a low-cost 0.35- m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed opera-tions in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 Arms. The input sensitivity of the receiver front-end is 16 A for 2.5-Gbps operation with bit-error rate less than10 12, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is1650 m 1500 m.
Index Terms—Active inductor, limiting amplifier (LA), tran-simpedance amplifier (TIA).
I. INTRODUCTION
F
IBER-OPTICAL networks have become a main stream for long haul and ultra high-speed data communications. The growing demands in broad-band access to internet, such as fiber to the home (FTTH), have motivated marvelous explorations of high performance optical transceivers recently [1]–[10]. This paper presents the design of a 2.5-Gbps optical receiver analog front-end (AFE) circuits in a low-cost 0.35- m digital CMOS process [1]. With the progress of CMOS photo detector (PD) technology, integrating photo detector, transimpedance ampli-fier (TIA), and limiting ampliampli-fier (LA) on a single chip provides the feasibility of system integration in the future [9].The architecture of the optical receiver AFE is shown in Fig. 1. The incoming nonreturn to zero (NRZ) optical signal is converted to a photo current by an external photo detector, and regenerated to a voltage signal suitable for clock-and-data recovery (CDR) by a TIA and an LA. Conventionally, the TIA converts the tiny photo current generated from a photo detector to a voltage signal of tens to hundreds millivolts, and couples it to a LA in the other package for post amplification. Since the Manuscript received December 20, 2004; revised April 28, 2005 and September 6, 2005. This work was supported by the National Science Foun-dation under Contract NSC-93-2220-E009-004, 93-EC-17-A-07-S1-001, by ITRI/STC, and by MediaTek Inc. This paper was recommended by Associate Editor K. Pedrotti.
W.-Z. Chen is with the Department of Electronics Engineering and Innovative Package Research Center (IPRC), National Chiao-Tung University, Hsin-Chu 300, Taiwan, R.O.C. (e-mail: wzchen@mail.nctu.edu.tw).
C.-H. Lu is now with Mediatek Inc., Hsin-Chu 300, Taiwan, R.O.C. Digital Object Identifier 10.1109/TCSI.2005.862068
TIA’s output signal is still small, off-chip voltage coupling is susceptible to noise disturbance.
In this design, both the TIA and the LA are integrated in a single chip. Thus, TIA’s output can be on chip dc-coupled to the LA, and no external coupling capacitor is required to min-imize noise interference. Furthermore, data jitter induced by low cutoff frequency in ac-coupled scheme can be alleviated. For on-chip dc-coupling, an automatic dc level control circuit (ADC) is incorporated as TIA’s output stage to adjust its output dc level to that of the post-LA’s input dc level.
This paper is organized as follows. Section II describes the de-sign of the TIA in the receiver. Several bandwidth enhancement techniques for CMOS TIA’s have been utilized. Its noise perfor-mance is also analyzed and discussed. The design of LA is in-troduced in Section III. The LA is basically a cascaded amplifier chain. The gain-bandwidth performance and power optimization are investigated in detail. Section IV describes the experimental results. And finally, conclusions are drawn in Section V.
II. TRANSIMPEDANCEAMPLIFIER
For CMOS TIAs, the primary factors that constrain signal bandwidth and noise performance are the inherent parasitic ca-pacitance introduced by the photo detector and the bonding pad. Therefore, in a conventional common source TIA architecture, its signal bandwidth has to be severely compromised with con-version gain and noise performance [2]. In this design, a low input impedance TIA using regulated cascode input stage [3] with shunt-feedback configuration is utilized [4]. Fig. 2 depicts the circuit schematic of the TIA. The input impedance of the TIA is greatly reduced by the local feedback amplifier
and shunt-feedback. This prevents the input pole from dominating signal bandwidth, and the gain degradation caused by the input shunting capacitance can be avoided.
To further enhance signal bandwidth, inductive loads at each gain stage are also utilized to partially trim out the parasitic ca-pacitance at the drain of and [4], [5]. Compared to using resistive loads, signal bandwidth is improved by 80% without gain peaking according to experimental results [4]. In this de-sign, active inductors are employed instead of passive spiral in-ductors for the latter ones are in general bulky and contribute significant parasitic capacitance. The active inductors are made up of an nMOS and a resistor, and are configured as , , and . The nMOS is operated in the sat-uration region, and the resistor is implemented using a pMOS operated in the triode region. Let and be the parasitic 1057-7122/$20.00 © 2006 IEEE
978 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 4, APRIL 2006
Fig. 1. Optical receiver AFE architecture.
Fig. 2. TIA circuit schematic.
capacitance of , , , , , and , be the loading capacitance at the source node of , , and , be the transconductance of , , , and be the turn on resistance of , , and . The input impedance looking into the active inductor can be expressed as , where (1), shown at the bottom of the page, is true, and
(2) (3) (4) , 8, 11 and , 9, 12.
The additional zero is introduced by the gate resistor . For to behave as an inductor, i.e., , it is required that
(5)
Under this condition, the active loads behave as inductors within the frequency range . In this case the open-loop bandwidth of the TIA dominated by the pole, , can be alleviated by the active inductor.
Within the inductive region, can be modeled as an ideal inductor L in series with a passive resistor and with another resistor in parallel, as is shown in Fig. 3. Let be the transconductance of , we have
(6)
In order to increase the open-loop gain of the TIA, another current source is added in parallel to the active inductor. Since the tolerated input current level of the TIA is determined by , by the current injection technique, can be increased without sacrificing the TIA’s input dynamic range and degrading the input pole frequency. In addition, it mitigates dc drop of the active inductors. Thus, dual supplies are not required compared to the prior art in [5].
Assuming the equivalent impedances introduced by the ac-tive inductors ( , , ) and ( , ) are approximated
by and , and , , and
re-spectively represents the parasitic capacitance at the drain node
Fig. 3. Active inductor (MOS-L).
of , , and , the open-loop gain, , of the TIA can be approximated as (7) where (8) (9) (10) The closed-loop gain can be derived as
(11) where
(12) At critical damping, the 3-dB bandwidth of can be ex-tended to according to (11). In ad-dition, another zero at is introduced by inductive peaking, which can be placed at the roll-off region of to further enhance bandwidth.
Both the inductive peaking and current injection techniques are also applied in the buffer stage, which is a common source gain stage comprised of and . In contrast to a source follower buffer stage, it provides a moderate gain at a relatively low power dissipation. The buffer stage also functions
as an ADC, whose output common mode voltage is preset to the input common mode voltage of the LA by a local feedback loop. This ensures dc level tracking of the TIA and the LA despite of process and temperature variations. In this way, the sensitive signal paths can be on-chip directly coupled and no external coupling capacitor is required to avoid noise disturbance.
The price paid in the regulated cascode (RGC) input stage is the extra noise introduced by the RGC feedback amplifier. The input-referred noise can be derived as [6]
(13) (14) where is the noise factor of the MOSFETs, is the par-asitic capacitance at the input node, and respectively represent the total parasitic capacitance at the gate of and the drain of . To mitigate this drawback, the transconduc-tance of is chosen to be as large as possible to reduce the input-referred noise coming from and ’s thermal noise [6]. Additionally, the tail current source needs to be suf-ficiently large to tolerate the input dynamic range.
III. LIMITINGAMPLIFIER
Fig. 1 depicts the architecture of the LA, which is composed of a chain of gain cells, an offset cancellation circuit, a feedback low-pass filter, and a current mode output buffer to drive 50-output loads.
A. Architecture
For a LA design, how to determine the number of gain stages with gain-bandwidth tradeoffs and power optimization is an
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portant issue. Assuming each gain cell is identical and can be approximated by a two pole amplifier, then its conversion gain can be described by , where
(15) Here, denotes its small-signal dc gain, is the corre-sponding damping factor, and is the natural frequency. Thus, the 3-dB bandwidth of a single-stage amplifier can be derived as , where
(16) After stages gain cells are cascaded, the overall conversion gain becomes . The 3-dB bandwidth of the LA is re-duced to , where
(17) For a Butterworth response, we want to have . By substituting (16) into (17), the bandwidth requirement for a single-stage amplifier in terms of the cascaded amplifier’s
3-dB bandwidth can be derived as
(18) Also, the gain requirement of the individual stage, , in terms of the LA’s conversion gain, , can be expressed as
(19) Under the above assumptions, the unity-gain frequency for the individual stages in terms of the targeted and can be derived by substituting (19) and (17) into (15). Let
, we have
(20) For a common-source voltage amplifier with an input stage transconductance and a loading capacitor , the relation-ship between the achievable unity gain bandwidth and the dc biased current can be described as
(21) Thus, the estimated total power consumption of an -stage LA can be approximated by
(22) In this design, the TIA provides a conversion gain of 55 dB , and the LA provides a voltage gain of 42 dB. Both circuitries have a 3-dB bandwidth over 2 GHz for 2.5-Gbps operation. To obtain the optimum number of stages which will require
Fig. 4. Gain-bandwidth performance and power consumption versus number of stages.
the least power consumption, the simulated gain-bandwidth re-quirements and power consumption of LAs with various number of stages based on (22) are illustrated in Fig. 4. The gain-band-width product and power consumption are normalized to those of a single-stage amplifier for ease of comparison. The figure reveals that a 3-stage cascaded amplifier consumes minimum power. However, the required unity gain frequency for a single-stage amplifier would be as high as 7 GHz, which is difficult to achieve in this technology. As a compromise, we choose a 5-stage architecture for its unity gain frequency is more feasible ( 5 GHz).
In the above analysis, we use a 2-pole system to model a single-stage amplifier. Compared to a single pole model as were proposed in [11], [12], the bandwidth requirement estimated by (20) would be closer to meet the specifications.
B. Gain Cell
The core circuit of each gain cell is shown in Fig. 5, which is a source coupled pair with regulated cascode and inductive loads. The regulated cascode gain cell is free from Miller ef-fect, which prevents signal bandwidth from being severely de-teriorated when the gain cells are hooked up. On the other hand, input impedance of the common gate gain stage is reduced by the loop gain . Thus, the nondominant pole is further pushed to a higher frequency band for stability. Let be the parasitic capacitance at the drain of , be the parasitic capacitance at the drain of , be the parasitic capacitance at the drain of , and be the parasitic ca-pacitance at the drain of M9. is the single-stage small-signal dc gain, and denote the device size of , , and , . and represent the current flowing through input device and inductor load respectively, and
is the injected current provided by .
The conversion gain of each gain cell can be derived as
Fig. 5. LA core circuit input buffer. where (24) (25) (26) (27) It shows that the single-stage conversion gain is deter-mined by the ratio of device size and the current ratio of the input device with respect to the inductive load . To increase the conversion gain of each stage, another biased current and are injected in parallel with the active inductor. According to (24), can be enhanced by boosting . Incorporating active inductor with current injection, the conversion gain and signal bandwidth can be in-creased simultaneously.
Equation (27) shows that is the dominant pole frequency, is the zero introduced by the inductive load, and is contributed by the regulated cascode gain stages. Here dominant pole is lo-cated at the drain of and . By choosing to be close to , the 3-dB bandwidth of each gain stage can be extended by partially trim out the parasitic capacitance at the output node. The 3-dB bandwidth can be further enhanced by placing around the roll-off corner. The damping factor is chosen at the vicinity of 1 to avoid severe gain peaking.
The input stage of the LA is shown in Fig. 6, which plays an important role in isolating loading effects introduced by the loop
Fig. 6. LA input buffer and offset subtractor.
Fig. 7. Chip photograph of the optical receiver AFE.
Fig. 8. Measured gain response of the LA.
filter. The source coupled pair in the input stage is decomposed into 4 transistors so as to function as an input buffer and an offset subtractor simultaneously. The offset voltage derived from the low-pass loop filter is converted to a compensation current and is subtracted from the input signal at the input node of a regulated cascode gain stage. Also, the input stage translates the single-ended input signal to fully differential output voltages, thus the amplifier chain would have higher immunity to common-mode noise.
As shown in Fig. 1, the input-referred offset voltage of the LA is derived from its output common mode voltage by a second-order low-pass filter, and fed back to the offset subtractor at the input port. By this means, LA’s input-referred offset voltage is reduced by after offset compensation, where is the
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Fig. 9. (a) Photo diode with packaging parasitics. (b) Experimental setup for the receiver measuerment in the electrical domain.
closed-loop gain of the feedback network. The dominant pole of the loop filter is introduced by on chip resistors and an ex-ternal capacitor to save chip area and reduce the low cutoff fre-quency . Moreover, in this design, a replicated gain cell is cascaded in front of the low-pass filter. The gain cell in the feedback path isolates the capacitive loading introduced by the feedback filters from the output port.
IV. EXPERIMENTALRESULTS
The single-chip optical receiver AFE has been fabricated in a generic single-poly triple-metal 0.35- m digital CMOS tech-nology. The chip micrograph of the receiver is shown in Fig. 7. Chip size is m , which is limited by testing pads. The core circuit of LA occupies a chip area of m , and TIA occupies a chip area of m only. The chip area is mainly limited by test pads, and the two circuitries are separated by 400 m (as far as possible) to alleviate substrate noise coupling. Operating from a single 3-V supply, the total power consumption is about 99 mW.
Also, individual TIA and LA test kits have been built up to characterize their performance in detail. Both the circuits are measured using network analyzer. The transimpedance gain and voltage gain of the receiver are derived from S-parameters. The TIA has a 3-dB bandwidth over 2.2 GHz with a conversion gain of about 54.5 dB [4]. The measured gain response of LA is shown in Fig. 8. The of LA is 2.2 GHz and the conver-sion gain is about 42 dB, while the low cutoff frequency is about 100 kHz.
The intersymbol interferene (ISI) induced timing jitter of the receiver front-end is estimated by [15]
(28)
For rad/s, ns, the is
about 0.3 ps, which is almost negligible in a 2.5-Gbps applica-tion.
The transient characteristic of the optical receiver
is measured in the electrical domain. Fig. 9(a) shows the equivalent ac circuits for a 10 Gbps p-i-n photodetector [14], and Fig. 9(b) illustrates the experimental setup and its parasitic components. Here the ac coupled capacitor is about 0.1 F. The 50- resistor is utilized for impedance matching. On the other hand, the 2-k resistor, which is much larger than the input impedance of the TIA, is utilized to convert external voltage ex-citation into input current. The parasitic capacitance introduced by the surface mount RC devices at the input of the receiver is
Fig. 10. Measured eye diagram @1.25 Gbps,x-axis = 260 ps/div, y-axis = 50 mV/div.
modeled by , which is about 0.3 pF and can be treated as the parasitic capacitance of a photo detector. and represent the inductance and series resistance of the bonding wire, which are about 3 nH and 0.3 respectively. denotes the parasitic capacitance of the bonding pad, which is about 0.05 pF.
The measured input sensitivities for bit-error rate (BER) at are about 12.6 and 6.5 A, respectively, for 2.5- and 1.25-Gbps operations. The input sensitivity for BER less than is estimated by extrapolation using the function [15]. As
(29) Here, denotes the input photo current, and is the rms noise current at the receiver input, including the input-re-ferred noise of the optical receiver and external noise distur-bance. The corresponding input sensitivities of the optical re-ceiver at a BER of less than are about 8 and 16 A, re-spectively, for 1.25- and 2.5-Gbps operations. When the input current is a test pattern, the measured eye dia-grams at 1.25 Gbps A and 2.5 Gbps A are shown in Figs. 10 and 11, respectively. The LA’s output swing is limited to 250 mV (single-ended, 500 mV differ-ential) in both cases. The input dynamic range of the receiver AFE is limited by the RGC input stage of the TIA. The mea-sured input-referred noise current of the receiver front-end is
Fig. 11. Measured eye diagram @ 2.5 Gbps, x 0 axis = 130 ps/div, y 0 axis = 50 mV/div.
about 0.8 A within 2.5-GHz noise bandwidth using spec-trum analyzer.
V. CONCLUSION
This paper describes the design of a 2.5-Gbps optical receiver AFE circuit in a low-cost digital CMOS process. Integrating both TIA and LA in a single chip, the front-end amplifier enlarges a 16 A photo current at 2.5 Gbps to a 250 mV (single-ended) logic swing. To achieve both high gain and wide bandwidth simultaneously, several gain-bandwidth enhancement techniques have been explored to boost overall performance. Instead of using bulky spiral inductors, active inductors are utilized in this design. Thus, the chip area can be greatly reduced. The proposed architecture is suitable for low-cost application.
ACKNOWLEDGMENT
The authors would like to thank CIC for chip manufacturing. and NSC, ITRI/STC, and MediaTek Inc. for funding support.
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Wei-Zen Chen was born in Yun-Lin, Taiwan, R.O.C., in 1970. He received the B.S., M.S., and PhD degrees in electronics engineering from Na-tional Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., in 1992, 1994, and 1999, respectively.
After graduation, he worked for Industrial Tech-nology Research Institute (ITRI), Hsin-Chu, T to –2002, he was with the department of Electrical Engineering, National Central University, Chung-Li, Taiwan, R.O.C. In 2002, he joined the Department of Electronics Engineering, National Chiao-Tung University, where he is currently an Assistant Professor. His research interests are integrated circuits and systems for high-speed networks and wireless communications.
Dr. Chen is a member of Phi Tau Phi.
Chao-Hsin Lu was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees in electrical engineering from the National Central University, Taiwan, R.O.C., in 1999 and 2001, respectively.
In 2001, he joined the Analog Department Center of Realtek Semiconductor Corporation, Taiwan, R.O.C., Since then, he has been engaged in the research and development of CMOS analog design for liquid crystal display application.
