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VI. CONCLUSION
This paper has detailed our experience in developing an energy-ef-ficient MPEG-2 audio/video decoder, which we have since publicly distributed in source form [1]. Aware that FPGAs are inherently en-ergy-inefficient, in this paper we have stressed that the efficiency gains we have made are at the architectural level, providing benefits regard-less of the choice of implementation technology.
ACKNOWLEDGMENT
The authors would like to acknowledge the technical contributions of P. Kinsman and J. Thong, as well the equipment contributions from Canadian Microelectronics Corporation [3] (CMC).
REFERENCES
[1] A. B. Kinsman, H. F. Ko, and N. Nicolici, “Release of Verilog design files for MP3 audio and MPEG2 audio/video,” 2007. [Online]. Avail-able: http://www.ece.mcmaster.ca/~nicola/mpeg.html
[2] K. H. Bang, N. H. Jeong, J. S. Kim, Y. C. Park, and D. H. Youn, “Design and VLSI implementation of a digital audio-specific DSP core for MP3/ AAC,” IEEE Trans. Consumer Electron., vol. 48, no. 3, pp. 790–795, Aug. 2002.
[3] CMC, Kingston, ON, Canada, “Canadian microelectronics corporation (CMC),” 2006. [Online]. Available: http://www.cmc.ca/
[4] C.-D. Chien, K.-P. Lu, Y.-M. Chen, J.-I. Guo, Y.-S. Chu, and C.-L. Su, “An area-efficient variable length decoder IP core design for MPEG-1/2/4 video coding applications,” IEEE Trans. Circuits Syst. for Video Technol., vol. 16, no. 9, pp. 1172–1178, Sep. 2006. [5] A. Cugnini and R. Shen, “MPEG-2 video decoder for the digital HDTV
grand alliance system,” IEEE Trans. Consumer Electron., vol. 14, no. 3, pp. 748–753, Aug. 1995.
[6] L. Feng, G. Rui, S. Shu, and C. Xu, “HW/SW co-design and implemen-tation of multi-standard video decoding,” in Proc. Workshop Embed. Syst. for Real Time Multimedia, 2006, pp. 87–92.
[7] S.-C. Han, S.-K. Yoo, S.-W. Park, N.-H. Jeong, J.-S. Kim, K.-S. Kim, Y.-T. Han, and D.-H. Youn, “An ASIC implementation of the MPEG-2 audio decoder,” IEEE Trans. Consumer Electron., vol. 42, no. 3, pp. 540–545, Aug. 1996.
[8] International Organization for Standardization, Geneva, Switzerland, “Information Technology—Generic Coding of Moving Pictures and Associated Audio Information: Parts 1–3,” ISO/IEC 13818, 2000. [9] K. Kohiyama, H. Shirai, K. Ogawa, A. Manakata, Y. Koga, and M.
Ishizaki, “Architecture of MPEG-2 digital set-top-box for CATV VOD system,” IEEE Trans. Consumer Electron., vol. 42, no. 3, pp. 667–672, Aug. 1996.
[10] Mentor Graphics, Wilsonville, OR, “MentorGraphics,” 2005. [Online]. Available: http://www.model.com/
[11] F. Shafait, M. Usman, A. ul Hassan, H. Jamal, and S. A. Khan, “Ar-chitecture for 2-D IDCT for real time decoding of MPEG/JPEG com-pliant bitstreams,” in Proc. Int. Conf. Microelectron. (ICM), 2005, pp. 229–233.
[12] R. Swamy, M. Khorasani, Y. Liu, D. Elliott, and S. Bates, “A fast, pipelined implementation of a two-dimensional inverse discrete cosine transform,” in Proc. Canadian Conf. Elect. Comput. Eng., 2005, pp. 665–668.
[13] T.-H. Tsai, C.-N. Liu, and Y.-W. Wang, “A pure-ASIC design approach for MPEG-2 AAC audio decoder,” in Proc. Int. Conf. Inf., Commun. Signal Process., 2003, pp. 226–230.
[14] Xilinx Incorporated, San Jose, CA, “Xilinx multimedia board,” 2004. [Online]. Available: http://www.xilinx.com/products/boards/multi-media/
[15] Y. Ye, L. Yuanjiu, and S. kaixiong, “Architecture and software imple-mentation of HDTV video decoder on a singlechip, MPEG decoder,” in Proc. Int. Conf. Comput. Graphics, Imag. Visualisation, 2006, pp. 226–230.
[16] A. Zemva and M. Verderber, “FPGA-oriented HW/SW implementation of the MPEG-4 video decoder,” Microprocessors Microsyst., vol. 31, no. 5, pp. 313–325, Aug. 2007.
A Digitally Testable Modulator Using the Decorrelating Design-for-Digital-Testability
Sheng-Chuan Liang and Hao-Chiao Hong
Abstract—This paper demonstrates a digitally testable second-order 6 0 1 modulator. The modulator under test (MUT) employs the
decorrelating design-for-digital-testability(D T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of theD T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a6 0 1 modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same6 0 1 modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, theD T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the03.2 dBFS test. The analog hardware overhead of the
D T MUT only consists of 13 switches.
Index Terms—Analog-to-digital conversion (ADC), built-in self-test
(BIST), design-for-testability (DfT), integrated circuit testing, mixed-mode circuit, Sigma-Delta modulation.
I. INTRODUCTION
Testing 6 0 1 modulators is very costly by conventional func-tional tests because of expensive automatic test equipment (ATE), a long test time, and a low-noise testing environment [1]. To reduce the test cost of the analog-to-digital converter (ADC), many de-sign-for-testability (DfT), and built-in-self-test (BIST) techniques for ADCs have been proposed [2]–[11]. Most of the state-of-the-art works are functional-test based to provide must-have results for industry such as signal-to-noise ratio (SNR) and signal-to-noise-and-distortion ratio (SNDR) [12]. They also have purely digital input/output (I/O) during testing since digital signals have large noise margins against environmental noise and interference. To digitize the I/O, the com-pulsory analog stimulus generator (ASG) for conducting functional tests can not but be embedded. As a result, the test accuracy of the DfT/BIST heavily relies on the performance of the embedded ASG. Xing et al. proposes a histogram-based BIST strategy that can use a low-resolution ASG to characterize the transition levels of the ADC under test [13].
A robust approach to realize the embedded ASG is applying a601 modulated bit-stream to a one-bit DAC followed by an analog anti-aliasing filter (AAF) [2], [3]. The single-bit characteristic of the6 0 1 modulated bit-stream ensures that the generated analog stimulus is purely linear as far as the AAF is linear.
Manuscript received May 22, 2009; revised September 15, 2009. First pub-lished December 11, 2009; current version pubpub-lished February 24, 2011. This work was supported in part by the National Science Council, Taiwan, R.O.C. under Grant NSC96-2221-E009-232.
The authors are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: scliang.ece93g@nctu. edu.tw; hchong@cn.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2009.2035508 1063-8210/$26.00 © 2009 IEEE
Fig. 1. Schematic of the proposedD T second-order 6 0 1 modulator.
Based on the similar idea of testing the ADC with a6 0 1 mod-ulated bit-stream, we proposed a design-for-digital-testability (DfDT) 601 modulator design in [14]. The DfDT 601 modulator is digitally testable with a601 modulated bit-stream and needs no AAF. Exper-imental results show that the DfDT design has low area overhead, high fault observability, good test accuracy, and is at-speed testable. How-ever, the SNDR result of the digital test degrades if the stimulus tone level exceeds06 dBFS. The digital and the corresponding analog test results can have an SNDR difference as high as 12 dB at an oversam-pling ratio (OSR) of 128 [14]. The major issue of the DfDT tests in [14] is that the digital stimuli are6 0 1 modulated bit-streams. They contain significant out-of-band shaped quantization noise which is ab-sent in their analog counterparts. The digital stimulus’ shaped noise correlates to the shaped noise generated by the modulator under test (MUT) and raises the inband noise power. As a result, DfDT tests al-ways report lower SNDR results than their analog counterparts do. The digital stimulus’ shaped noise also overloads the MUT at a higher stim-ulus tone level. Thus, the DfDT tests present a lower peak SNDR than analog tests do.
Reference [15] proposed a decorrelating design-for-digital-testa-bility (D3T) scheme for 6 0 1 modulators to improve the test accuracy of digital tests. The D3T design realizes an intrinsic fi-nite-impulse-response (FIR) low-pass filter (LPF) to filter the digital
stimulus. This additional LPF mitigates the undesired shaped noise of the digital stimulus and thus enhances the test accuracy. Behavioral and circuit simulation results verify that theD3T tests are superior to the DfDT ones.
To more solidly validate theD3T scheme and to evaluate its practical performance, we demonstrate experimental results of a second-order modulator with theD3T scheme in this brief. Section II describes the design of the proposedD3T second-order 601 modulator. Measure-ment results are shown in Section III. Finally, Section IV concludes this work.
II. DESIGN OF THED3T SECOND-ORDER6 0 1 MODULATOR Fig. 1 shows the schematic of the proposedD3T second-order 601 modulator. It is derived from the schematic of the DfDT modulator in [14] by splitting the original DfDT structure into two copies as shown by the shaded area of Fig. 1. In this way, the proposedD3T design has a decomposition number of two so as not to increase too much additional KT=C noise to the digital test results [15]. Note that the proposed implementation requires only one reference(VREF), while the design in the [15] requires two reference voltage sources (includingVREF+ andVREF0). It saves the area and the power of an additional reference generator. TheD3T MUT has two operation modes.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011 505
1) Normal Mode: When the test mode control pinT is set to zero and the stimulus input pinsDij(z), j 2 f0; 1g are fixed at one, the MUT operates in the normal mode. This setup turns off the switches S1j toS5j, wherej 2 f0; 1g. The configured MUT accepts the test stimulus from the primary analog inputsVi+andVi0. TheD3T MUT operates as a normal second-order6 0 1 modulator does.
LetYo 2DO 0 1 be the normalized output of the MUT and Vi(z) = VREFXASG(z). The normalized I/O relationship of the MUT in the normal mode can be shown to be
Yo(z) = STFMUT(z)XASG(z) + NTFMUT(z)EMUT(z) (1) whereSTFMUT(z), XASG(z), NTFMUT(z) and EMUT(z), stand for the signal transfer function (STF), the normalized test stimulus, the noise transfer function (NTF), and the quantization noise of MUT, respectively.
2) Digital Test Mode: By setting the digital test mode control pin T to one, the MUT operates in the digital test mode. In this mode, the switchesSAj,SBj, andSEj forj 2 f0; 1g are off. The D3T switched-capacitor network, indicated by the shaded area in Fig. 1, is reconfigured as two differential digital-to-charge converters (DCCs). Each of the DCCs accepts the corresponding single-bit digital stimulus Dij as its input. The two DCCs convert the digital stimuli into two charge signals and the following integrator sums up the charge signals as the analog test stimulus in the digital test mode. The rest of the MUT convert the analog test stimulus into a6 0 1 modulated output DOas if they were in the normal mode. Because both the DCCs are single-bit, the generated analog test stimulus is nonlinearity-free. Hence, theD3T MUT can achieve high test accuracy.
The required two digital stimuliDijare the same6 0 1 modulated bit-streams except for a relative delayn [15]. We adopted the feed-forward, single-bit, third-order6 0 1 modulator in [16] as our bit-stream generator (BSG) which modulates the normalized test stimulus XASG(z) to generate Dij. Note that this BSG inherently can not accept a stimulus tone level higher than03 dBFS; otherwise, the BSG will not be stable. The limited input level is a common restriction of high-order, single-bit6 0 1 modulator designs [16].
LetSTFBSG(z), NTFBSG(z), and EBSG(z) represent the STF, the NTF, and the quantization error of the software BSG, respectively. Without loss of generality, the normalized digital stimuliYij 2Dij0 1, j 2 f0; 1g can be shown to be
Yi0(z) = STFBSG(z)XASG(z) + NTFBSG(z)EBSG(z)
Yi1(z) = z0nYi0(z): (2)
We chooseCS0+ = CS1+ = CS00 = CS10in this design so as to achieve the best shaped noise attenuation [15]. The normalized I/O relationship of theD3T MUT in the digital test mode thus becomes
Yo(z) = HDCR(z)STFMUT(z)STFBSG(z)XASG(z) + HDCR(z)STFMUT(z)NTFBSG(z)EBSG(z)
+ NTFMUT(z)EMUT(z) (3)
where the decorrelating term is defined as
HDCR(z) (1 + z 0n)
2 : (4)
Equation (3) indicates that theD3T test can attenuate the digital stim-ulus’ shaped noise as our desire sinceHDCR(z) is actually an FIR LPF.
Fig. 2. Micrograph of the decorrelating DfDT second-order601 modulator. This decorrelating term puts real zeros on the frequencies ofm=nfclk, m n and these zeros attenate the shaped noise around them. We can tune the relative input delayn in (4) to achieve the best test accuracy. On the contrary,HDCR(z) usually has negligible impacts on the stim-ulus term of (3). It is because the MUT operates at a large oversampling ratio (OSR) and thus the zeros ofHDCR(z) are far from the passband for a moderaten.
TheD3T MUT only consists of three active components: two op-erational transconductance amplifiers (OTAs) and a comparator. The OTAs of this design are similar to the folded-cascode OTA used in [14]. Circuit simulation results show that our OTA achieves an open-loop gain of 87.7 dB, a phase-margin of 68 degrees, and a unit-gain band-width of 100 MHz.
On the other hand, the design of the comparator is not as critical because the noise and the distortion generated by the comparator will be attenuated by the6 0 1 modulation loop. This work uses a simple latch-type comparator.
III. EXPERIMENTALRESULTS
TheD3T MUT has been fabricated in a 0.18-m 1.8/3.3 V mixed-mode CMOS process through the service of the Chip Implementation Center (CIC), Taiwan. The analog parts are realized by 3.3 V devices, while the digital circuits are realized using 1.8 V devices. Fig. 2 shows the micrograph of theD3T 6 0 1 modulator. The active area of the D3T MUT is 310 378 m2. The total area of the additional analog switches and the control-signal generator for theD3T scheme is less than 1200m2. All the additional circuits are placed on the free space of the layout, resulting in no area overhead.
The following measurements are all single-tone tests. The stimulus tone has a level of04 dBFS and a frequency of 23/128 k times the sampling frequency unless otherwise noted. Each of the digital stimuli is a 128 k-sample bit-stream which is cyclicly applied to the MUT. The sampling frequency and the OSR are set to 6.144 and 128 MHz, respectively, corresponding to a passband of 24 kHz. The minimum four-term window is applied to derive all spectra.
A. Choice of the Relative Input Delay
Fig. 3 shows the measured SNDR results with variousn. We also added the measurement result of the corresponding analog test as a reference. The digital-test-mode-enabled D3T MUT has the lowest SNDR, 75.9 dB, whenn = 0. In fact, setting n to zero turns the decor-relating term of theD3T MUT to one and thus disables the LPF capa-bility of the decorrelating term. In other words, theD3T MUT degen-erates into a DfDT one. Consequently, the shaped correlation between the MUT and the digital stimulus becomes higher and degrades the measured SNDR.
The SNDR result closest to that of the analog test is 80.1 dB whenn equals 4. This value is 4.2 dB higher than the DfDT case(n = 0). Further increasing n does not improve the test accuracy because a largern narrows the attenuation bands of the zeros of the decorre-lating term. Consequently, some significant high-frequency spurs of the digital stimuli may not be effectively suppressed. Fig. 3 also shows
Fig. 3. Measured SNDR results of theD T tests with various relative input delays. The stimulus tone level is04 dBFS.
Fig. 4. Measured SNDR versus stimulus tone level.
the measurement results of 23 kHz tests. The highest SNDR occurs at n = 4 as well. It shows that the best n seems to be stimulus frequency independent.
We measured all the five samples we had. Four of them achieve their highest SNDRs whenn = 4. Only one sample achieves its peak SNDR atn = 6. Yet the n = 4 test gives the second highest SNDR for this exclusive sample. The SNDR difference between the two tests is only 0.2 dB.
B. Dynamic Range Tests
Fig. 4 shows the measured SNDRs of the MUT at different stimulus tone levels. We sweep the stimulus tone level from060 to 03.2 dBFS. TheD3T tests are set with the same relative input delay of 4. In partic-ular, we add the measurement results of the degenerated DfDT MUT (settingn = 0) as references to demonstrate the effectiveness of the D3T scheme. The measurement results show that the D3T test results are very close to their analog counterparts.
The dynamic range (DR) obtained by theD3T test is 85.2 dB. This value is very close to the normal mode test result which is 86.6 dB. The peak SNDRs of theD3T test and the DfDT test are 80.1 dB and
Fig. 5. SNDR difference versus stimulus tone level.
Fig. 6. Measured output spectra of the04 dBFS analog test and the 04 dBFS D T test.
77.3 dB which occur at04 dBFS and at 06 dBFS, respectively. The D3T test successfully extends the peak stimulus tone level of the digital tests by 2 dB. Fig. 5 plots the measured SNDR differences between the analog tests and the corresponding digital ones to compare both tests with each other. TheD3T tests outperform their DfDT counterparts in most cases. In the range of060 to 04 dBFS, the maximal SNDR difference between theD3T tests and the corresponding analog ones is less than 1.9 dB.
On the contrary, the DfDT SNDR results diverse from the corre-sponding analog ones more severely as the stimulus tone level ap-proaches the full scale. Within the same060 to 04 dBFS range, the peak SNDR difference between the DfDT and the analog tests is as high as 5.9 dB. As has been discussed in Section I, the large shaped noise of the digital stimulus leads to the increased SNDR differences [15].
The03.2 dBFS D3T test reports an SNDR that differs from the corresponding analog test result by 3.6 dB. It is because such a large stimulus severely overloads the MUT, though the decorrelating term alleviates the shaped noise of the digital stimulus. Nevertheless, the D3T test still achieves 6.7 dB improvement over the corresponding DfDT test.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011 507
Fig. 7. Measured SNDR versus stimulus frequency. The stimulus tone levels are all04 dBFS.
TABLE I PERFORMANCESUMMARY
Dynamic range SNDR @-60 dBFS (in dB) + 60 dB [17]. : Test results of the04 dBFS, 1 kHz tests.
: For the stimulus tone levels within04 dBFS.
Fig. 6 compares the output spectrum of the04 dBFS D3T test with that of the corresponding analog test. The two spectra are similar to each other, but show different offset values for the same MUT. The offset reported by the digital test is more accurate since the offset is de-termined by the MUT itself. While the ASG, the analog buffers on the evaluation board, and the MUT contribute the measured offset together in the analog test. The SNDR difference between the two tests in Fig. 6 is less than 1.6 dB. However, the spectrum of the analog test shows no significant harmonic tone within the passband, whereas theD3T test reports some. This is because the input power of the04 dBFS D3T test is higher than that of the analog test owing to the residue shaped noise of the digital stimulus. This higher input power somewhat over-loads the digital-test-mode-enabled MUT and results in the harmonics. A solid evidence for our argument is that these harmonics almost dis-appear in the output spectrum of the05 dBFS D3T test.
C. Full Power Bandwidth Tests
Fig. 7 illustrates the measured SNDR values of the MUT vs. stimulus frequency. TheD3T tests show better correlation to the analog tests than the DfDT tests do over the whole passband. When the stimulus frequency is 23 kHz, the measured SNDR results of the analog, the D3T and the DfDT tests are 81.8, 80.5, and 74.9 dB, respectively. The experimental results reveal that theD3T digital tests can be used to test the full power bandwidth of the MUT with good test accuracy.
Table I summarizes the performance of theD3T second-order 6 0 1 modulator. The MUT receives the largest input power in the DfDT test and thus is overloaded the most severely. As a result, the DfDT test presents the worst SFDR. TheD3T test gives a closer SFDR to that of the analog test because its decorrelating term reduces the digital stimulus’ shaped noise power.
IV. CONCLUSION
This paper demonstrates aD3T second-order 601 modulator fab-ricated in 0.18-m CMOS. Measurement results show that the D3T digital tests report a peak SNDR of 80.1 dB for the MUT, which is 2.8 dB better than the result obtained by the DfDT tests. At an OSR of 128, theD3T tests and their analog counterparts have SNDR differ-ences less than 2 dB when the stimulus tone level is not higher than04 dB. The analog hardware overhead of theD3T design only consists of 13 switches, which is negligible. TheD3T design also ensures high fault observability because most of the MUT’s components are active and have the same functions and loads in both the modes.
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