IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 9, SEPTEMBER 2005 667
Threading Dislocation Induced Low Frequency
Noise in Strained-Si nMOSFETs
W.-C. Hua, M. H. Lee, P. S. Chen, M.-J. Tsai, and C. W. Liu, Senior Member, IEEE
Abstract—The correlations between the threading
disloca-tions and the low-frequency noise characteristics of the n-type strained-Si field-effect transistors are studied using the devices with different sizes. The device-area-dependent VG (power spectral density of the gate referred voltage noise) ratio of the strained-Si devices over the control Si devices obtained form geometric average can be understood by the modified carrier number fluctuation model with excess traps from the Poisson distributed threading dislocations. The equivalent trap number per threading dislocation extracted from the area-dependent VG ratios is 85 for the strained-Si devices, and which results in 4.2X degradation of the VGfor the strained-Si device with the device area of 625 m2.
Index Terms—Flicker noise, MOSFET, strained-Si, threading
dislocation.
I. INTRODUCTION
D
UE to its enhanced current drive and high-frequency performances [1]–[3], the strained-Si technology is un-doubtedly one of the enabling technologies for RF circuit applications. Although the enhanced cutoff frequency of the strained-Si MOSFET [3] can facilitate the RF CMOS circuit design, the unintentionally induced threading dislocations in the strained-Si channel can potentially degrade some RF cir-cuits. Although the threading dislocations in the strained-Si channel may lead to different electrical properties, few litera-tures are reported regarding this issue. In this letter, the flicker noise characteristics for both the strained-Si and the control Si devices with different sizes are investigated to clarify the correlations between the threading dislocations and the flicker noise characteristics.II. DEVICEFABRICATION
Fig. 1 shows the schematic diagrams of the device structures of the strained-Si nMOSFETs with and without threading dislo-cations in the channel. The 20-nm strained-Si channel is grown
Manuscript received May 9, 2005; revised June 13, 2005. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract 93-2215-E-002-003 and Contract 93-2120-M-007-008. The review of this letter was arranged by Editor E. Sangiorgi.
W.-C. Hua is with the Department of Electrical Engineering and Graduate In-stitute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
M. H. Lee, P. S. Chen, and M.-J. Tsai are with the Electronics Research & Service Organization, Industrial Technology Research Institute (ERSO/ITRI), Hsinchu 300, Taiwan, R.O.C.
C. W. Liu is with the Department of Electrical Engineering and Graduate In-stitute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, R.O.C, and also with the Electronics Research and Service Organization, Indus-trial Technology Research Institute (ERSO/ITRI), Hsinchu 300, Taiwan, R.O.C. (e-mail: chee@cc.ee.ntu.edu.tw).
Digital Object Identifier 10.1109/LED.2005.853672
Fig. 1. Schematic diagrams of the strained-Si device structures. (a) A large-area device with threading dislocation in the channel. (b) A small-area device with the dislocation-free channel.
epitaxially on the relaxed 1- m Si Ge layer and the 1- m graded Si Ge buffer from to 0.2 by ultrahigh-vacuum chemical vapor deposition. The tensile strain in the channel is 0.64%, measured by the surface Raman spectroscopy [4] and increases to 0.7% after the device process. Low-temperature (700 C) deposited tetraethylorthosilicate gate oxide (30 nm) is used to avoid the high-temperature thermal oxidation-enhanced Ge outdiffusion [5]. The effect of the Ge outdiffusion on the flicker noise is negligible. The output characteristics of the strained-Si devices m show 78% and 35% enhancements of at constant overdrive at the linear and the saturation region, respectively. The effective mobility of the strained-Si device is extracted from the drain current and the split capacitance–voltage [6] measurements on the large-area devices m , and has a 65% enhancement at the effective normal field of 1.0 MV/cm [3].
III. RESULTS ANDDISCUSSION
Fig. 2 shows the surface morphology of the strained-Si film after defect-etching [7]. The density of threading dislocations of the strained-Si film is m . The existence of the threading dislocations in the strained-Si channel is also con-firmed by the transmission electron microscopy on the large-area device. Fig. 3(a) and (b) shows the statistical of the strained-Si and the control Si devices at 30 Hz with m for different gate width, and m for different gate lengths. All the devices are biased at V with con-stant gate overdrive V at the saturation region. The statistical results are obtained from the geometric average of the measured for ten to 20 devices. The geometric average
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668 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 9, SEPTEMBER 2005
Fig. 2. Surface morphology of the strained-Si channel layer after defect-etching. The black points are the threading dislocations and the density of threading dislocations is 10 cm (10 m ).
Fig. 3. Statistical result ofS of the strained-Si and the control Si devices at 30 Hz. The error bars stand for the geometric standard deviations of theS (obtained from the arithmetic standard deviation of thelog(S )): (a) L = 0:8 m for various gate widths (b) W = 25 m for various gate lengths.
method shows lower error [8] and can fit the distribution of large number of noise measurements more precisely than the arith-metic average [9]. In Fig. 3(a), the of both the strained-Si and the control Si devices are approximately inversely propor-tional to the channel width and are consistent with the carrier number fluctuation model [10]–[13] of the nMOSFET biased at saturation, which is given by
(1) where is the electron charge, is the equivalent oxide trap per unit area and is assumed to be independent of gate bias, is the oxide capacitance per unit area, is the gate width, is the gate length, and is the frequency. The validity of the carrier number fluctuation model is confirmed by extracting the ( to cm ) at various gate bias in the saturation region ( to 0.5 V, V) for the control Si devices. The is nearly independent of gate bias at saturation region for the nMOSFETs [12], [13]. Although all the device areas in Fig. 3(a) are smaller than 100 m , there are still some chances to have dislocations in the strained-Si chan-nels. Thus, the of the strained-Si devices are slightly higher than the control Si devices in Fig. 3(a). In Fig. 3(b), the statis-tical of the control Si devices are inversely proportional to the channel length, but the of the strained-Si devices
Fig. 4. Measured and calculatedS ratio of the strained-Si devices over the control Si devices for various device sizes. The calculation of theS ratio is based on the Poisson distributed threading dislocations.
shows an increasing degradation as compared to the control Si devices as the channel length increases. The threading dislo-cations in the channel may act as the trap centers, which play the similar role as the Si/oxide interface trap and increase the of the strained-Si devices. The effect of the dislocations on the can be quantitatively characterized by the Poisson dis-tributed threading dislocations. The probability density function of having n dislocations in an area of m for the strained-Si device is given by
(2) where is the average number of the dislocations in an area of m . From the defect etching experiment, is given by . The equivalent total trap number per unit area for the strained-Si device with n dislocations in the channel is given by
(3) where is the equivalent trap number per dislocation. The geometric average of the of the strained-Si device
with device area of m is given by
(4) where is the of the control Si device with the device area of m . Fig. 4 shows the measured and the calculated ratios of the strained-Si devices over the control Si devices with different sizes for both rectangular and ring FETs. The calculated ratios are area-dependent since presents in the power term in (4). Only the first 20 terms in (4) are significant in the practical calculation of ratios in Fig. 4. Significant degradation of the strained-Si devices as compared with the control Si devices are found for the de-vice area larger than 100 m . The is 85 extracted by fitting the ratios in Fig. 4 using (4). The equivalent total trap number per unit area for the strained-Si can be obtained by multiplying the cm of the con-trol Si device by the ratios in Fig. 4. According to the pro-posed model, the calculated ratio has a saturation value
HUA et al.: THREADING DISLOCATION INDUCED LOW FREQUENCY NOISE 669
of 4.5 when the device area is very large, and which is very close to the ratio derived from the conventional approach
m cm .
IV. CONCLUSION
The excess flicker noise induced by the threading dislocation shows a device-area-dependent behavior and which is different as compared to the behavior of the in unstrained Si nMOS-FETs. This phenomenon can be quantitatively characterized by the Poisson distributed threading dislocations with geometric average of the measured . In order to take advantage of the enhanced performance of the strained-Si MOSFET and main-tain the flicker noise performance, the devices with lower den-sity of threading dislocations in the channel is required.
ACKNOWLEDGMENT
The authors would like to thank Dr. K. M. Chen from the RF Group, National Nano Device Laboratories, Hsinchu, Taiwan, R.O.C., for the flicker noise measurement.
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